Sylpheed/tools/ppc-manual/memory/lswi.md

lswi — Load String Word Immediate

Category: Memory · Form: X · Opcode: 0x7c0004aa

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
lswi	lswi	—	Load String Word Immediate

Syntax

(no disassembly template)

Encoding

lswi — form X

• Opcode word: 0x7c0004aa
• Primary opcode (bits 0–5): 31
• Extended opcode: 597
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RT/FRT/VRT	destination
11–15	RA/FRA/VRA	source A
16–20	RB/FRB/VRB	source B
21–30	XO	extended opcode (10 bits)
31	Rc	record-form flag

Operands

Field	Role	Description

Register Effects

lswi

• Reads (always): none
• Reads (conditional): none
• Writes (always): none
• Writes (conditional): none

Status-Register Effects

No condition-register or status-register effects.

Operation (pseudocode)

; No hand-written pseudocode for this instruction yet.
; The authoritative semantics are the Canary emitter snapshot under
; Implementation References; about half of Canary's emitters open
; with the PPC-style definition as a comment (`RD <- (RA) + (RB)`).
; Every side effect is also enumerated in the Register Effects and
; Status-Register Effects tables above.

C Translation Example

/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

lswi

• Canary XML: tools/ppc-instructions.xml — search for mnem="lswi"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_memory.cc:727
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:133
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:939

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_lswi(PPCHIRBuilder& f, const InstrData& i) {
  XEINSTRNOTIMPLEMENTED();
  return 1;
}

Special Cases & Edge Conditions

• Byte-granular bulk load. Reads NB bytes starting at EA and packs them, big-endian, into successive GPRs starting at RT. Each filled GPR holds 4 bytes in its low word; partial last words are left- (most-significant-byte-) aligned with trailing zero bytes. The byte count NB is held in the RB field of the instruction encoding (1..31), with the special case NB = 0 meaning "32 bytes".
• Register wraparound at r31 → r0. If the byte count is large enough to spill past r31, the next register is r0, then r1, etc. AIX docs flag the "RA in destination range" and "RB in destination range" cases as invalid. ⚠️ Canary does not implement lswi: its emitter is XEINSTRNOTIMPLEMENTED, so translating one logs "Unimplemented instr" and, with the default break_on_unimplemented_instructions, breaks.
• RA0 semantics. RA = 0 selects literal zero. There is no RA post-write — lswi is not an update form.
• Big-endian byte ordering inside each word. First byte read goes into bits 0–7 of the destination GPR (most-significant byte). There is no Canary behaviour to compare: it does not implement lswi.
• Last partial word. When NB is not a multiple of 4, the final GPR's unused low bytes are zero. The high bits remain whatever the load placed there.
• Alignment. The architecture allows arbitrary alignment, but real implementations may take alignment exceptions on cache-inhibited storage. Canary does not implement lswi (XEINSTRNOTIMPLEMENTED), so there is no Canary behaviour to compare.
• Vanishingly rare in compiled code. Compilers don't emit lswi. Hand-written memcpy cores from the PowerPC SDK era used it for short copies; otherwise it appears mostly in byte-string init helpers.

Related Instructions

• lswx — register-supplied byte-count variant.
• stswi, stswx — symmetric stores.
• lmw — word-granular bulk load (multiple of 4 bytes only, no register wrap).
• lwz, lbz — scalar loads that compilers emit instead.

IBM Reference

• AIX 7.3 — lswi (Load String Word Immediate)
• PowerISA v2.07B Book II § "Load and Store String" for the invalid-form checks.