Sylpheed/tools/ppc-manual/alu/nandx.md

nandx — NAND

Category: Integer ALU · Form: X · Opcode: 0x7c0003b8

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
nand	nandx	—	NAND
nand.	nandx	Rc=1	NAND

Syntax

nand[Rc] [RA], [RS], [RB]

Encoding

nandx — form X

• Opcode word: 0x7c0003b8
• Primary opcode (bits 0–5): 31
• Extended opcode: 476
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RT/FRT/VRT	destination
11–15	RA/FRA/VRA	source A
16–20	RB/FRB/VRB	source B
21–30	XO	extended opcode (10 bits)
31	Rc	record-form flag

Operands

Field	Role	Description
RS	nandx: read	Source GPR (alias for RD in some stores).
RB	nandx: read	Source GPR.
RA	nandx: write	Source GPR (r0–r31).
CR	nandx: write (conditional)	Condition-register update. When Rc=1, CR field 0 (or CR6 for vector compares, CR1 for FPU) is updated from the result.

Register Effects

nandx

• Reads (always): RS, RB
• Reads (conditional): none
• Writes (always): RA
• Writes (conditional): CR

Status-Register Effects

• nandx: CR0 ← signed-compare(result, 0) with SO ← XER[SO], when Rc=1.

Operation (pseudocode)

RA <- ~((RS) & (RB))

C Translation Example

/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

nandx

• Canary XML: tools/ppc-instructions.xml — search for mnem="nandx"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_alu.cc:753
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:196
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:927

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_nandx(PPCHIRBuilder& f, const InstrData& i) {
  // RA <- ¬((RS) & (RB))
  Value* ra = f.Not(f.And(f.LoadGPR(i.X.RT), f.LoadGPR(i.X.RB)));
  f.StoreGPR(i.X.RA, ra);
  if (i.X.Rc) {
    f.UpdateCR(0, ra);
  }
  return 0;
}

Special Cases & Edge Conditions

• RA ← ~(RS AND RB). Bit-wise NAND. Since nand RA, RS, RS = ~RS (NOT-OR-self), the simplified mnemonic not RA, RS assembles to nor RA, RS, RS (note: NOR, not NAND). NAND-self is equivalent — both produce ~RS — but the assembler prefers the NOR form by convention.
• Operand convention is X-form (RA destination, RS/RB sources).
• 64-bit operation on Xenon; ~ operates on the full u64.
• No OE or XER side effects. Only Rc=1 updates CR0 (signed compare to zero).
• 64-bit CR update on Xenon, 32-bit in Canary. f.UpdateCR(0, v) truncates to INT32. NAND results frequently have all-ones high bits, so the low word's sign can differ from the full word's — call it out if reproducing CR-sensitive behaviour.
• Idiom: NAND of two equal values produces NOT. nand. RA, RS, RS ≡ ~RS with CR0 update. Sometimes used by compilers when not. is unavailable in their tablegen.

Related Instructions

• andx, andcx — base AND family.
• norx — assembler-preferred form for "NOT" via nor RA, RS, RS.
• eqvx — NXOR.
• orx, orcx, xorx — full logical family.

IBM Reference

• AIX 7.3 — nand (NAND)