Sylpheed/tools/ppc-manual/alu/sync.md

sync — Synchronize

Category: Integer ALU · Form: X · Opcode: 0x7c0004ac

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
sync	sync	—	Synchronize

Syntax

sync

Encoding

sync — form X

• Opcode word: 0x7c0004ac
• Primary opcode (bits 0–5): 31
• Extended opcode: 598
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RT/FRT/VRT	destination
11–15	RA/FRA/VRA	source A
16–20	RB/FRB/VRB	source B
21–30	XO	extended opcode (10 bits)
31	Rc	record-form flag

Operands

Field	Role	Description

Register Effects

sync

• Reads (always): none
• Reads (conditional): none
• Writes (always): none
• Writes (conditional): none

Status-Register Effects

No condition-register or status-register effects.

Operation (pseudocode)

multi-thread memory barrier (heavy). L=0 full sync; L=1 lightweight sync.

C Translation Example

/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

sync

• Canary XML: tools/ppc-instructions.xml — search for mnem="sync"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_memory.cc:754
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:288
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:940

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_sync(PPCHIRBuilder& f, const InstrData& i) {
  f.MemoryBarrier();
  return 0;
}

Special Cases & Edge Conditions

• Heavy multi-thread memory barrier. All memory accesses (loads and stores, cacheable and not) issued by this thread before sync complete with respect to all other threads/processors before any subsequent memory access begins. Drains the store queue.
• L field selects sync class. L=0 is full hwsync (the default). L=1 is lwsync — orders only loads-after-loads, loads-after-stores, and stores-after-stores (not stores-after-loads). The Xenon implements both via the same encoding with L (bit 9) selecting variant. Most disassembly shows the unsuffixed sync mnemonic, which assembles to L=0.
• No register or CR effects. Pure ordering primitive.
• Used to implement release semantics. A typical lock-release sequence is sync; stw r0, lock. Acquire side uses lwsync after the load.
• Canary emits f.MemoryBarrier(), as for eieio; isync is a plain f.Nop(). A sequential C translation needs neither: host program order subsumes the PPC ordering.
• Distinct from isync, which orders the instruction stream — sync does not refetch instructions.
• Slow on real hardware. Hundreds of cycles when the store queue is full; hot paths avoid sync and use lwsync or no barrier when only single-thread ordering is needed.

Related Instructions

• isync — instruction-fetch barrier.
• eieio — lighter I/O barrier for caching-inhibited storage.
• lwsync — same encoding, L=1; not separately enumerated in this page set.

IBM Reference

• AIX 7.3 — sync (Synchronize)
• PowerISA v2.07B, Book II, §1.7 — defines hwsync/lwsync/ptesync semantics.