Sylpheed/tools/ppc-manual/alu/xori.md

xori — XOR Immediate

Category: Integer ALU · Form: D · Opcode: 0x68000000

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
xori	xori	—	XOR Immediate

Syntax

xori [RA], [RS], [UIMM]

Encoding

xori — form D

• Opcode word: 0x68000000
• Primary opcode (bits 0–5): 26
• Extended opcode: —
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RT	destination GPR (or RS when storing)
11–15	RA	source GPR (0 ⇒ literal 0 for RA0 forms)
16–31	D/SI/UI	16-bit signed or unsigned immediate

Operands

Field	Role	Description
RS	xori: read	Source GPR (alias for RD in some stores).
UIMM	xori: read	16-bit unsigned immediate. Zero-extended.
RA	xori: write	Source GPR (r0–r31).

Register Effects

xori

• Reads (always): RS, UIMM
• Reads (conditional): none
• Writes (always): RA
• Writes (conditional): none

Status-Register Effects

No condition-register or status-register effects.

Operation (pseudocode)

RA <- (RS) ^ (0x0000 || UIMM)

C Translation Example

/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

xori

• Canary XML: tools/ppc-instructions.xml — search for mnem="xori"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_alu.cc:839
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:497
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:464

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_xori(PPCHIRBuilder& f, const InstrData& i) {
  // RA <- (RS) XOR (i48.0 || UI)
  Value* ra = f.Xor(f.LoadGPR(i.D.RT), f.LoadConstantUint64(XEEXTZ16(i.D.DS)));
  f.StoreGPR(i.D.RA, ra);
  return 0;
}

Special Cases & Edge Conditions

• No record form. Like ori, there is no xori.. To get a CR0 update follow with cmpwi or use xorx with Rc=1.
• Immediate is zero-extended to 64 bits. Only the low 16 bits of RA can be flipped; the high 48 bits are passed through from RS unchanged.
• xori 0, 0, 0 is a valid NOP encoding but the canonical NOP is ori 0, 0, 0. Disassemblers should still display this as xori r0, r0, 0 or recognise it as a no-op.
• 64-bit operation in Canary. f.Xor(RS, EXTZ16(UI)) on the full u64.
• No XER, no CR side effects.
• RA = 0 reads r0 (not literal zero); see ori.
• Useful for masked toggle. xori rA, rS, mask flips the bits of rS indicated by mask (low 16 bits only).

Related Instructions

• xoris — companion (immediate shifted left 16).
• xorx — register-register XOR.
• eqvx — ~(RS ^ RB).
• ori, andix — sister immediate logicals.

IBM Reference

• AIX 7.3 — xori (XOR Immediate)