Sylpheed/tools/ppc-manual/memory/dcbt.md

dcbt — Data Cache Block Touch

Category: Memory · Form: X · Opcode: 0x7c00022c

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
dcbt	dcbt	—	Data Cache Block Touch

Syntax

dcbt [RA0], [RB]

Encoding

dcbt — form X

• Opcode word: 0x7c00022c
• Primary opcode (bits 0–5): 31
• Extended opcode: 278
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RT/FRT/VRT	destination
11–15	RA/FRA/VRA	source A
16–20	RB/FRB/VRB	source B
21–30	XO	extended opcode (10 bits)
31	Rc	record-form flag

Operands

Field	Role	Description
RA0	dcbt: read	Source GPR; when the encoded register number is 0 the operand is the literal 64-bit zero, not r0.
RB	dcbt: read	Source GPR.

Register Effects

dcbt

• Reads (always): RA0, RB
• Reads (conditional): none
• Writes (always): none
• Writes (conditional): none

Status-Register Effects

No condition-register or status-register effects.

Operation (pseudocode)

; No hand-written pseudocode for this instruction yet.
; The authoritative semantics are the Canary emitter snapshot under
; Implementation References; about half of Canary's emitters open
; with the PPC-style definition as a comment (`RD <- (RA) + (RB)`).
; Every side effect is also enumerated in the Register Effects and
; Status-Register Effects tables above.

C Translation Example

/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

dcbt

• Canary XML: tools/ppc-instructions.xml — search for mnem="dcbt"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_memory.cc:1142
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:47
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:909

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_dcbt(PPCHIRBuilder& f, const InstrData& i) {
  if (!cvars::disable_prefetch_and_cachecontrol) {
    Value* ea = CalculateEA_0(f, i.X.RA, i.X.RB);
    f.CacheControl(ea, 128, CacheControlType::CACHE_CONTROL_TYPE_DATA_TOUCH);
  }
  return 0;
}

Special Cases & Edge Conditions

• Hint, not a guarantee. dcbt requests that the cache line containing EA be brought into L1 in anticipation of a future load. The processor is free to ignore the hint (e.g. under cache pressure or for non-cacheable storage).
• Read-intent prefetch. Pair-mate of dcbtst (which signals write intent and may prefer an exclusive cache state). Use dcbt when the next access is a read.
• No exception on bad address. Unlike a real load, dcbt to an unmapped or protected page does not raise; the hint is silently dropped. This makes it safe to "speculatively" prefetch one line past the end of a buffer.
• Cache line size. Xenon line is 128 bytes; low seven bits of EA are ignored.
• RA0 semantics. RA = 0 selects literal zero — dcbt 0, RB prefetches the line containing address RB.
• Stream-engine hints. The Xenon supports up to four hardware data-streams set up by sequences of dcbt with a stride; refer to the XDK for the stream-engine encoding (uses bits ignored by the architectural decode).
• Canary turns it into a host hint. Unless disable_prefetch_and_cachecontrol is set it emits prefetcht0 over the 128-byte cache line. Hints have no guest-observable effect.
• Unprivileged. Always available.

Related Instructions

• dcbtst — write-intent prefetch.
• dcbf, dcbst, dcbi — push / invalidate counterparts.
• dcbz, dcbz128 — allocate-and-zero (a stronger "I want this line" signal).
• icbi — instruction-cache analog (no instruction-cache prefetch in PowerPC).

IBM Reference

• AIX 7.3 — dcbt (Data Cache Block Touch)
• PowerISA v2.07B Book II § "Storage Control Instructions" for hint semantics.