Sylpheed/tools/ppc-manual/memory/lvehx.md

lvehx — Load Vector Element Half Word Indexed

Category: Memory · Form: X · Opcode: 0x7c00004e

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
lvehx	lvehx	—	Load Vector Element Half Word Indexed

Syntax

lvehx [VD], [RA0], [RB]

Encoding

lvehx — form X

• Opcode word: 0x7c00004e
• Primary opcode (bits 0–5): 31
• Extended opcode: 39
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RT/FRT/VRT	destination
11–15	RA/FRA/VRA	source A
16–20	RB/FRB/VRB	source B
21–30	XO	extended opcode (10 bits)
31	Rc	record-form flag

Operands

Field	Role	Description
RA0	lvehx: read	Source GPR; when the encoded register number is 0 the operand is the literal 64-bit zero, not r0.
RB	lvehx: read	Source GPR.
VD	lvehx: write	Destination vector register.

Register Effects

lvehx

• Reads (always): RA0, RB
• Reads (conditional): none
• Writes (always): VD
• Writes (conditional): none

Status-Register Effects

No condition-register or status-register effects.

Operation (pseudocode)

; No hand-written pseudocode for this instruction yet.
; The authoritative semantics are the Canary emitter snapshot under
; Implementation References; about half of Canary's emitters open
; with the PPC-style definition as a comment (`RD <- (RA) + (RB)`).
; Every side effect is also enumerated in the Register Effects and
; Status-Register Effects tables above.

C Translation Example

/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

lvehx

• Canary XML: tools/ppc-instructions.xml — search for mnem="lvehx"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_altivec.cc:81
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:137
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:878

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_lvehx(PPCHIRBuilder& f, const InstrData& i) {
  // Same as lvx.
  Value* ea =
      f.And(CalculateEA_0(f, i.X.RA, i.X.RB), f.LoadConstantUint64(~0xFull));
  f.StoreVR(i.X.RT, f.ByteSwap(f.Load(ea, VEC128_TYPE)));
  return 0;
}

Special Cases & Edge Conditions

• Single half-word element load. Architecturally lvehx loads exactly two bytes from EA (which must be 2-byte aligned) and places them in the half-word lane (EA mod 16) >> 1 of the destination vector; the other 7 half-word lanes are undefined.
• EA must be half-aligned. The low bit of EA is masked by hardware to align to 2 — an odd EA rounds down. ⚠️ Canary treats lvehx exactly like lvx: it masks to 16-byte alignment and loads the whole 128-bit vector.
• Canary simplification — full-line read. Canary's lvehx emits lvx's body, like lvebx / lvewx: ea & ~0xF then a full 16-byte read into VD. Architectural undefined lanes are filled in deterministically, which is stronger than hardware guarantees but practically convenient.
• RA0 semantics. When RA = 0, base is literal zero; lvehx VD, 0, RB reads at RB (and, in Canary, the surrounding aligned line).
• No update form. No lvehux exists.
• No VMX128 sibling. No lvehx128 — Xbox 360 code prefers lvx128 plus vperm.
• Big-endian half within the lane. The byte at the lower address is the most-significant byte of the half-word lane.
• Common idiom. Pair with vsplth to broadcast or with vperm to assemble a vector from sparse memory.

Related Instructions

• lvebx, lvewx — byte and word element loads.
• lvx, lvxl — full 16-byte aligned vector loads.
• lvlx, lvrx — load-left / load-right partial-vector ops.
• stvehx — symmetric single-half store.

IBM Reference

• AIX 7.3 — lvehx (Load Vector Element Half Word Indexed)
• PowerISA v2.07B Book I "Vector Facility" § "Vector Load and Store" for lane-placement rules.