7f8a81b8f8
The generator had not been able to run correctly since the manual moved into
`tools/ppc-manual/`: it computed the repository root as `HERE.parent.parent`,
which now names `tools/`, so the XML, Canary's emitters and xenia-rs all stopped
resolving — silently, because both scrapers skipped what they could not find.
Every page's references had been pointing at paths that exist nowhere.
What each source contributed, measured on the 350 pages before this change:
Operation (pseudocode) 251 pages: fixed boilerplate "derives from the xenia-rs
interpreter"; 99 carry real hand-written seeds
C translation 337 pages: the same kind of boilerplate
xenia-rs snapshot 336 pages: the interpreter arm, pasted in — the only
per-instruction semantics on unseeded pages
links xenia-rs opcode/decoder/interpreter + Canary emitter
Now:
* semantics come from **Xenia Canary**, the reference emulator, read through
`git show` at a pinned upstream commit (`origin/canary_experimental`,
f21ebd49e9). Not our checkout: it carries instrumentation and lacked
upstream's `mcrf` fix, so it would have published probes and a wrong `mcrf`.
Each page embeds the emitter (`InstrEmit_<mnem>`), and for the 128 pure
one-line delegations also the helper that holds the semantics.
* decode references point at `crates/sylpheed-ppc` — the decoder that
produces `sylpheed.db` — as in-repo relative links.
* the boilerplate now says what is true, and the C translation guide maps
Canary's actual HIR calls, checked against `ppc_hir_builder.h` (including
that `UpdateCR(n, v)` truncates to 32 bits).
* `rust_scraper.py` -> `decoder_scraper.py` (interpreter half dropped);
missing sources are now errors, not empty results.
Verified:
consistency checks 455 XML entries, 350 families, 598 index keys
hand-written tails 386/386 byte-identical after regeneration
xenia-rs in generated 0
pages with a snapshot 349/350 (was 336) — `dcbi` has no Canary emitter at all
in-repo decoder links 910/910 resolve to a line holding the identifier
emitter boundaries brace counter == column-0 `}` rule on 521/521;
preprocessor model unit-tested (#if 0/#else/#elif)
idempotency re-run: 0 pages updated, 0 working-tree changes
Hand-written notes (outside the generated regions) are not rewritten here:
* 110 links into `../../xenia-rs/...` were dead; they now point at the file in
the archived repository (git.mc02.dev/fabi/xenia-rs @ 8401d4d). Line anchors
were dropped because the notes predate that commit — 0 of 441 old line
ranges match it — and a precise-looking wrong anchor is worse than none. The
link text, which carries the author's line numbers, is unchanged.
* 140 prose claims about xenia-rs's behaviour remain. 23 are verified to hold
for Canary too (the 32-bit CR0 truncation, OE left unimplemented); the other
114 need checking one by one, and some invert — e.g. `divdx` notes a correct
64-bit CR0 update in xenia-rs where Canary's `UpdateCR` truncates. Left for
a deliberate pass rather than a blind substitution.
Co-Authored-By: Claude Opus 5 (1M context) <noreply@anthropic.com>
4.5 KiB
4.5 KiB
isync — Instruction Synchronize
Category: Integer ALU · Form: XL · Opcode:
0x4c00012c
Assembler Mnemonics
| Mnemonic | XML entry | Flags | Description |
|---|---|---|---|
isync |
isync |
— | Instruction Synchronize |
Syntax
isync
Encoding
isync — form XL
- Opcode word:
0x4c00012c - Primary opcode (bits 0–5):
19 - Extended opcode:
150 - Synchronising: no
| Bits | Field | Meaning |
|---|---|---|
| 0–5 | OPCD |
primary opcode (19) |
| 6–10 | BT/BO |
target / branch options |
| 11–15 | BA/BI |
source A / CR bit to test |
| 16–20 | BB |
source B |
| 21–30 | XO |
extended opcode (10 bits) |
| 31 | LK |
link flag |
Operands
| Field | Role | Description |
|---|
Register Effects
isync
- Reads (always): none
- Reads (conditional): none
- Writes (always): none
- Writes (conditional): none
Status-Register Effects
No condition-register or status-register effects.
Operation (pseudocode)
instruction-stream synchronisation — discards speculative state.
C Translation Example
/* No hand-written C yet. Translate the Canary emitter snapshot */
/* under Implementation References; its HIR maps directly: */
/* f.LoadGPR(n) / f.StoreGPR(n, v) -> r[n] / r[n] = v */
/* f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n] */
/* f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters */
/* wrap them in f.ByteSwap for the big-endian guest value */
/* f.UpdateCR(n, v) -> CR field n from v's LOW 32 BITS vs 0 */
/* f.LoadCA / f.StoreCA -> xer.CA; f.StoreSAT -> vscr.SAT */
/* i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands */
/* The Register Effects and Status-Register Effects tables above */
/* enumerate every side effect a faithful translation must emit. */
Implementation References
isync
- Canary XML:
tools/ppc-instructions.xml— search formnem="isync" - Canary emitter:
src/xenia/cpu/ppc/ppc_emit_memory.cc:759 - Sylpheed opcode:
crates/sylpheed-ppc/src/opcode.rs:99 - Sylpheed decoder:
crates/sylpheed-ppc/src/decoder.rs:829
Canary emitter (frozen snapshot @ f21ebd49e9)
int InstrEmit_isync(PPCHIRBuilder& f, const InstrData& i) {
// XEINSTRNOTIMPLEMENTED();
f.Nop();
return 0;
}
Special Cases & Edge Conditions
- Instruction-fetch barrier. Discards any speculatively fetched/decoded instructions and forces all subsequent ones to be re-fetched after preceding instructions complete. Required after self-modifying code, JIT-emitted code, and after MMU/page-table changes.
- Stronger than
syncfor instruction stream, weaker for memory stream —isyncdoes not order stores against later loads. It only forces a fetch refresh. - Common idiom:
dcbf/icbi/sync/isync— flush data cache, invalidate instruction cache, drain memory, refetch — used by JITs and self-modifying loaders. - No operands. Encoded as a fixed-form
XLinstruction; assemblers always emit0x4c00012c. - Xenia-rs is a no-op.
interpreter.rs:1267handlessync/eieio/isynctogether. Because xenia interprets in straight-line program order without any speculative instruction cache, no barrier behaviour is needed for correctness. - Privilege level: user. Unlike most cache management ops,
isyncis unprivileged and frequently appears in userland trampolines.
Related Instructions
sync— heavy memory barrier.eieio— I/O ordering for caching-inhibited storage.icbi,dcbf,dcbst— cache management ops (outside this page set) usually paired withisync.