Sylpheed/tools/ppc-manual/control/mfmsr.md

mfmsr — Move from Machine State Register

Category: Control / CR / SPR · Form: X · Opcode: 0x7c0000a6 · sync

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
mfmsr	mfmsr	—	Move from Machine State Register

Syntax

mfmsr [RD]

Encoding

mfmsr — form X

• Opcode word: 0x7c0000a6
• Primary opcode (bits 0–5): 31
• Extended opcode: 83
• Synchronising: yes

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RT/FRT/VRT	destination
11–15	RA/FRA/VRA	source A
16–20	RB/FRB/VRB	source B
21–30	XO	extended opcode (10 bits)
31	Rc	record-form flag

Operands

Field	Role	Description
MSR	mfmsr: read	Machine State Register.
RD	mfmsr: write	Destination GPR.

Register Effects

mfmsr

• Reads (always): MSR
• Reads (conditional): none
• Writes (always): RD
• Writes (conditional): none

Status-Register Effects

No condition-register or status-register effects.

Operation (pseudocode)

; No hand-written pseudocode for this instruction yet.
; The authoritative semantics are the Canary emitter snapshot under
; Implementation References; about half of Canary's emitters open
; with the PPC-style definition as a comment (`RD <- (RA) + (RB)`).
; Every side effect is also enumerated in the Register Effects and
; Status-Register Effects tables above.

C Translation Example

/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

mfmsr

• Canary XML: tools/ppc-instructions.xml — search for mnem="mfmsr"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_control.cc:816
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:173
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:886

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_mfmsr(PPCHIRBuilder& f, const InstrData& i) {
  // bit 48 = EE; interrupt enabled
  // bit 62 = RI; recoverable interrupt
  // return 8000h if unlocked (interrupts enabled), else 0
  f.StoreGPR(i.X.RT, f.LoadContext(offsetof(PPCContext, msr), INT64_TYPE));
  return 0;
}

Special Cases & Edge Conditions

• Privileged. mfmsr is supervisor-only; executing it from problem state on real hardware raises a Privileged Instruction interrupt. Xbox 360 game code never executes it directly — it appears only in the kernel image (xboxkrnl.exe) and in xenia's HLE bridge.

• MSR layout (Xenon-relevant fields, big-endian bit numbering).

  Bit	Name	Meaning
  32	EE	external interrupts enabled
  33	PR	problem state (1 = user)
  34	FP	floating-point available
  35	ME	machine-check enable
  38	DR	data address translation
  39	IR	instruction address translation
  50	LE	little-endian (always 0 on Xenon)
  63	RI	recoverable interrupt

  The Xenon also exposes MSR[SF] (bit 0) = 1 for 64-bit mode; MSR[HV] (bit 3) for hypervisor. See PowerISA Book III for the full table.

• Synchronisation. Marked sync in xenia's XML — mfmsr is execution-synchronising on real hardware (drains the pipeline before sampling MSR).

• xenia model. xenia-rs stores MSR as a flat u64 and returns it raw. No real bit semantics are modelled — the kernel HLE never observes individual MSR fields. The interpreter ignores privilege.

• Read of an undocumented field returns 0. Most of the MSR is zero in xenia because no path explicitly initialises it.

Related Instructions

• mtmsr — write MSR from a GPR (32-bit form).
• mtmsrd — write the full 64-bit MSR (PPC64 form).
• mfspr — for non-MSR special registers; MSR has its own dedicated opcode.
• sc — kernel entry where MSR transitions occur via rfid/hrfid.

mfmsr has no simplified mnemonics.

IBM Reference

• AIX 7.3 — mfmsr (Move from Machine State Register)
• PowerISA v2.07B, Book III §4.3 — MSR field definitions.