fabi/Sylpheed
1
0
Fork 0
Code Issues 9 Pull Requests 1 Actions Packages Projects Releases Wiki Activity
Files
c082d72bdcf7b2a54e262fdafbe084cd2ac63a62
Sylpheed/tools/ppc-manual/control/mfvscr.md
sim 7f8a81b8f8
All checks were successful
CI / Native — linux (pull_request) Successful in 2h2m37s
Details
CI / WASM — Web (pull_request) Successful in 30m13s
Details
CI / Formatting (pull_request) Successful in 1m23s
Details
docs(ppc-manual): quote Canary and our own decoder, not the retired xenia-rs 
The generator had not been able to run correctly since the manual moved into
`tools/ppc-manual/`: it computed the repository root as `HERE.parent.parent`,
which now names `tools/`, so the XML, Canary's emitters and xenia-rs all stopped
resolving — silently, because both scrapers skipped what they could not find.
Every page's references had been pointing at paths that exist nowhere.

What each source contributed, measured on the 350 pages before this change:

  Operation (pseudocode)  251 pages: fixed boilerplate "derives from the xenia-rs
                          interpreter"; 99 carry real hand-written seeds
  C translation           337 pages: the same kind of boilerplate
  xenia-rs snapshot       336 pages: the interpreter arm, pasted in — the only
                          per-instruction semantics on unseeded pages
  links                   xenia-rs opcode/decoder/interpreter + Canary emitter

Now:

  * semantics come from **Xenia Canary**, the reference emulator, read through
    `git show` at a pinned upstream commit (`origin/canary_experimental`,
    f21ebd49e9). Not our checkout: it carries instrumentation and lacked
    upstream's `mcrf` fix, so it would have published probes and a wrong `mcrf`.
    Each page embeds the emitter (`InstrEmit_<mnem>`), and for the 128 pure
    one-line delegations also the helper that holds the semantics.
  * decode references point at `crates/sylpheed-ppc` — the decoder that
    produces `sylpheed.db` — as in-repo relative links.
  * the boilerplate now says what is true, and the C translation guide maps
    Canary's actual HIR calls, checked against `ppc_hir_builder.h` (including
    that `UpdateCR(n, v)` truncates to 32 bits).
  * `rust_scraper.py` -> `decoder_scraper.py` (interpreter half dropped);
    missing sources are now errors, not empty results.

Verified:

  consistency checks        455 XML entries, 350 families, 598 index keys
  hand-written tails        386/386 byte-identical after regeneration
  xenia-rs in generated     0
  pages with a snapshot     349/350 (was 336) — `dcbi` has no Canary emitter at all
  in-repo decoder links     910/910 resolve to a line holding the identifier
  emitter boundaries        brace counter == column-0 `}` rule on 521/521;
                            preprocessor model unit-tested (#if 0/#else/#elif)
  idempotency               re-run: 0 pages updated, 0 working-tree changes

Hand-written notes (outside the generated regions) are not rewritten here:

  * 110 links into `../../xenia-rs/...` were dead; they now point at the file in
    the archived repository (git.mc02.dev/fabi/xenia-rs @ 8401d4d). Line anchors
    were dropped because the notes predate that commit — 0 of 441 old line
    ranges match it — and a precise-looking wrong anchor is worse than none. The
    link text, which carries the author's line numbers, is unchanged.
  * 140 prose claims about xenia-rs's behaviour remain. 23 are verified to hold
    for Canary too (the 32-bit CR0 truncation, OE left unimplemented); the other
    114 need checking one by one, and some invert — e.g. `divdx` notes a correct
    64-bit CR0 update in xenia-rs where Canary's `UpdateCR` truncates. Left for
    a deliberate pass rather than a blind substitution.

Co-Authored-By: Claude Opus 5 (1M context) <noreply@anthropic.com>
2026-09-16 20:34:34 +02:00

5.5 KiB
Raw Blame History

mfvscr — Move from VSCR

Category: Control / CR / SPR · Form: VX · Opcode: 0x10000604

Assembler Mnemonics

Mnemonic XML entry Flags Description
mfvscr mfvscr — Move from VSCR

Syntax

(no disassembly template)

Encoding

mfvscr — form VX

  • Opcode word: 0x10000604
  • Primary opcode (bits 0–5): 4
  • Extended opcode: 1540
  • Synchronising: no
Bits Field Meaning
0–5 OPCD primary opcode (4)
6–10 VRT/VD destination vector register
11–15 VRA/VA source A vector register
16–20 VRB/VB source B vector register
21–31 XO extended opcode (11 bits)

Operands

Field Role Description
VSCR mfvscr: read Vector Status and Control Register (NJ/SAT bits).
VD mfvscr: write Destination vector register.

Register Effects

mfvscr

  • Reads (always): VSCR
  • Reads (conditional): none
  • Writes (always): VD
  • Writes (conditional): none

Status-Register Effects

No condition-register or status-register effects.

Operation (pseudocode)

; No hand-written pseudocode for this instruction yet.
; The authoritative semantics are the Canary emitter snapshot under
; Implementation References; about half of Canary's emitters open
; with the PPC-style definition as a comment (`RD <- (RA) + (RB)`).
; Every side effect is also enumerated in the Register Effects and
; Status-Register Effects tables above.

C Translation Example

/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

mfvscr

Canary emitter (frozen snapshot @ f21ebd49e9) 
int InstrEmit_mfvscr(PPCHIRBuilder& f, const InstrData& i) {
  // mfvscr VD - Move from VSCR to VD
  f.StoreVR(i.VX.VD,
            f.LoadContext(offsetof(PPCContext, vscr_vec), VEC128_TYPE));
  return 0;
}

Special Cases & Edge Conditions

  • Operation. Reads the 32-bit Vector Status and Control Register (VSCR) into the low 32 bits of the rightmost word of VD (the 128-bit vector register). The other 96 bits of VD are zeroed. PowerISA places the result at byte offset 12..15 (big-endian within the 128-bit register).

  • VSCR contents (Xenon-relevant).

    Bit Name Meaning
    16 NJ Non-Java mode (denormal handling for IEEE-754 single-prec vector ops)
    31 SAT Saturation — sticky; set whenever a saturating vector op clamps

    All other bits are reserved (zero).

  • SAT is sticky. Once a saturating vector instruction clamps a result, VSCR[SAT] becomes 1 and stays 1 until explicitly cleared via mtvscr. Software polls it after a vector batch to detect overflow.

  • NJ controls denormals. When NJ=1 (the Xenon's default), AltiVec single-precision ops flush denormal inputs/outputs to zero (non-IEEE behaviour); NJ=0 enforces full IEEE.

  • VRSAVE. Writing the entire 128-bit VD consumes a vector register slot; software wishing to honour VRSAVE bookkeeping should ensure the chosen VD is in the live mask.

  • xenia simplification. xenia-rs stores VSCR as a single value of the same vr type (effectively a u128) and copies it directly into ctx.vr[VD]. Saturating ops in xenia-rs do maintain SAT correctly for the vector ops that are implemented; NJ is honoured for the denormal-flush paths but its effect is small in practice.

  • Not synchronising.

Related Instructions

  • mtvscr — write VSCR from a vector register (the inverse).
  • mfspr — for non-vector status registers; VSCR has its own opcode.
  • AltiVec saturating-arithmetic ops (e.g., vaddubs, vsubuhs) — primary writers of VSCR[SAT].

mfvscr has no simplified mnemonics.

IBM Reference

Reference in New Issue View Git Blame Copy Permalink