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docs(ppc-manual): quote Canary and our own decoder, not the retired xenia-rs 
The generator had not been able to run correctly since the manual moved into
`tools/ppc-manual/`: it computed the repository root as `HERE.parent.parent`,
which now names `tools/`, so the XML, Canary's emitters and xenia-rs all stopped
resolving — silently, because both scrapers skipped what they could not find.
Every page's references had been pointing at paths that exist nowhere.

What each source contributed, measured on the 350 pages before this change:

  Operation (pseudocode)  251 pages: fixed boilerplate "derives from the xenia-rs
                          interpreter"; 99 carry real hand-written seeds
  C translation           337 pages: the same kind of boilerplate
  xenia-rs snapshot       336 pages: the interpreter arm, pasted in — the only
                          per-instruction semantics on unseeded pages
  links                   xenia-rs opcode/decoder/interpreter + Canary emitter

Now:

  * semantics come from **Xenia Canary**, the reference emulator, read through
    `git show` at a pinned upstream commit (`origin/canary_experimental`,
    f21ebd49e9). Not our checkout: it carries instrumentation and lacked
    upstream's `mcrf` fix, so it would have published probes and a wrong `mcrf`.
    Each page embeds the emitter (`InstrEmit_<mnem>`), and for the 128 pure
    one-line delegations also the helper that holds the semantics.
  * decode references point at `crates/sylpheed-ppc` — the decoder that
    produces `sylpheed.db` — as in-repo relative links.
  * the boilerplate now says what is true, and the C translation guide maps
    Canary's actual HIR calls, checked against `ppc_hir_builder.h` (including
    that `UpdateCR(n, v)` truncates to 32 bits).
  * `rust_scraper.py` -> `decoder_scraper.py` (interpreter half dropped);
    missing sources are now errors, not empty results.

Verified:

  consistency checks        455 XML entries, 350 families, 598 index keys
  hand-written tails        386/386 byte-identical after regeneration
  xenia-rs in generated     0
  pages with a snapshot     349/350 (was 336) — `dcbi` has no Canary emitter at all
  in-repo decoder links     910/910 resolve to a line holding the identifier
  emitter boundaries        brace counter == column-0 `}` rule on 521/521;
                            preprocessor model unit-tested (#if 0/#else/#elif)
  idempotency               re-run: 0 pages updated, 0 working-tree changes

Hand-written notes (outside the generated regions) are not rewritten here:

  * 110 links into `../../xenia-rs/...` were dead; they now point at the file in
    the archived repository (git.mc02.dev/fabi/xenia-rs @ 8401d4d). Line anchors
    were dropped because the notes predate that commit — 0 of 441 old line
    ranges match it — and a precise-looking wrong anchor is worse than none. The
    link text, which carries the author's line numbers, is unchanged.
  * 140 prose claims about xenia-rs's behaviour remain. 23 are verified to hold
    for Canary too (the 32-bit CR0 truncation, OE left unimplemented); the other
    114 need checking one by one, and some invert — e.g. `divdx` notes a correct
    64-bit CR0 update in xenia-rs where Canary's `UpdateCR` truncates. Left for
    a deliberate pass rather than a blind substitution.

Co-Authored-By: Claude Opus 5 (1M context) <noreply@anthropic.com>
2026-09-16 20:34:34 +02:00

5.8 KiB
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fdivx — Floating Divide

Category: Floating-Point · Form: A · Opcode: 0xfc000024

Assembler Mnemonics

Mnemonic XML entry Flags Description
fdiv fdivx — Floating Divide
fdiv. fdivx Rc=1 Floating Divide

Syntax

fdiv[Rc] [FD], [FA], [FB]

Encoding

fdivx — form A

  • Opcode word: 0xfc000024
  • Primary opcode (bits 0–5): 63
  • Extended opcode: 18
  • Synchronising: no
Bits Field Meaning
0–5 OPCD primary opcode (59 or 63)
6–10 FRT destination FPR
11–15 FRA source A FPR
16–20 FRB source B FPR
21–25 FRC source C FPR (multiplier for madd-style ops)
26–30 XO extended opcode (5 bits)
31 Rc record-form flag (updates CR1)

Operands

Field Role Description
FA fdivx: read Source A floating-point register (fr0–fr31).
FB fdivx: read Source B floating-point register.
FD fdivx: write Destination floating-point register.
CR fdivx: write (conditional) Condition-register update. When Rc=1, CR field 0 (or CR6 for vector compares, CR1 for FPU) is updated from the result.
FPSCR fdivx: write Floating-Point Status and Control Register.

Register Effects

fdivx

  • Reads (always): FA, FB
  • Reads (conditional): none
  • Writes (always): FD, FPSCR
  • Writes (conditional): CR

Status-Register Effects

  • fdivx: CR1 ← FPSCR[FX, FEX, VX, OX] when Rc=1.; FPSCR updated per IEEE-754 flags (FX, FEX, FPRF, FR, FI, exceptions).

Operation (pseudocode)

FRT <- FRA ÷ FRB

C Translation Example

/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

fdivx

Canary emitter (frozen snapshot @ f21ebd49e9) 
int InstrEmit_fdivx(PPCHIRBuilder& f, const InstrData& i) {
  // frD <- frA / frB
#if XE_PLATFORM_LINUX
  // TODO(has207): verify if this is needed on Windows
  // On Linux, fdiv needs to use A format fields instead of X format
  Value* v = f.Div(f.LoadFPR(i.A.FRA), f.LoadFPR(i.A.FRB));
  f.StoreFPR(i.A.FRT, v);
  f.UpdateFPSCR(v, i.A.Rc);
#else
  Value* v = f.Div(f.LoadFPR(i.X.RA), f.LoadFPR(i.X.RB));
  f.StoreFPR(i.X.RT, v);
  f.UpdateFPSCR(v, i.X.Rc);
#endif
  return 0;
}

Special Cases & Edge Conditions

  • Double precision. Operates on IEEE-754 binary64; fdivsx is the single-precision sibling.
  • Divide by zero. FRA / ±0 (with FRA finite, non-zero) sets FPSCR[ZX, FX] and produces a correctly-signed infinity. xenia relies on host f64 /, which produces the same ±∞ — but does not raise ZX in the interpreter snapshot. xenia quirk: title code that polls FPSCR for divide-by-zero will not observe it.
  • 0 / 0 sets FPSCR[VXZDZ, VX, FX] and yields a quiet NaN.
  • ±∞ / ±∞ sets FPSCR[VXIDI, VX, FX] and yields a quiet NaN.
  • FPSCR side effects. Hardware updates FPRF, FR, FI, FX plus exception bits OX, UX, XX, ZX, VXZDZ, VXIDI, VXSNAN. xenia-rs does not maintain these.
  • Rc=1 (fdiv.) copies FPSCR[FX, FEX, VX, OX] into CR1.
  • NaN propagation. Quiet-NaN result for any NaN operand; signalling NaNs are quietened.
  • Performance. Hardware divide is multi-cycle and not pipelined on Xenon. Many titles prefer fres/frsqrte followed by Newton-Raphson refinement (or by fmadd chains) to avoid the divider.
  • Denormal flush. Xenon boots with FPSCR[NI]=1; xenia uses host IEEE.
  • Encoding. A-form, primary 63, XO 18. FRC is don't-care.

Related Instructions

  • fdivsx — single-precision divide.
  • fresx — reciprocal estimate ~1/FRB; combined with fmul/fmadd to implement reciprocal divides.
  • fmulx, faddx, fsubx — companion arithmetic.
  • fmaddx, fnmsubx — used in Newton-Raphson refinement steps.
  • mffsx, mtfsfx — FPSCR control (rounding mode, exception masks).

IBM Reference

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