Sylpheed/tools/ppc-manual/memory/dcbtst.md

dcbtst — Data Cache Block Touch for Store

Category: Memory · Form: X · Opcode: 0x7c0001ec

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
dcbtst	dcbtst	—	Data Cache Block Touch for Store

Syntax

dcbtst [RA0], [RB]

Encoding

dcbtst — form X

• Opcode word: 0x7c0001ec
• Primary opcode (bits 0–5): 31
• Extended opcode: 246
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RT/FRT/VRT	destination
11–15	RA/FRA/VRA	source A
16–20	RB/FRB/VRB	source B
21–30	XO	extended opcode (10 bits)
31	Rc	record-form flag

Operands

Field	Role	Description
RA0	dcbtst: read	Source GPR; when the encoded register number is 0 the operand is the literal 64-bit zero, not r0.
RB	dcbtst: read	Source GPR.

Register Effects

dcbtst

• Reads (always): RA0, RB
• Reads (conditional): none
• Writes (always): none
• Writes (conditional): none

Status-Register Effects

No condition-register or status-register effects.

Operation (pseudocode)

; No hand-written pseudocode for this instruction yet.
; The authoritative semantics are the Canary emitter snapshot under
; Implementation References; about half of Canary's emitters open
; with the PPC-style definition as a comment (`RD <- (RA) + (RB)`).
; Every side effect is also enumerated in the Register Effects and
; Status-Register Effects tables above.

C Translation Example

/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

dcbtst

• Canary XML: tools/ppc-instructions.xml — search for mnem="dcbtst"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_memory.cc:1150
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:48
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:907

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_dcbtst(PPCHIRBuilder& f, const InstrData& i) {
  if (!cvars::disable_prefetch_and_cachecontrol) {
    Value* ea = CalculateEA_0(f, i.X.RA, i.X.RB);
    f.CacheControl(ea, 128,
                   CacheControlType::CACHE_CONTROL_TYPE_DATA_TOUCH_FOR_STORE);
  }
  return 0;
}

Special Cases & Edge Conditions

• Hint, not a guarantee. dcbtst requests the addressed cache line be brought into L1 in anticipation of a future store. Hardware may treat this as a hint to fetch in an exclusive coherence state to avoid a follow-up upgrade.
• Pair of dcbt. dcbt signals read intent; dcbtst signals write intent. Use dcbtst before a planned store loop to avoid stalling on cache-line acquisition.
• No exception on bad address. Like dcbt, prefetch hints to unmapped or protected pages are silently dropped — no DSI exception. Safe to issue speculatively.
• Cache line size. Xenon line is 128 bytes; the low seven bits of EA are ignored.
• RA0 semantics. RA = 0 selects literal zero — dcbtst 0, RB prefetches the line containing address RB.
• Often replaced by dcbz128. When code knows it will write the entire line, dcbz128 is preferable: it allocates the line and zeros it without reading from memory at all, beating dcbtst + first-store.
• Xenia treats as no-op. Hints have no observable effect under the emulated memory model.

Related Instructions

• dcbt — read-intent prefetch.
• dcbz, dcbz128 — allocate-and-zero (skip the read entirely when writing the whole line).
• dcbf, dcbst, dcbi — push / invalidate counterparts.
• icbi — instruction-cache invalidate.

IBM Reference

• AIX 7.3 — dcbtst (Data Cache Block Touch for Store)
• PowerISA v2.07B Book II § "Storage Control Instructions".