Sylpheed/tools/ppc-manual/memory/stvlx.md

stvlx — Store Vector Left Indexed

Category: Memory · Form: X · Opcode: 0x7c00050e

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
stvlx	stvlx	—	Store Vector Left Indexed
stvlx128	stvlx128	—	Store Vector Left Indexed 128

Syntax

stvlx [VS], [RA0], [RB]
stvlx128 [VS], [RA0], [RB]

Encoding

stvlx — form X

• Opcode word: 0x7c00050e
• Primary opcode (bits 0–5): 31
• Extended opcode: 647
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RT/FRT/VRT	destination
11–15	RA/FRA/VRA	source A
16–20	RB/FRB/VRB	source B
21–30	XO	extended opcode (10 bits)
31	Rc	record-form flag

stvlx128 — form VX128_1

• Opcode word: 0x10000503
• Primary opcode (bits 0–5): 4
• Extended opcode: 1283
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (4)
6–10	VD128l	destination low 5 bits
11–15	RA	address register
16–20	RB	offset register
21–27	XO	extended opcode
28–29	VD128h	destination high 2 bits
30–31	—	reserved

Operands

Field	Role	Description
VS	stvlx: read; stvlx128: read	Source vector register (alias for VD on stores).
RA0	stvlx: read; stvlx128: read	Source GPR; when the encoded register number is 0 the operand is the literal 64-bit zero, not r0.
RB	stvlx: read; stvlx128: read	Source GPR.

Register Effects

stvlx

• Reads (always): VS, RA0, RB
• Reads (conditional): none
• Writes (always): none
• Writes (conditional): none

stvlx128

• Reads (always): VS, RA0, RB
• Reads (conditional): none
• Writes (always): none
• Writes (conditional): none

Status-Register Effects

No condition-register or status-register effects.

Operation (pseudocode)

; No hand-written pseudocode for this instruction yet.
; The authoritative semantics are the Canary emitter snapshot under
; Implementation References; about half of Canary's emitters open
; with the PPC-style definition as a comment (`RD <- (RA) + (RB)`).
; Every side effect is also enumerated in the Register Effects and
; Status-Register Effects tables above.

C Translation Example

/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

stvlx

• Canary XML: tools/ppc-instructions.xml — search for mnem="stvlx"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_altivec.cc:265
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:261
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:943

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_stvlx(PPCHIRBuilder& f, const InstrData& i) {
  return InstrEmit_stvlx_(f, i, i.X.RT, i.X.RA, i.X.RB);
}

// ── delegates to (src/xenia/cpu/ppc/ppc_emit_altivec.cc:254) ──
int InstrEmit_stvlx_(PPCHIRBuilder& f, const InstrData& i, uint32_t vd,
                     uint32_t ra, uint32_t rb) {
  // NOTE: if eb == 0 (so 16b aligned) this equals new_value
  //       we could optimize this to prevent the other load/mask, in that case.

  Value* ea = CalculateEA_0(f, ra, rb);

  Value* vdr = f.LoadVR(vd);
  f.StoreVectorLeft(ea, vdr);
  return 0;
}

stvlx128

• Canary XML: tools/ppc-instructions.xml — search for mnem="stvlx128"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_altivec.cc:268
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:262
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:537

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_stvlx128(PPCHIRBuilder& f, const InstrData& i) {
  return InstrEmit_stvlx_(f, i, VX128_1_VD128, i.VX128_1.RA, i.VX128_1.RB);
}

// ── delegates to (src/xenia/cpu/ppc/ppc_emit_altivec.cc:254) ──
int InstrEmit_stvlx_(PPCHIRBuilder& f, const InstrData& i, uint32_t vd,
                     uint32_t ra, uint32_t rb) {
  // NOTE: if eb == 0 (so 16b aligned) this equals new_value
  //       we could optimize this to prevent the other load/mask, in that case.

  Value* ea = CalculateEA_0(f, ra, rb);

  Value* vdr = f.LoadVR(vd);
  f.StoreVectorLeft(ea, vdr);
  return 0;
}

Special Cases & Edge Conditions

• Store-left half of an unaligned vector. stvlx writes (16 - (EA mod 16)) bytes from the left (low-lane) half of VS to addresses starting at the exact EA. The right half of VS is not stored. Combine with stvrx at EA + 16 to commit a full unaligned vector across an alignment boundary.
• Companion idiom. stvlx VS, RA, RB ; stvrx VS, RA, RB+16 writes the 16 bytes of VS to address EA regardless of alignment. The two halves are byte-disjoint, so the order between them doesn't affect correctness.
• No alignment masking. Unlike stvx, the EA is not rounded down. EA mod 16 controls how the source vector splits.
• RA0 semantics. RA = 0 selects literal zero.
• Microsoft Xbox 360 specific. Part of the VMX128 / Cell BE extended set, not in baseline Altivec.
• Implementation in xenia. The shared snapshot calls vmx::store_vector_left(mem, ea, vs), performing the unaligned partial-byte write.
• VMX128 sibling (stvlx128). Identical semantics; alternative operand encoding addressing v0..v127.
• stvlxl is the LRU-hint variant. Same data behaviour, hint ignored under emulation.

Related Instructions

• stvrx, stvrx128 — store-right partner.
• stvlxl, stvlxl128 — LRU-hint variants.
• stvx, stvx128 — aligned store (the EA-masking sibling).
• lvlx, lvrx — symmetric unaligned loads.

IBM Reference

• AIX 7.3 — stvlx (Store Vector Left Indexed)
• PowerISA v2.07B Book I "Vector Facility"; Microsoft Xbox 360 XDK for VMX128 unaligned stores.