7f8a81b8f8
The generator had not been able to run correctly since the manual moved into
`tools/ppc-manual/`: it computed the repository root as `HERE.parent.parent`,
which now names `tools/`, so the XML, Canary's emitters and xenia-rs all stopped
resolving — silently, because both scrapers skipped what they could not find.
Every page's references had been pointing at paths that exist nowhere.
What each source contributed, measured on the 350 pages before this change:
Operation (pseudocode) 251 pages: fixed boilerplate "derives from the xenia-rs
interpreter"; 99 carry real hand-written seeds
C translation 337 pages: the same kind of boilerplate
xenia-rs snapshot 336 pages: the interpreter arm, pasted in — the only
per-instruction semantics on unseeded pages
links xenia-rs opcode/decoder/interpreter + Canary emitter
Now:
* semantics come from **Xenia Canary**, the reference emulator, read through
`git show` at a pinned upstream commit (`origin/canary_experimental`,
f21ebd49e9). Not our checkout: it carries instrumentation and lacked
upstream's `mcrf` fix, so it would have published probes and a wrong `mcrf`.
Each page embeds the emitter (`InstrEmit_<mnem>`), and for the 128 pure
one-line delegations also the helper that holds the semantics.
* decode references point at `crates/sylpheed-ppc` — the decoder that
produces `sylpheed.db` — as in-repo relative links.
* the boilerplate now says what is true, and the C translation guide maps
Canary's actual HIR calls, checked against `ppc_hir_builder.h` (including
that `UpdateCR(n, v)` truncates to 32 bits).
* `rust_scraper.py` -> `decoder_scraper.py` (interpreter half dropped);
missing sources are now errors, not empty results.
Verified:
consistency checks 455 XML entries, 350 families, 598 index keys
hand-written tails 386/386 byte-identical after regeneration
xenia-rs in generated 0
pages with a snapshot 349/350 (was 336) — `dcbi` has no Canary emitter at all
in-repo decoder links 910/910 resolve to a line holding the identifier
emitter boundaries brace counter == column-0 `}` rule on 521/521;
preprocessor model unit-tested (#if 0/#else/#elif)
idempotency re-run: 0 pages updated, 0 working-tree changes
Hand-written notes (outside the generated regions) are not rewritten here:
* 110 links into `../../xenia-rs/...` were dead; they now point at the file in
the archived repository (git.mc02.dev/fabi/xenia-rs @ 8401d4d). Line anchors
were dropped because the notes predate that commit — 0 of 441 old line
ranges match it — and a precise-looking wrong anchor is worse than none. The
link text, which carries the author's line numbers, is unchanged.
* 140 prose claims about xenia-rs's behaviour remain. 23 are verified to hold
for Canary too (the 32-bit CR0 truncation, OE left unimplemented); the other
114 need checking one by one, and some invert — e.g. `divdx` notes a correct
64-bit CR0 update in xenia-rs where Canary's `UpdateCR` truncates. Left for
a deliberate pass rather than a blind substitution.
Co-Authored-By: Claude Opus 5 (1M context) <noreply@anthropic.com>
5.4 KiB
5.4 KiB
vadduhs — Vector Add Unsigned Half Word Saturate
Category: VMX (Altivec) · Form: VX · Opcode:
0x10000240
Assembler Mnemonics
| Mnemonic | XML entry | Flags | Description |
|---|---|---|---|
vadduhs |
vadduhs |
— | Vector Add Unsigned Half Word Saturate |
Syntax
vadduhs [VD], [VA], [VB]
Encoding
vadduhs — form VX
- Opcode word:
0x10000240 - Primary opcode (bits 0–5):
4 - Extended opcode:
576 - Synchronising: no
| Bits | Field | Meaning |
|---|---|---|
| 0–5 | OPCD |
primary opcode (4) |
| 6–10 | VRT/VD |
destination vector register |
| 11–15 | VRA/VA |
source A vector register |
| 16–20 | VRB/VB |
source B vector register |
| 21–31 | XO |
extended opcode (11 bits) |
Operands
| Field | Role | Description |
|---|---|---|
VA |
vadduhs: read | Source A vector register. |
VB |
vadduhs: read | Source B vector register. |
VD |
vadduhs: write | Destination vector register. |
VSCR |
vadduhs: write | Vector Status and Control Register (NJ/SAT bits). |
Register Effects
vadduhs
- Reads (always):
VA,VB - Reads (conditional): none
- Writes (always):
VD,VSCR - Writes (conditional): none
Status-Register Effects
vadduhs: VSCR[SAT] may be stickied on saturating vector operations.
Operation (pseudocode)
; No hand-written pseudocode for this instruction yet.
; The authoritative semantics are the Canary emitter snapshot under
; Implementation References; about half of Canary's emitters open
; with the PPC-style definition as a comment (`RD <- (RA) + (RB)`).
; Every side effect is also enumerated in the Register Effects and
; Status-Register Effects tables above.
C Translation Example
/* No hand-written C yet. Translate the Canary emitter snapshot */
/* under Implementation References; its HIR maps directly: */
/* f.LoadGPR(n) / f.StoreGPR(n, v) -> r[n] / r[n] = v */
/* f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n] */
/* f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters */
/* wrap them in f.ByteSwap for the big-endian guest value */
/* f.UpdateCR(n, v) -> CR field n from v's LOW 32 BITS vs 0 */
/* f.LoadCA / f.StoreCA -> xer.CA; f.StoreSAT -> vscr.SAT */
/* i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands */
/* The Register Effects and Status-Register Effects tables above */
/* enumerate every side effect a faithful translation must emit. */
Implementation References
vadduhs
- Canary XML:
tools/ppc-instructions.xml— search formnem="vadduhs" - Canary emitter:
src/xenia/cpu/ppc/ppc_emit_altivec.cc:394 - Sylpheed opcode:
crates/sylpheed-ppc/src/opcode.rs:304 - Sylpheed decoder:
crates/sylpheed-ppc/src/decoder.rs:597
Canary emitter (frozen snapshot @ f21ebd49e9)
int InstrEmit_vadduhs(PPCHIRBuilder& f, const InstrData& i) {
Value* v = f.VectorAdd(f.LoadVR(i.VX.VA), f.LoadVR(i.VX.VB), INT16_TYPE,
ARITHMETIC_UNSIGNED | ARITHMETIC_SATURATE);
f.StoreSAT(f.DidSaturate(v));
f.StoreVR(i.VX.VD, v);
return 0;
}
Special Cases & Edge Conditions
- Eight unsigned-half lanes, saturating. Each
VD[i] = min(VA[i] + VB[i], 0xFFFF)fori = 0..7. Lane 0 (VD[0..1]afterstvx) is the most-significant half. VSCR[SAT]is sticky-set if any lane clamps. Cleared only bymtvscr. Xenia usescrate::vmx::sat_add_u16(crates/xenia-cpu/src/vmx.rs) and ORs the per-lane flag.- One-sided clamp. Unsigned add cannot underflow, so only the upper bound
0xFFFFever clips. - The modulo counterpart is
vadduhm. Usevadduhswhen "too large to fit" must be flagged or clipped — typical for accumulating Q16 unsigned counters. - No XER side effects.
- Maps directly to
_mm_adds_epu16on SSE2 hosts — semantically identical, including the sticky-saturation observation step (xenia recovers the SAT flag from the per-lane comparison). - No VMX128 sibling.
Related Instructions
vadduhm— same width, modulo (non-saturating) add.vaddshs— same width, signed saturating add (range-32768..+32767).vaddubs,vadduws— unsigned saturating add at byte / word width.vsubuhs— the matching unsigned saturating subtract.mtvscr/mfvscr— read or clear the stickyVSCR[SAT]bit.