Sylpheed/tools/ppc-manual/vmx/vmaddfp.md

vmaddfp — Vector Multiply-Add Floating Point

Category: VMX (Altivec) · Form: VA · Opcode: 0x1000002e

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
vmaddfp	vmaddfp	—	Vector Multiply-Add Floating Point
vmaddfp128	vmaddfp128	—	Vector128 Multiply Add Floating Point

Syntax

vmaddfp [VD], [VA], [VC], [VB]
vmaddfp128 [VD], [VA], [VB], [VD]

Encoding

vmaddfp — form VA

• Opcode word: 0x1000002e
• Primary opcode (bits 0–5): 4
• Extended opcode: 46
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (4)
6–10	VRT	destination vector register
11–15	VRA	source A
16–20	VRB	source B
21–25	VRC	source C / shift
26–31	XO	extended opcode (6 bits)

vmaddfp128 — form VX128

• Opcode word: 0x140000d0
• Primary opcode (bits 0–5): 5
• Extended opcode: 208
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (4 or 5)
6–10	VD128l	destination low 5 bits
11–15	VA128l	source A low 5 bits
16–20	VB128l	source B low 5 bits
21	VA128H	source A high bit
22	—	reserved
23–25	VC	optional VC / XO sub-field
26	VA128h	source A middle bit
27	—	reserved
28–29	VD128h	destination high 2 bits
30–31	VB128h	source B high 2 bits

Operands

Field	Role	Description
VA	vmaddfp: read; vmaddfp128: read	Source A vector register.
VC	vmaddfp: read; vmaddfp128: read	Source C vector register / 3-bit selector.
VB	vmaddfp: read; vmaddfp128: read	Source B vector register.
VD	vmaddfp: write; vmaddfp128: write	Destination vector register.

Register Effects

vmaddfp

• Reads (always): VA, VC, VB
• Reads (conditional): none
• Writes (always): VD
• Writes (conditional): none

vmaddfp128

• Reads (always): VA, VC, VB
• Reads (conditional): none
• Writes (always): VD
• Writes (conditional): none

Status-Register Effects

No condition-register or status-register effects.

Operation (pseudocode)

for each 32-bit float lane i in 0..3:
    VD[i] <- (VA[i] * VC[i]) + VB[i]

C Translation Example

/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

vmaddfp

• Canary XML: tools/ppc-instructions.xml — search for mnem="vmaddfp"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_altivec.cc:795
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:348
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:703

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_vmaddfp(PPCHIRBuilder& f, const InstrData& i) {
  // (VD) <- ((VA) * (VC)) + (VB)
  return InstrEmit_vmaddfp_(f, i.VXA.VD, i.VXA.VA, i.VXA.VB, i.VXA.VC);
}

// ── delegates to (src/xenia/cpu/ppc/ppc_emit_altivec.cc:786) ──
int InstrEmit_vmaddfp_(PPCHIRBuilder& f, uint32_t vd, uint32_t va, uint32_t vb,
                       uint32_t vc) {
  // POWER8 testing showed that vmaddfp flushes denormal inputs to zero
  // regardless of NJM.
  // (VD) <- ((VA) * (VC)) + (VB)
  Value* v = f.MulAdd(f.LoadVR(va), f.LoadVR(vc), f.LoadVR(vb));
  f.StoreVR(vd, v);
  return 0;
}

vmaddfp128

• Canary XML: tools/ppc-instructions.xml — search for mnem="vmaddfp128"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_altivec.cc:799
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:349
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:728

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_vmaddfp128(PPCHIRBuilder& f, const InstrData& i) {
  // (VD) <- ((VA) * (VB)) + (VD)
  // NOTE: this resuses VD and swaps the arg order!
  return InstrEmit_vmaddfp_(f, VX128_VD128, VX128_VA128, VX128_VD128,
                            VX128_VB128);
}

Special Cases & Edge Conditions

• Fused multiply-add: VD = (VA * VC) + VB per word lane (single rounding). No intermediate rounding between the multiply and the add — this is critical for numerical accuracy in DSP filters and reduces error in dot products.
• Big-endian word lanes. Lane 0 is the most-significant word.
• NaN propagation, ±∞ arithmetic. Standard IEEE-754: any NaN input yields NaN; (+∞ * 0) yields NaN; the sum of +∞ and -∞ (e.g. (+∞ * 1) + -∞) yields NaN. No trap, no sticky bit.
• VSCR[NJ] denormals. With NJ = 1 (Xenon default), denormal inputs and outputs are flushed to ±0.
• No VSCR[SAT] change, no XER change, no exceptions.
• VMX128 sibling has surprising operand layout — VD is also a source. Xenia's vmaddfp128 reads VA, VB, and VD itself (as the accumulator), computing VD = (VA * VB) + VD_prev (crates/xenia-cpu/src/interpreter.rs). The standard vmaddfp keeps the canonical 4-operand VA, VC, VB → VD shape. This is a real difference in operand encoding (VX128_3 form vs. VA-form) that compilers must respect — VMX128 sacrifices the third source register slot for the extra register-file bits.
• Aliasing legal. vmaddfp v3, v3, v3, v3 works (squares + adds itself).
• Common usage. Per-lane polynomial evaluation, dot-product accumulation, any matrix multiply inner loop. Pair four vmaddfp instructions to do a 4×4 × 4-vec multiply.

Related Instructions

• vnmsubfp — −((VA * VC) − VB); fused negative-multiply-subtract.
• vaddfp, vsubfp — plain float add / subtract.
• vmulfp — xenia helper for VA * VC; on hardware games use vmaddfp v, va, vc, v0_zero.
• vmaxfp, vminfp — min / max for clamping.
• vrefp, vrsqrtefp — reciprocal / inverse-sqrt estimates that often appear in the same FMA chain.

IBM Reference

• AIX 7.3 — vmaddfp (Vector Multiply-Add Floating Point)
• IBM AltiVec Technology Programmer's Interface Manual, Chapter 5 — Floating-Point Multiply-Add Family