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docs(ppc-manual): quote Canary and our own decoder, not the retired xenia-rs 
The generator had not been able to run correctly since the manual moved into
`tools/ppc-manual/`: it computed the repository root as `HERE.parent.parent`,
which now names `tools/`, so the XML, Canary's emitters and xenia-rs all stopped
resolving — silently, because both scrapers skipped what they could not find.
Every page's references had been pointing at paths that exist nowhere.

What each source contributed, measured on the 350 pages before this change:

  Operation (pseudocode)  251 pages: fixed boilerplate "derives from the xenia-rs
                          interpreter"; 99 carry real hand-written seeds
  C translation           337 pages: the same kind of boilerplate
  xenia-rs snapshot       336 pages: the interpreter arm, pasted in — the only
                          per-instruction semantics on unseeded pages
  links                   xenia-rs opcode/decoder/interpreter + Canary emitter

Now:

  * semantics come from **Xenia Canary**, the reference emulator, read through
    `git show` at a pinned upstream commit (`origin/canary_experimental`,
    f21ebd49e9). Not our checkout: it carries instrumentation and lacked
    upstream's `mcrf` fix, so it would have published probes and a wrong `mcrf`.
    Each page embeds the emitter (`InstrEmit_<mnem>`), and for the 128 pure
    one-line delegations also the helper that holds the semantics.
  * decode references point at `crates/sylpheed-ppc` — the decoder that
    produces `sylpheed.db` — as in-repo relative links.
  * the boilerplate now says what is true, and the C translation guide maps
    Canary's actual HIR calls, checked against `ppc_hir_builder.h` (including
    that `UpdateCR(n, v)` truncates to 32 bits).
  * `rust_scraper.py` -> `decoder_scraper.py` (interpreter half dropped);
    missing sources are now errors, not empty results.

Verified:

  consistency checks        455 XML entries, 350 families, 598 index keys
  hand-written tails        386/386 byte-identical after regeneration
  xenia-rs in generated     0
  pages with a snapshot     349/350 (was 336) — `dcbi` has no Canary emitter at all
  in-repo decoder links     910/910 resolve to a line holding the identifier
  emitter boundaries        brace counter == column-0 `}` rule on 521/521;
                            preprocessor model unit-tested (#if 0/#else/#elif)
  idempotency               re-run: 0 pages updated, 0 working-tree changes

Hand-written notes (outside the generated regions) are not rewritten here:

  * 110 links into `../../xenia-rs/...` were dead; they now point at the file in
    the archived repository (git.mc02.dev/fabi/xenia-rs @ 8401d4d). Line anchors
    were dropped because the notes predate that commit — 0 of 441 old line
    ranges match it — and a precise-looking wrong anchor is worse than none. The
    link text, which carries the author's line numbers, is unchanged.
  * 140 prose claims about xenia-rs's behaviour remain. 23 are verified to hold
    for Canary too (the 32-bit CR0 truncation, OE left unimplemented); the other
    114 need checking one by one, and some invert — e.g. `divdx` notes a correct
    64-bit CR0 update in xenia-rs where Canary's `UpdateCR` truncates. Left for
    a deliberate pass rather than a blind substitution.

Co-Authored-By: Claude Opus 5 (1M context) <noreply@anthropic.com>
2026-09-16 20:34:34 +02:00

7.0 KiB
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vor — Vector Logical OR

Category: VMX (Altivec) · Form: VX · Opcode: 0x10000484

Assembler Mnemonics

Mnemonic XML entry Flags Description
vor vor — Vector Logical OR
vor128 vor128 — Vector128 Logical OR

Syntax

vor [VD], [VA], [VB]
vor128 [VD], [VA], [VB]

Encoding

vor — form VX

  • Opcode word: 0x10000484
  • Primary opcode (bits 0–5): 4
  • Extended opcode: 1156
  • Synchronising: no
Bits Field Meaning
0–5 OPCD primary opcode (4)
6–10 VRT/VD destination vector register
11–15 VRA/VA source A vector register
16–20 VRB/VB source B vector register
21–31 XO extended opcode (11 bits)

vor128 — form VX128

  • Opcode word: 0x140002d0
  • Primary opcode (bits 0–5): 5
  • Extended opcode: 720
  • Synchronising: no
Bits Field Meaning
0–5 OPCD primary opcode (4 or 5)
6–10 VD128l destination low 5 bits
11–15 VA128l source A low 5 bits
16–20 VB128l source B low 5 bits
21 VA128H source A high bit
22 — reserved
23–25 VC optional VC / XO sub-field
26 VA128h source A middle bit
27 — reserved
28–29 VD128h destination high 2 bits
30–31 VB128h source B high 2 bits

Operands

Field Role Description
VA vor: read; vor128: read Source A vector register.
VB vor: read; vor128: read Source B vector register.
VD vor: write; vor128: write Destination vector register.

Register Effects

vor

  • Reads (always): VA, VB
  • Reads (conditional): none
  • Writes (always): VD
  • Writes (conditional): none

vor128

  • Reads (always): VA, VB
  • Reads (conditional): none
  • Writes (always): VD
  • Writes (conditional): none

Status-Register Effects

No condition-register or status-register effects.

Operation (pseudocode)

; No hand-written pseudocode for this instruction yet.
; The authoritative semantics are the Canary emitter snapshot under
; Implementation References; about half of Canary's emitters open
; with the PPC-style definition as a comment (`RD <- (RA) + (RB)`).
; Every side effect is also enumerated in the Register Effects and
; Status-Register Effects tables above.

C Translation Example

/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

vor

Canary emitter (frozen snapshot @ f21ebd49e9) 
int InstrEmit_vor(PPCHIRBuilder& f, const InstrData& i) {
  return InstrEmit_vor_(f, i.VX.VD, i.VX.VA, i.VX.VB);
}

// ── delegates to (src/xenia/cpu/ppc/ppc_emit_altivec.cc:1151) ──
int InstrEmit_vor_(PPCHIRBuilder& f, uint32_t vd, uint32_t va, uint32_t vb) {
  // VD <- (VA) | (VB)
  if (va == vb) {
    // Copy VA==VB into VD.
    f.StoreVR(vd, f.LoadVR(va));
  } else {
    Value* v = f.Or(f.LoadVR(va), f.LoadVR(vb));
    f.StoreVR(vd, v);
  }
  return 0;
}

vor128

Canary emitter (frozen snapshot @ f21ebd49e9) 
int InstrEmit_vor128(PPCHIRBuilder& f, const InstrData& i) {
  return InstrEmit_vor_(f, VX128_VD128, VX128_VA128, VX128_VB128);
}

// ── delegates to (src/xenia/cpu/ppc/ppc_emit_altivec.cc:1151) ──
int InstrEmit_vor_(PPCHIRBuilder& f, uint32_t vd, uint32_t va, uint32_t vb) {
  // VD <- (VA) | (VB)
  if (va == vb) {
    // Copy VA==VB into VD.
    f.StoreVR(vd, f.LoadVR(va));
  } else {
    Value* v = f.Or(f.LoadVR(va), f.LoadVR(vb));
    f.StoreVR(vd, v);
  }
  return 0;
}

Special Cases & Edge Conditions

  • Bitwise OR across the full 128-bit register. Lane-agnostic; xenia implements it as four 32-bit lanes but the result is identical at any granularity.
  • vor VD, VA, VA is the idiomatic register move. No dedicated "vmr" exists in base Altivec; compilers recognise the vor v3, v4, v4 pattern as a move and schedule accordingly.
  • Aliasing is legal. vor v3, v3, v4 merges the mask in v4 into v3.
  • No flags, no VSCR effect.
  • VMX128 sibling vor128. Same operation, wider register file.
  • Common pattern: ORing a compare mask with a data vector to force specific lanes to all-ones without needing a select.

Related Instructions

  • vand, vandc — AND / AND-with-complement.
  • vnor — NOR, includes the idiom for bitwise NOT.
  • vxor — XOR; also a common "zero register" via vxor vD, vD, vD.
  • vsel — three-operand bit-select, often combined with OR of masks.

IBM Reference

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