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docs(ppc-manual): quote Canary and our own decoder, not the retired xenia-rs

The generator had not been able to run correctly since the manual moved into
`tools/ppc-manual/`: it computed the repository root as `HERE.parent.parent`,
which now names `tools/`, so the XML, Canary's emitters and xenia-rs all stopped
resolving — silently, because both scrapers skipped what they could not find.
Every page's references had been pointing at paths that exist nowhere.

What each source contributed, measured on the 350 pages before this change:

  Operation (pseudocode)  251 pages: fixed boilerplate "derives from the xenia-rs
                          interpreter"; 99 carry real hand-written seeds
  C translation           337 pages: the same kind of boilerplate
  xenia-rs snapshot       336 pages: the interpreter arm, pasted in — the only
                          per-instruction semantics on unseeded pages
  links                   xenia-rs opcode/decoder/interpreter + Canary emitter

Now:

  * semantics come from **Xenia Canary**, the reference emulator, read through
    `git show` at a pinned upstream commit (`origin/canary_experimental`,
    f21ebd49e9). Not our checkout: it carries instrumentation and lacked
    upstream's `mcrf` fix, so it would have published probes and a wrong `mcrf`.
    Each page embeds the emitter (`InstrEmit_<mnem>`), and for the 128 pure
    one-line delegations also the helper that holds the semantics.
  * decode references point at `crates/sylpheed-ppc` — the decoder that
    produces `sylpheed.db` — as in-repo relative links.
  * the boilerplate now says what is true, and the C translation guide maps
    Canary's actual HIR calls, checked against `ppc_hir_builder.h` (including
    that `UpdateCR(n, v)` truncates to 32 bits).
  * `rust_scraper.py` -> `decoder_scraper.py` (interpreter half dropped);
    missing sources are now errors, not empty results.

Verified:

  consistency checks        455 XML entries, 350 families, 598 index keys
  hand-written tails        386/386 byte-identical after regeneration
  xenia-rs in generated     0
  pages with a snapshot     349/350 (was 336) — `dcbi` has no Canary emitter at all
  in-repo decoder links     910/910 resolve to a line holding the identifier
  emitter boundaries        brace counter == column-0 `}` rule on 521/521;
                            preprocessor model unit-tested (#if 0/#else/#elif)
  idempotency               re-run: 0 pages updated, 0 working-tree changes

Hand-written notes (outside the generated regions) are not rewritten here:

  * 110 links into `../../xenia-rs/...` were dead; they now point at the file in
    the archived repository (git.mc02.dev/fabi/xenia-rs @ 8401d4d). Line anchors
    were dropped because the notes predate that commit — 0 of 441 old line
    ranges match it — and a precise-looking wrong anchor is worse than none. The
    link text, which carries the author's line numbers, is unchanged.
  * 140 prose claims about xenia-rs's behaviour remain. 23 are verified to hold
    for Canary too (the 32-bit CR0 truncation, OE left unimplemented); the other
    114 need checking one by one, and some invert — e.g. `divdx` notes a correct
    64-bit CR0 update in xenia-rs where Canary's `UpdateCR` truncates. Left for
    a deliberate pass rather than a blind substitution.

Co-Authored-By: Claude Opus 5 (1M context) <noreply@anthropic.com>

2026-09-16 20:34:34 +02:00

7.4 KiB

Raw Blame History

`vslo` — Vector Shift Left by Octet

Category: VMX (Altivec) · Form: VX · Opcode: 0x1000040c

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
`vslo`	`vslo`	—	Vector Shift Left by Octet
`vslo128`	`vslo128`	—	Vector128 Shift Left Octet

Syntax

vslo [VD], [VA], [VB]
vslo128 [VD], [VA], [VB]

Encoding

`vslo` — form `VX`

Opcode word: 0x1000040c
Primary opcode (bits 0–5): 4
Extended opcode: 1036
Synchronising: no

Bits	Field	Meaning
0–5	`OPCD`	primary opcode (4)
6–10	`VRT/VD`	destination vector register
11–15	`VRA/VA`	source A vector register
16–20	`VRB/VB`	source B vector register
21–31	`XO`	extended opcode (11 bits)

`vslo128` — form `VX128`

Opcode word: 0x14000390
Primary opcode (bits 0–5): 5
Extended opcode: 912
Synchronising: no

Bits	Field	Meaning
0–5	`OPCD`	primary opcode (4 or 5)
6–10	`VD128l`	destination low 5 bits
11–15	`VA128l`	source A low 5 bits
16–20	`VB128l`	source B low 5 bits
21	`VA128H`	source A high bit
22	`—`	reserved
23–25	`VC`	optional VC / XO sub-field
26	`VA128h`	source A middle bit
27	`—`	reserved
28–29	`VD128h`	destination high 2 bits
30–31	`VB128h`	source B high 2 bits

Operands

Field	Role	Description
`VA`	vslo: read; vslo128: read	Source A vector register.
`VB`	vslo: read; vslo128: read	Source B vector register.
`VD`	vslo: write; vslo128: write	Destination vector register.

Register Effects

`vslo`

Reads (always): VA, VB
Reads (conditional): none
Writes (always): VD
Writes (conditional): none

`vslo128`

Reads (always): VA, VB
Reads (conditional): none
Writes (always): VD
Writes (conditional): none

Status-Register Effects

No condition-register or status-register effects.

Operation (pseudocode)

; No hand-written pseudocode for this instruction yet.
; The authoritative semantics are the Canary emitter snapshot under
; Implementation References; about half of Canary's emitters open
; with the PPC-style definition as a comment (`RD <- (RA) + (RB)`).
; Every side effect is also enumerated in the Register Effects and
; Status-Register Effects tables above.

C Translation Example

/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

vslo

Canary XML: tools/ppc-instructions.xml — search for mnem="vslo"
Canary emitter: src/xenia/cpu/ppc/ppc_emit_altivec.cc:1482
Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:445
Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:638

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_vslo(PPCHIRBuilder& f, const InstrData& i) {
  return InstrEmit_vslo_(f, i.VX.VD, i.VX.VA, i.VX.VB);
}

// ── delegates to (src/xenia/cpu/ppc/ppc_emit_altivec.cc:1471) ──
int InstrEmit_vslo_(PPCHIRBuilder& f, uint32_t vd, uint32_t va, uint32_t vb) {
  // (VD) <- (VA) << (VB.b[F] & 0x78) (by octet)
  // TODO(benvanik): flag for shift-by-octet as optimization.
  Value* sh = f.Shr(
      f.And(f.Extract(f.LoadVR(vb), 15, INT8_TYPE), f.LoadConstantInt8(0x78)),
      3);
  Value* v = f.Permute(f.LoadVectorShl(sh), f.LoadVR(va), f.LoadZeroVec128(),
                       INT8_TYPE);
  f.StoreVR(vd, v);
  return 0;
}

vslo128

Canary XML: tools/ppc-instructions.xml — search for mnem="vslo128"
Canary emitter: src/xenia/cpu/ppc/ppc_emit_altivec.cc:1485
Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:446
Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:746

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_vslo128(PPCHIRBuilder& f, const InstrData& i) {
  return InstrEmit_vslo_(f, VX128_VD128, VX128_VA128, VX128_VB128);
}

// ── delegates to (src/xenia/cpu/ppc/ppc_emit_altivec.cc:1471) ──
int InstrEmit_vslo_(PPCHIRBuilder& f, uint32_t vd, uint32_t va, uint32_t vb) {
  // (VD) <- (VA) << (VB.b[F] & 0x78) (by octet)
  // TODO(benvanik): flag for shift-by-octet as optimization.
  Value* sh = f.Shr(
      f.And(f.Extract(f.LoadVR(vb), 15, INT8_TYPE), f.LoadConstantInt8(0x78)),
      3);
  Value* v = f.Permute(f.LoadVectorShl(sh), f.LoadVR(va), f.LoadZeroVec128(),
                       INT8_TYPE);
  f.StoreVR(vd, v);
  return 0;
}

Special Cases & Edge Conditions

Whole-register shift-left by octets (bytes). VA is shifted left by N bytes, where N = (VB.b[15] >> 3) & 0xF — bits 1..4 of the last byte of VB. Right end is zero-filled. N saturates at 15 because only 4 bits are honoured.
Shift count constraint. The ISA mandates a uniform 4-bit count across all of VB; xenia-rs reads only byte 15. Splat with vspltb before invoking when the count is derived dynamically.
Pair with vsl for full bit-level shifts. vslo contributes the byte-granular part; vsl contributes the 0..7 residual bits.
Big-endian. "Left" = toward MSB = toward VD.b[0].
No flags, no VSCR.
VMX128 sibling vslo128.

vsl — the bit-level whole-register shift-left.
vsro — shift-right by octets.
vsldoi — static-immediate variant.
vslb, vslh, vslw — per-lane shifts.

7.4 KiB Raw Blame History Unescape Escape

vslo — Vector Shift Left by Octet

Assembler Mnemonics

Syntax

Encoding

vslo — form VX

vslo128 — form VX128

Operands

Register Effects

vslo

vslo128

Status-Register Effects

Operation (pseudocode)

C Translation Example

Implementation References

Special Cases & Edge Conditions

Related Instructions

IBM Reference

7.4 KiB

Raw Blame History

`vslo` — Vector Shift Left by Octet

`vslo` — form `VX`

`vslo128` — form `VX128`

`vslo`

`vslo128`