Sylpheed/tools/ppc-manual/memory/dcbt.md

dcbt — Data Cache Block Touch

Category: Memory · Form: X · Opcode: 0x7c00022c

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
dcbt	dcbt	—	Data Cache Block Touch

Syntax

dcbt [RA0], [RB]

Encoding

dcbt — form X

• Opcode word: 0x7c00022c
• Primary opcode (bits 0–5): 31
• Extended opcode: 278
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RT/FRT/VRT	destination
11–15	RA/FRA/VRA	source A
16–20	RB/FRB/VRB	source B
21–30	XO	extended opcode (10 bits)
31	Rc	record-form flag

Operands

Field	Role	Description
RA0	dcbt: read	Source GPR; when the encoded register number is 0 the operand is the literal 64-bit zero, not r0.
RB	dcbt: read	Source GPR.

Register Effects

dcbt

• Reads (always): RA0, RB
• Reads (conditional): none
• Writes (always): none
• Writes (conditional): none

Status-Register Effects

No condition-register or status-register effects.

Operation (pseudocode)

; Pseudocode derives directly from the xenia-rs interpreter
; arm (see Implementation References). Operation semantics:
;   - Read source operands from the fields listed under Operands.
;   - Apply the arithmetic / logical / memory action described
;     in the Description field above.
;   - Write results to the destination register(s); update any
;     status bits enumerated under Status-Register Effects.
; Consult the IBM AIX reference link under IBM Reference for
; canonical PPC-style pseudocode where xenia's expression is
; terse.

C Translation Example

/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

dcbt

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="dcbt"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_memory.cc:1142
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:19
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:794

Special Cases & Edge Conditions

• Hint, not a guarantee. dcbt requests that the cache line containing EA be brought into L1 in anticipation of a future load. The processor is free to ignore the hint (e.g. under cache pressure or for non-cacheable storage).
• Read-intent prefetch. Pair-mate of dcbtst (which signals write intent and may prefer an exclusive cache state). Use dcbt when the next access is a read.
• No exception on bad address. Unlike a real load, dcbt to an unmapped or protected page does not raise; the hint is silently dropped. This makes it safe to "speculatively" prefetch one line past the end of a buffer.
• Cache line size. Xenon line is 128 bytes; low seven bits of EA are ignored.
• RA0 semantics. RA = 0 selects literal zero — dcbt 0, RB prefetches the line containing address RB.
• Stream-engine hints. The Xenon supports up to four hardware data-streams set up by sequences of dcbt with a stride; refer to the XDK for the stream-engine encoding (uses bits ignored by the architectural decode).
• Xenia treats as no-op. Hints have no observable effect under the emulated memory model.
• Unprivileged. Always available.

Related Instructions

• dcbtst — write-intent prefetch.
• dcbf, dcbst, dcbi — push / invalidate counterparts.
• dcbz, dcbz128 — allocate-and-zero (a stronger "I want this line" signal).
• icbi — instruction-cache analog (no instruction-cache prefetch in PowerPC).

IBM Reference

• AIX 7.3 — dcbt (Data Cache Block Touch)
• PowerISA v2.07B Book II § "Storage Control Instructions" for hint semantics.