Sylpheed/tools/ppc-manual/vmx/vrefp.md

vrefp — Vector Reciprocal Estimate Floating Point

Category: VMX (Altivec) · Form: VX · Opcode: 0x1000010a

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
vrefp	vrefp	—	Vector Reciprocal Estimate Floating Point
vrefp128	vrefp128	—	Vector128 Reciprocal Estimate Floating Point

Syntax

vrefp [VD], [VB]
vrefp128 [VD], [VB]

Encoding

vrefp — form VX

• Opcode word: 0x1000010a
• Primary opcode (bits 0–5): 4
• Extended opcode: 266
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (4)
6–10	VRT/VD	destination vector register
11–15	VRA/VA	source A vector register
16–20	VRB/VB	source B vector register
21–31	XO	extended opcode (11 bits)

vrefp128 — form VX128_3

• Opcode word: 0x18000630
• Primary opcode (bits 0–5): 6
• Extended opcode: 1584
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (6)
6–10	VD128l	destination low 5 bits
11–15	IMM	5-bit immediate
16–20	VB128l	source B low 5 bits
21–27	XO	extended opcode
28–29	VD128h	destination high 2 bits
30–31	VB128h	source B high 2 bits

Operands

Field	Role	Description
VB	vrefp: read; vrefp128: read	Source B vector register.
VD	vrefp: write; vrefp128: write	Destination vector register.

Register Effects

vrefp

• Reads (always): VB
• Reads (conditional): none
• Writes (always): VD
• Writes (conditional): none

vrefp128

• Reads (always): VB
• Reads (conditional): none
• Writes (always): VD
• Writes (conditional): none

Status-Register Effects

No condition-register or status-register effects.

Operation (pseudocode)

; No hand-written pseudocode for this instruction yet.
; The authoritative semantics are the Canary emitter snapshot under
; Implementation References; about half of Canary's emitters open
; with the PPC-style definition as a comment (`RD <- (RA) + (RB)`).
; Every side effect is also enumerated in the Register Effects and
; Status-Register Effects tables above.

C Translation Example

/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

vrefp

• Canary XML: tools/ppc-instructions.xml — search for mnem="vrefp"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_altivec.cc:1203
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:421
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:572

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_vrefp(PPCHIRBuilder& f, const InstrData& i) {
  return InstrEmit_vrefp_(f, i.VX.VD, i.VX.VB);
}

// ── delegates to (src/xenia/cpu/ppc/ppc_emit_altivec.cc:1197) ──
int InstrEmit_vrefp_(PPCHIRBuilder& f, uint32_t vd, uint32_t vb) {
  // (VD) <- 1/(VB)
  Value* v = f.Recip(f.LoadVR(vb));
  f.StoreVR(vd, v);
  return 0;
}

vrefp128

• Canary XML: tools/ppc-instructions.xml — search for mnem="vrefp128"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_altivec.cc:1206
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:422
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:779

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_vrefp128(PPCHIRBuilder& f, const InstrData& i) {
  return InstrEmit_vrefp_(f, VX128_3_VD128, VX128_3_VB128);
}

// ── delegates to (src/xenia/cpu/ppc/ppc_emit_altivec.cc:1197) ──
int InstrEmit_vrefp_(PPCHIRBuilder& f, uint32_t vd, uint32_t vb) {
  // (VD) <- 1/(VB)
  Value* v = f.Recip(f.LoadVR(vb));
  f.StoreVR(vd, v);
  return 0;
}

Special Cases & Edge Conditions

• Lane-wise reciprocal estimate. Each 32-bit float lane of VB is approximated by 1.0 / VB[i]. The PowerPC spec permits an estimate accurate to about 1/4096 (≈12 bits); Canary divides exactly (vdivps into 1.0) — its comment notes that AVX rcpps misses that 1/4096 bound and broke gameplay in one title. Game code that cares about bit-reproducible behaviour should Newton-iterate with vnmsubfp regardless of which backend computes the seed.
• Standard Newton iteration. x₁ = x₀ * (2 − VB * x₀), expressible as vnmsubfp x₁, x₀, VB, 2.0f followed by vmaddfp x₁, x₀, x₁, 0.0f (or similar). One iteration roughly doubles the valid bit count.
• IEEE-754 binary32 lanes; VSCR[NJ] honoured (denormals flush to zero when NJ = 1).
• No VSCR[SAT] update, no FPSCR update, no exception. Division by zero yields ±∞; division of zero yields ±∞ too (same sign convention).
• Big-endian lane indexing.
• VMX128 sibling vrefp128.

Related Instructions

• vrsqrtefp — reciprocal square root estimate, used with the same Newton scheme.
• vmaddfp, vnmsubfp — the building blocks of the Newton iteration.
• vexptefp, vlogefp — other "estimate"-style transcendentals.
• vaddfp, vsubfp — the float add/sub.

IBM Reference

• AIX 7.3 — vrefp (Vector Reciprocal Estimate Floating Point)
• IBM AltiVec Technology Programmer's Interface Manual, Chapter 5 — Floating-Point Arithmetic