Sylpheed/tools/ppc-manual/control/mcrfs.md

mcrfs — Move to Condition Register from FPSCR

Category: Control / CR / SPR · Form: X · Opcode: 0xfc000080

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
mcrfs	mcrfs	—	Move to Condition Register from FPSCR

Syntax

mcrfs [CRFD], [CRFS]

Encoding

mcrfs — form X

• Opcode word: 0xfc000080
• Primary opcode (bits 0–5): 63
• Extended opcode: 64
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RT/FRT/VRT	destination
11–15	RA/FRA/VRA	source A
16–20	RB/FRB/VRB	source B
21–30	XO	extended opcode (10 bits)
31	Rc	record-form flag

Operands

Field	Role	Description
CRFS	mcrfs: read	CR source field.
FPSCR	mcrfs: read; mcrfs: write	Floating-Point Status and Control Register.
CRFD	mcrfs: write	CR destination field (crf, 0–7).

Register Effects

mcrfs

• Reads (always): CRFS, FPSCR
• Reads (conditional): none
• Writes (always): CRFD, FPSCR
• Writes (conditional): none

Status-Register Effects

• mcrfs: FPSCR updated per IEEE-754 flags (FX, FEX, FPRF, FR, FI, exceptions).

Operation (pseudocode)

; No hand-written pseudocode for this instruction yet.
; The authoritative semantics are the Canary emitter snapshot under
; Implementation References; about half of Canary's emitters open
; with the PPC-style definition as a comment (`RD <- (RA) + (RB)`).
; Every side effect is also enumerated in the Register Effects and
; Status-Register Effects tables above.

C Translation Example

/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

mcrfs

• Canary XML: tools/ppc-instructions.xml — search for mnem="mcrfs"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_fpu.cc:371
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:168
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:1019

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_mcrfs(PPCHIRBuilder& f, const InstrData& i) {
  // mcrfs CRFD, CRFS
  // CR[4*CRFD:4*CRFD+3] <- FPSCR[4*CRFS:4*CRFS+3]
  // FPSCR[4*CRFS:4*CRFS+3] <- 0 (exception bits cleared)

  uint32_t crfd = i.X.RT >> 2;  // Destination CR field
  uint32_t crfs = i.X.RA >> 2;  // Source FPSCR field

  Value* fpscr = f.LoadFPSCR();

  // Extract 4-bit field from FPSCR
  // FPSCR fields are numbered from left to right (0-7), with field 0 being bits
  // 0-3
  uint32_t shift = 4 * (7 - crfs);
  Value* fpscr_field = f.And(f.Shr(fpscr, shift), f.LoadConstantUint32(0xF));

  // Store to CR field (need to shift to proper position in 64-bit CR)
  f.StoreCR(crfd, f.Shl(f.ZeroExtend(fpscr_field, INT64_TYPE), 4 * (7 - crfd)));

  // Clear the FPSCR field (set to 0)
  uint32_t mask = ~(0xF << shift);
  f.StoreFPSCR(f.And(fpscr, f.LoadConstantUint32(mask)));

  return 0;
}

Special Cases & Edge Conditions

• Operation. Copies one 4-bit FPSCR field into the chosen CR field, then clears the source FPSCR exception-status bits (sticky-bit reset). The non-exception status bits (FPRF, etc.) are not cleared.
• Bits cleared in FPSCR. The architectural rule is: any bit in the source FPSCR field that is one of {FX, OX, UX, ZX, XX, VXSNAN, VXISI, VXIDI, VXZDZ, VXIMZ, VXVC, VXSOFT, VXSQRT, VXCVI} is reset to 0 after the copy. FEX and VX (summary bits) are subsequently re-derived. Many other FPSCR bits (rounding mode, FPRF, FR/FI) are not affected — even if they fall in CRFS.
• CR field destination. CRFD is a 3-bit field index (0..7); the four bits land in their natural positions (LT, GT, EQ, SO) of the chosen CR field. After mcrfs, crf can be tested with the usual conditional branches.
• Use case. Inspect a particular FPSCR exception group, then act on it with a bc — e.g. test FPSCR[24..27] (the FI / FR / VXSNAN / VXISI cluster) and branch.
• Privilege. Non-privileged on the Xenon — application-visible.
• Canary status. Implemented: Canary copies the FPSCR field into the CR field and then zeroes all four bits of that FPSCR field (PowerISA clears only the exception bits in it). Its FPSCR model is incomplete (UpdateFPSCR is a stub), so the cleared bits rarely have an observable effect.
• No Rc. X-form, but the Rc bit position is unused (reserved 0).

Related Instructions

• mffsx — read entire FPSCR into an FPR.
• mtfsfx, mtfsb0x, mtfsb1x, mtfsfix — write FPSCR bits/fields.
• mcrf — copy a CR field to another CR field.
• mcrxr — analogous copy from XER (also clears).

mcrfs has no simplified mnemonics.

IBM Reference

• AIX 7.3 — mcrfs (Move to Condition Register from FPSCR)
• PowerISA v2.07B, Book I §4.6 — FPSCR layout (sticky exception bits and which clear semantics apply).