Sylpheed/tools/ppc-manual/fpu/fctiwzx.md

fctiwzx — Floating Convert to Integer Word with Round Toward Zero

Category: Floating-Point · Form: X · Opcode: 0xfc00001e

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
fctiwz	fctiwzx	—	Floating Convert to Integer Word with Round Toward Zero
fctiwz.	fctiwzx	Rc=1	Floating Convert to Integer Word with Round Toward Zero

Syntax

fctiwz[Rc] [FD], [FB]

Encoding

fctiwzx — form X

• Opcode word: 0xfc00001e
• Primary opcode (bits 0–5): 63
• Extended opcode: 15
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RT/FRT/VRT	destination
11–15	RA/FRA/VRA	source A
16–20	RB/FRB/VRB	source B
21–30	XO	extended opcode (10 bits)
31	Rc	record-form flag

Operands

Field	Role	Description
FB	fctiwzx: read	Source B floating-point register.
FD	fctiwzx: write	Destination floating-point register.
CR	fctiwzx: write (conditional)	Condition-register update. When Rc=1, CR field 0 (or CR6 for vector compares, CR1 for FPU) is updated from the result.
FPSCR	fctiwzx: write	Floating-Point Status and Control Register.

Register Effects

fctiwzx

• Reads (always): FB
• Reads (conditional): none
• Writes (always): FD, FPSCR
• Writes (conditional): CR

Status-Register Effects

• fctiwzx: CR0 ← signed-compare(result, 0) with SO ← XER[SO], when Rc=1.; FPSCR updated per IEEE-754 flags (FX, FEX, FPRF, FR, FI, exceptions).

Operation (pseudocode)

; No hand-written pseudocode for this instruction yet.
; The authoritative semantics are the Canary emitter snapshot under
; Implementation References; about half of Canary's emitters open
; with the PPC-style definition as a comment (`RD <- (RA) + (RB)`).
; Every side effect is also enumerated in the Register Effects and
; Status-Register Effects tables above.

C Translation Example

/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

fctiwzx

• Canary XML: tools/ppc-instructions.xml — search for mnem="fctiwzx"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_fpu.cc:313
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:73
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:1015

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_fctiwzx(PPCHIRBuilder& f, const InstrData& i) {
  // TODO(benvanik): assuming round to zero is always set, is that ok?
  return InstrEmit_fctiwxx_(f, i, ROUND_TO_ZERO);
}

// ── delegates to (src/xenia/cpu/ppc/ppc_emit_fpu.cc:289) ──
int InstrEmit_fctiwxx_(PPCHIRBuilder& f, const InstrData& i,
                       RoundMode round_mode) {
  auto end = f.NewLabel();
  auto isnan = f.NewLabel();
  Value* v;
  f.BranchTrue(f.IsNan(f.LoadFPR(i.X.RB)), isnan);
  v = f.Convert(f.LoadFPR(i.X.RB), INT32_TYPE, round_mode);
  v = f.Cast(f.SignExtend(v, INT64_TYPE), FLOAT64_TYPE);
  f.StoreFPR(i.X.RT, v);
  f.UpdateFPSCR(v, i.X.Rc);
  f.Branch(end);
  f.MarkLabel(isnan);
  v = f.Cast(f.LoadConstantUint32(0x80000000u), FLOAT64_TYPE);
  f.StoreFPR(i.X.RT, v);
  f.UpdateFPSCR(v, i.X.Rc);
  f.MarkLabel(end);
  return 0;
}

Special Cases & Edge Conditions

• binary64 → 32-bit signed integer, round toward zero. Truncates regardless of FPSCR[RN]. Canary clamps to (double)0x7FFFFFFF and converts with cvttsd2si, which truncates — matching PPC fctiwz semantics.
• Most common conversion in compiled code. Translates C/C++ (int32_t)f casts, which require truncation per the C standard.
• Saturation on out-of-range. Hardware saturates to i32::MAX for large positives, i32::MIN for large negatives or NaN, and sets FPSCR[VXCVI, VX, FX]. Canary reproduces the values (the clamp, cvttsd2si's 0x80000000, and an explicit NaN branch) but raises no FPSCR bits (UpdateFPSCR is a stub).
• NaN sentinel. Canary stores 0x0000_0000_8000_0000 — i32::MIN in the low word (the PPC sentinel), high word zero.
• High 32 bits of FPR. Architecturally undefined per PowerISA; Canary sign-extends the 32-bit result into them (a NaN input gives 0x0000_0000_8000_0000). Use stfiwx (store low 32 bits) — never stfd — for the canonical "store this integer" idiom.
• Inexact. Sets FPSCR[XX, FX] on any non-integer input on hardware; Canary raises no FPSCR bits (UpdateFPSCR is a stub).
• Rc=1 (fctiwz.) copies FPSCR[FX, FEX, VX, OX] into CR1.
• Encoding. X-form, primary 63, XO 15. Reads FRB only.

Related Instructions

• fctiwx — 32-bit integer with FPSCR[RN] rounding.
• fctidx, fctidzx — 64-bit integer variants.
• fcfidx — inverse direction (i64 → f64); for i32 → f64, sign-extend to i64 first.
• stfiwx — store low 32 bits of FPR; canonical companion.
• mffsx, mtfsfx — FPSCR control (no effect on fctiwz since rounding mode is fixed to truncation).

IBM Reference

• AIX 7.3 — fctiwz (Floating Convert to Integer Word with Round Toward Zero)
• PowerISA v2.07B, Book I, Chapter 4 — Floating-Point Processor.