Sylpheed/tools/ppc-manual/fpu/fmulsx.md

fmulsx — Floating Multiply Single

Category: Floating-Point · Form: A · Opcode: 0xec000032

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
fmuls	fmulsx	—	Floating Multiply Single
fmuls.	fmulsx	Rc=1	Floating Multiply Single

Syntax

fmuls[Rc] [FD], [FA], [FC]

Encoding

fmulsx — form A

• Opcode word: 0xec000032
• Primary opcode (bits 0–5): 59
• Extended opcode: 25
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (59 or 63)
6–10	FRT	destination FPR
11–15	FRA	source A FPR
16–20	FRB	source B FPR
21–25	FRC	source C FPR (multiplier for madd-style ops)
26–30	XO	extended opcode (5 bits)
31	Rc	record-form flag (updates CR1)

Operands

Field	Role	Description
FA	fmulsx: read	Source A floating-point register (fr0–fr31).
FC	fmulsx: read	Source C floating-point register (for madd-style ops).
FD	fmulsx: write	Destination floating-point register.
CR	fmulsx: write (conditional)	Condition-register update. When Rc=1, CR field 0 (or CR6 for vector compares, CR1 for FPU) is updated from the result.
FPSCR	fmulsx: write	Floating-Point Status and Control Register.

Register Effects

fmulsx

• Reads (always): FA, FC
• Reads (conditional): none
• Writes (always): FD, FPSCR
• Writes (conditional): CR

Status-Register Effects

• fmulsx: CR1 ← FPSCR[FX, FEX, VX, OX] when Rc=1.; FPSCR updated per IEEE-754 flags (FX, FEX, FPRF, FR, FI, exceptions).

Operation (pseudocode)

; No hand-written pseudocode for this instruction yet.
; The authoritative semantics are the Canary emitter snapshot under
; Implementation References; about half of Canary's emitters open
; with the PPC-style definition as a comment (`RD <- (RA) + (RB)`).
; Every side effect is also enumerated in the Register Effects and
; Status-Register Effects tables above.

C Translation Example

/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

fmulsx

• Canary XML: tools/ppc-instructions.xml — search for mnem="fmulsx"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_fpu.cc:97
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:81
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:506

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_fmulsx(PPCHIRBuilder& f, const InstrData& i) {
  // frD <- (frA) x (frC)
  Value* v = f.Mul(f.LoadFPR(i.A.FRA), f.LoadFPR(i.A.FRC));
  v = f.ToSingle(v);
  f.StoreFPR(i.A.FRT, v);
  f.UpdateFPSCR(v, i.A.Rc);
  return 0;
}

Special Cases & Edge Conditions

• A-form quirk: multiplier is FRC. Operands come from FRA (bits 11–15) and FRC (bits 21–25). Canary reads the multiplier from i.A.FRC (don't confuse it with the record bit Rc).
• Single precision. Result is rounded to IEEE-754 binary32 then re-encoded into the 64-bit FPR. Canary computes ToSingle(Mul(a, c)): vmulsd, then vcvtsd2ss + vcvtss2sd.
• 0 × ±∞ sets FPSCR[VXIMZ, VX, FX] and yields a quiet NaN.
• FPSCR side effects. Hardware updates FPRF, FR, FI, FX and exception bits OX, UX, XX, VXIMZ, VXSNAN. Canary does not maintain FPSCR (UpdateFPSCR is a stub).
• Rc=1 (fmuls.) copies FPSCR[FX, FEX, VX, OX] into CR1.
• NaN propagation. Quiet-NaN result for any NaN operand; signalling NaNs are quietened.
• Single-precision overflow returns ±∞ and sets OX/XX/FX.
• Denormal flush. That Xenon boots with FPSCR[NI]=1 is unverified. Canary starts every guest thread in IEEE mode (MXCSR 0x1F80; its init comment flags the startup state as unchecked) and turns on the host's flush-to-zero (MXCSR.FZ) only when the guest sets NI through mtfsf/mtfsfi.
• Encoding. A-form, primary 59, XO 25.

Related Instructions

• fmulx — double-precision multiply.
• fmaddsx, fmsubsx, fnmaddsx, fnmsubsx — single-precision fused multiply-add family (one rounding step; preferred for dot products).
• faddsx, fsubsx, fdivsx — companion single-precision arithmetic.
• fresx, frsqrtex — reciprocal estimates often paired with fmuls to compute a * (1/b).
• frspx — explicit double→single rounding helper.

IBM Reference

• AIX 7.3 — fmuls (Floating Multiply Single)
• PowerISA v2.07B, Book I, Chapter 4 — Floating-Point Processor.