Sylpheed/tools/ppc-manual/fpu/fsqrtx.md

fsqrtx — Floating Square Root

Category: Floating-Point · Form: A · Opcode: 0xfc00002c

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
fsqrt	fsqrtx	—	Floating Square Root
fsqrt.	fsqrtx	Rc=1	Floating Square Root

Syntax

fsqrt[Rc] [FD], [FB]

Encoding

fsqrtx — form A

• Opcode word: 0xfc00002c
• Primary opcode (bits 0–5): 63
• Extended opcode: 22
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (59 or 63)
6–10	FRT	destination FPR
11–15	FRA	source A FPR
16–20	FRB	source B FPR
21–25	FRC	source C FPR (multiplier for madd-style ops)
26–30	XO	extended opcode (5 bits)
31	Rc	record-form flag (updates CR1)

Operands

Field	Role	Description
FB	fsqrtx: read	Source B floating-point register.
FD	fsqrtx: write	Destination floating-point register.
CR	fsqrtx: write (conditional)	Condition-register update. When Rc=1, CR field 0 (or CR6 for vector compares, CR1 for FPU) is updated from the result.
FPSCR	fsqrtx: write	Floating-Point Status and Control Register.

Register Effects

fsqrtx

• Reads (always): FB
• Reads (conditional): none
• Writes (always): FD, FPSCR
• Writes (conditional): CR

Status-Register Effects

• fsqrtx: CR1 ← FPSCR[FX, FEX, VX, OX] when Rc=1.; FPSCR updated per IEEE-754 flags (FX, FEX, FPRF, FR, FI, exceptions).

Operation (pseudocode)

; No hand-written pseudocode for this instruction yet.
; The authoritative semantics are the Canary emitter snapshot under
; Implementation References; about half of Canary's emitters open
; with the PPC-style definition as a comment (`RD <- (RA) + (RB)`).
; Every side effect is also enumerated in the Register Effects and
; Status-Register Effects tables above.

C Translation Example

/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

fsqrtx

• Canary XML: tools/ppc-instructions.xml — search for mnem="fsqrtx"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_fpu.cc:164
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:94
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:1038

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_fsqrtx(PPCHIRBuilder& f, const InstrData& i) {
  return InstrEmit_fsqrt(f, i, false);
}

Special Cases & Edge Conditions

• Double precision. Operates on IEEE-754 binary64; fsqrtsx is the single-precision sibling. Canary emits the host's vsqrtsd.
• Negative inputs are invalid. sqrt(x < 0) (other than -0) sets FPSCR[VXSQRT, VX, FX] and yields a quiet NaN. Note: sqrt(-0) = -0 per IEEE-754 (preserves sign of zero) — host f64::sqrt matches.
• sqrt(+∞) = +∞, exact.
• FPSCR side effects. Hardware updates FPRF, FR, FI, FX plus exception bits XX (inexact, very common since sqrt is rarely exact), VXSQRT, VXSNAN. Canary does not update FPSCR (UpdateFPSCR is a stub).
• Rc=1 (fsqrt.) copies FPSCR[FX, FEX, VX, OX] into CR1.
• NaN propagation. Quiet-NaN result for any NaN operand; signalling NaNs are quietened.
• Performance / availability. fsqrt is a Power-ISA optional instruction; some implementations trap as illegal-opcode. Xenon implements it natively. Canary emits it directly as vsqrtsd.
• Encoding. A-form, primary 63, XO 22; reads FRB only — FRA and FRC are don't-care.
• Rounding mode uses FPSCR[RN].

Related Instructions

• fsqrtsx — single-precision square root.
• frsqrtex — reciprocal-square-root estimate (~1/sqrt(x)); preferred for normalize/length operations.
• fresx — reciprocal estimate; pairs with fsqrt for 1/sqrt(x).
• fmulx, fmaddx — used in Newton-Raphson refinement of frsqrte outputs.
• mffsx, mtfsfx — FPSCR control.

IBM Reference

• AIX 7.3 — fsqrt (Floating Square Root)
• PowerISA v2.07B, Book I, Chapter 4 — Floating-Point Processor (square-root invalid-operation rules).