Sylpheed/tools/ppc-manual/vmx/vavguw.md

vavguw — Vector Average Unsigned Word

Category: VMX (Altivec) · Form: VX · Opcode: 0x10000482

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
vavguw	vavguw	—	Vector Average Unsigned Word

Syntax

vavguw [VD], [VA], [VB]

Encoding

vavguw — form VX

• Opcode word: 0x10000482
• Primary opcode (bits 0–5): 4
• Extended opcode: 1154
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (4)
6–10	VRT/VD	destination vector register
11–15	VRA/VA	source A vector register
16–20	VRB/VB	source B vector register
21–31	XO	extended opcode (11 bits)

Operands

Field	Role	Description
VA	vavguw: read	Source A vector register.
VB	vavguw: read	Source B vector register.
VD	vavguw: write	Destination vector register.

Register Effects

vavguw

• Reads (always): VA, VB
• Reads (conditional): none
• Writes (always): VD
• Writes (conditional): none

Status-Register Effects

No condition-register or status-register effects.

Operation (pseudocode)

; No hand-written pseudocode for this instruction yet.
; The authoritative semantics are the Canary emitter snapshot under
; Implementation References; about half of Canary's emitters open
; with the PPC-style definition as a comment (`RD <- (RA) + (RB)`).
; Every side effect is also enumerated in the Register Effects and
; Status-Register Effects tables above.

C Translation Example

/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

vavguw

• Canary XML: tools/ppc-instructions.xml — search for mnem="vavguw"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_altivec.cc:482
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:316
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:645

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_vavguw(PPCHIRBuilder& f, const InstrData& i) {
  Value* v = f.VectorAverage(f.LoadVR(i.VX.VA), f.LoadVR(i.VX.VB), INT32_TYPE,
                             ARITHMETIC_UNSIGNED);
  f.StoreVR(i.VX.VD, v);
  return 0;
}

Special Cases & Edge Conditions

• Four unsigned-word rounding averages. Each VD[i] = (VA[i] + VB[i] + 1) >> 1, computed in 64-bit arithmetic to avoid intermediate overflow, then truncated to u32. Rounding is half-up.
• Big-endian word lanes. Lane 0 (VD[0..3] after stvx) is the most-significant word.
• No VSCR[SAT] impact. The result always fits in u32. Canary's x64 backend computes each lane in a scalar loop as (a + b + 1) >> 1 on zero-extended 64-bit values.
• No SSE2 direct equivalent. SSE2 only provides _mm_avg_epu8 and _mm_avg_epu16; on x86 hosts Canary widens each lane to 64 bits and averages in a scalar loop.
• Common usage. Per-tile counters; midpoint of two 32-bit packed values.
• Aliasing legal.
• No VMX128 sibling.

Related Instructions

• vavgsw — same width, signed rounding average.
• vavgub, vavguh — unsigned rounding average at byte / half width.
• vadduwm, vadduws — addition variants without the divide step.
• vsubuwm — modulo subtract; difference before averaging.

IBM Reference

• AIX 7.3 — vavguw (Vector Average Unsigned Word)
• IBM AltiVec Technology Programmer's Interface Manual, Chapter 6 — Average Instructions