Sylpheed/tools/ppc-manual/vmx/vcmpbfp.md

vcmpbfp — Vector Compare Bounds Floating Point

Category: VMX (Altivec) · Form: VC · Opcode: 0x100003c6

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
vcmpbfp	vcmpbfp	—	Vector Compare Bounds Floating Point
vcmpbfp.	vcmpbfp	Rc=1	Vector Compare Bounds Floating Point
vcmpbfp128	vcmpbfp128	—	Vector128 Compare Bounds Floating Point
vcmpbfp128.	vcmpbfp128	Rc=1	Vector128 Compare Bounds Floating Point

Syntax

vcmpbfp[Rc] [VD], [VA], [VB]
vcmpbfp128[Rc] [VD], [VA], [VB]

Encoding

vcmpbfp — form VC

• Opcode word: 0x100003c6
• Primary opcode (bits 0–5): 4
• Extended opcode: 966
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (4)
6–10	VRT	destination vector register
11–15	VRA	source A
16–20	VRB	source B
21	Rc	record-form flag (updates CR6)
22–31	XO	extended opcode (10 bits)

vcmpbfp128 — form VX128_R

• Opcode word: 0x18000180
• Primary opcode (bits 0–5): 6
• Extended opcode: 384
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (4)
6–10	VD128l	destination low 5 bits
11–15	VA128l	source A low 5 bits
16–20	VB128l	source B low 5 bits
21	VA128H	source A high bit
22–25	XO	extended opcode (compare)
26	VA128h	source A middle bit
27	Rc	record-form flag (updates CR6)
28–29	VD128h	destination high 2 bits
30–31	VB128h	source B high 2 bits

Operands

Field	Role	Description
VA	vcmpbfp: read; vcmpbfp128: read	Source A vector register.
VB	vcmpbfp: read; vcmpbfp128: read	Source B vector register.
VD	vcmpbfp: write; vcmpbfp128: write	Destination vector register.
CR	vcmpbfp: write (conditional); vcmpbfp128: write (conditional)	Condition-register update. When Rc=1, CR field 0 (or CR6 for vector compares, CR1 for FPU) is updated from the result.

Register Effects

vcmpbfp

• Reads (always): VA, VB
• Reads (conditional): none
• Writes (always): VD
• Writes (conditional): CR

vcmpbfp128

• Reads (always): VA, VB
• Reads (conditional): none
• Writes (always): VD
• Writes (conditional): CR

Status-Register Effects

• vcmpbfp: CR6 ← [all-true, 0, all-false, 0] when Rc=1.
• vcmpbfp128: CR6 ← [all-true, 0, all-false, 0] when Rc=1.

Operation (pseudocode)

; No hand-written pseudocode for this instruction yet.
; The authoritative semantics are the Canary emitter snapshot under
; Implementation References; about half of Canary's emitters open
; with the PPC-style definition as a comment (`RD <- (RA) + (RB)`).
; Every side effect is also enumerated in the Register Effects and
; Status-Register Effects tables above.

C Translation Example

/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

vcmpbfp

• Canary XML: tools/ppc-instructions.xml — search for mnem="vcmpbfp"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_altivec.cc:583
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:321
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:684

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_vcmpbfp(PPCHIRBuilder& f, const InstrData& i) {
  return InstrEmit_vcmpbfp_(f, i, i.VXR.VD, i.VXR.VA, i.VXR.VB, i.VXR.Rc);
}

// ── delegates to (src/xenia/cpu/ppc/ppc_emit_altivec.cc:561) ──
int InstrEmit_vcmpbfp_(PPCHIRBuilder& f, const InstrData& i, uint32_t vd,
                       uint32_t va, uint32_t vb, uint32_t rc) {
  // if vA or vB are NaN, the 2 high-order bits are set (0xC0000000)
  Value* va_value = f.LoadVR(va);
  Value* vb_value = f.LoadVR(vb);
  Value* gt = f.VectorCompareSGT(va_value, vb_value, FLOAT32_TYPE);
  Value* lt =
      f.Not(f.VectorCompareSGE(va_value, f.Neg(vb_value), FLOAT32_TYPE));
  Value* v =
      f.Or(f.And(gt, f.LoadConstantVec128(vec128i(0x80000000, 0x80000000,
                                                  0x80000000, 0x80000000))),
           f.And(lt, f.LoadConstantVec128(vec128i(0x40000000, 0x40000000,
                                                  0x40000000, 0x40000000))));
  f.StoreVR(vd, v);
  if (rc) {
    // CR0:4 = 0; CR0:5 = VT == 0; CR0:6 = CR0:7 = 0;
    // If all of the elements are within bounds, CR6[2] is set
    // FIXME: Does not affect CR6[0], but the following function does.
    f.UpdateCR6(f.Or(gt, lt));
  }
  return 0;
}

vcmpbfp128

• Canary XML: tools/ppc-instructions.xml — search for mnem="vcmpbfp128"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_altivec.cc:586
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:322
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:799

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_vcmpbfp128(PPCHIRBuilder& f, const InstrData& i) {
  return InstrEmit_vcmpbfp_(f, i, VX128_R_VD128, VX128_R_VA128, VX128_R_VB128,
                            i.VX128_R.Rc);
}

Special Cases & Edge Conditions

• "Bounds" compare, not equality. Per word lane, sets two output bits: bit 0 (mask 0x80000000) if VA[i] > VB[i] (out-of-range high) and bit 1 (mask 0x40000000) if VA[i] < -VB[i] (out-of-range low). Bits 2..31 of each lane are zero.
• NaN inputs. The IBM manual treats NaN as violating both bounds (0xC0000000), and Canary's comment says the same, but its code sets only 0x40000000: the "greater than" test is vcmpgtps (false for NaN) and only the "not ≥ −VB" test comes out true. Canary quirk for NaN inputs.
• CR6 update when Rc=1. CR6 is set as [lt=0, gt=0, eq=(no-lane-out-of-range), so=0] — i.e. only the eq bit signifies "all four lanes were within ±VB". Useful as bc 12,26 (branch if all in-range) for SIMD clamping loops.
• No VSCR[SAT], no XER changes, no exceptions.
• The convention is "is point inside box?" — not a per-lane compare like the other vcmp* ops. Output is a flag-pair, not a boolean mask, so it does not plug directly into vsel. To get a boolean, OR the two bits down with vor and a shift.
• VMX128 sibling (vcmpbfp128). Identical semantics; the Rc bit lives at bit 27 of the VX128_R encoding.
• Lane width is fixed at word. Bounds check is single-precision float only; there is no vcmpb* for half / byte / int.

Related Instructions

• vcmpeqfp — element-wise == for floats.
• vcmpgtfp, vcmpgefp — element-wise > and >= for floats.
• vsel, vand, vor — combine the two bits per lane into a boolean mask if needed.
• vmaxfp, vminfp — clamp values to a range without testing.

IBM Reference

• AIX 7.3 — vcmpbfp (Vector Compare Bounds Floating Point)
• IBM AltiVec Technology Programmer's Interface Manual, Chapter 5 — Floating-Point Compares