Sylpheed/tools/ppc-manual/vmx/vexptefp.md

vexptefp — Vector 2 Raised to the Exponent Estimate Floating Point

Category: VMX (Altivec) · Form: VX · Opcode: 0x1000018a

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
vexptefp	vexptefp	—	Vector 2 Raised to the Exponent Estimate Floating Point
vexptefp128	vexptefp128	—	Vector128 Log2 Estimate Floating Point

Syntax

vexptefp [VD], [VB]
vexptefp128 [VD], [VB]

Encoding

vexptefp — form VX

• Opcode word: 0x1000018a
• Primary opcode (bits 0–5): 4
• Extended opcode: 394
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (4)
6–10	VRT/VD	destination vector register
11–15	VRA/VA	source A vector register
16–20	VRB/VB	source B vector register
21–31	XO	extended opcode (11 bits)

vexptefp128 — form VX128_3

• Opcode word: 0x180006b0
• Primary opcode (bits 0–5): 6
• Extended opcode: 1712
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (6)
6–10	VD128l	destination low 5 bits
11–15	IMM	5-bit immediate
16–20	VB128l	source B low 5 bits
21–27	XO	extended opcode
28–29	VD128h	destination high 2 bits
30–31	VB128h	source B high 2 bits

Operands

Field	Role	Description
VB	vexptefp: read; vexptefp128: read	Source B vector register.
VD	vexptefp: write; vexptefp128: write	Destination vector register.

Register Effects

vexptefp

• Reads (always): VB
• Reads (conditional): none
• Writes (always): VD
• Writes (conditional): none

vexptefp128

• Reads (always): VB
• Reads (conditional): none
• Writes (always): VD
• Writes (conditional): none

Status-Register Effects

No condition-register or status-register effects.

Operation (pseudocode)

; No hand-written pseudocode for this instruction yet.
; The authoritative semantics are the Canary emitter snapshot under
; Implementation References; about half of Canary's emitters open
; with the PPC-style definition as a comment (`RD <- (RA) + (RB)`).
; Every side effect is also enumerated in the Register Effects and
; Status-Register Effects tables above.

C Translation Example

/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

vexptefp

• Canary XML: tools/ppc-instructions.xml — search for mnem="vexptefp"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_altivec.cc:766
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:343
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:584

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_vexptefp(PPCHIRBuilder& f, const InstrData& i) {
  return InstrEmit_vexptefp_(f, i.VX.VD, i.VX.VB);
}

// ── delegates to (src/xenia/cpu/ppc/ppc_emit_altivec.cc:760) ──
int InstrEmit_vexptefp_(PPCHIRBuilder& f, uint32_t vd, uint32_t vb) {
  // (VD) <- pow2(VB)
  Value* v = f.Pow2(f.LoadVR(vb));
  f.StoreVR(vd, v);
  return 0;
}

vexptefp128

• Canary XML: tools/ppc-instructions.xml — search for mnem="vexptefp128"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_altivec.cc:769
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:344
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:781

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_vexptefp128(PPCHIRBuilder& f, const InstrData& i) {
  return InstrEmit_vexptefp_(f, VX128_3_VD128, VX128_3_VB128);
}

// ── delegates to (src/xenia/cpu/ppc/ppc_emit_altivec.cc:760) ──
int InstrEmit_vexptefp_(PPCHIRBuilder& f, uint32_t vd, uint32_t vb) {
  // (VD) <- pow2(VB)
  Value* v = f.Pow2(f.LoadVR(vb));
  f.StoreVR(vd, v);
  return 0;
}

Special Cases & Edge Conditions

• Per-lane base-2 exponent. Each of the four word lanes computes VD[i] = 2^VB[i] in binary32. Note: the IBM manual specifies a low-precision estimate (≤ 1/16 ULP relative error). Canary calls the host's std::exp2 per lane, which is full-precision — programs that depend on hardware-quality estimation may observe small numerical differences.
• Use vlogefp for the inverse. The natural pair is vexptefp(vlogefp(x)) = x for positive finite x, modulo each estimate's error budget.
• Big-endian word lanes. Lane 0 is the most-significant word.
• NaN, ±∞. 2^NaN = NaN; 2^(+∞) = +∞; 2^(-∞) = +0. Subnormal results may be flushed to ±0 if VSCR[NJ] = 1 (Xenon default).
• No exception, no VSCR[SAT] change, no XER change.
• VMX128 sibling (vexptefp128). Identical semantics with the extended encoding.
• Build natural exp / log via change-of-base. e^x = 2^(x * log2(e)), so combine vmaddfp (multiply-by-constant) with vexptefp.

Related Instructions

• vlogefp — base-2 logarithm (the inverse).
• vrefp — reciprocal estimate.
• vrsqrtefp — reciprocal-square-root estimate.
• vmaddfp — fused multiply-add for change-of-base scaling.
• vmulfp128 — VMX128-only lane-wise float multiply.

IBM Reference

• AIX 7.3 — vexptefp (Vector 2 Raised to the Exponent Estimate Floating Point)
• IBM AltiVec Technology Programmer's Interface Manual, Chapter 5 — Estimate Instructions