21161154d1
- Category pages linked each family as `<slug>.md`, relative to categories/, where no family page lives. They now link `../<category>/<slug>.md`. - Form pages linked a member into its *own* category directory, so every VMX128 sibling (`vsldoi128`) pointed at vmx128/ although its family page is under vmx/. They now link into the family's directory. - Hand-written "Related" and sibling mentions linked other categories' pages as if they were in the same directory. 109 are retargeted through the page index; 29 that pointed a family page at itself (`vrefp128` on vrefp.md) and 6 naming instructions the manual has no page for are plain text now. Regenerated at the existing Canary pin (f21ebd49e): upstream has moved on, and re-pinning belongs in its own change. The generator reports 0 family pages changed and is idempotent; the only dead links left are TEMPLATE.md's placeholders. Co-Authored-By: Claude Opus 5 (1M context) <noreply@anthropic.com>
4.8 KiB
4.8 KiB
vmrglh — Vector Merge Low Half Word
Category: VMX (Altivec) · Form: VX · Opcode:
0x1000014c
Assembler Mnemonics
| Mnemonic | XML entry | Flags | Description |
|---|---|---|---|
vmrglh |
vmrglh |
— | Vector Merge Low Half Word |
Syntax
vmrglh [VD], [VA], [VB]
Encoding
vmrglh — form VX
- Opcode word:
0x1000014c - Primary opcode (bits 0–5):
4 - Extended opcode:
332 - Synchronising: no
| Bits | Field | Meaning |
|---|---|---|
| 0–5 | OPCD |
primary opcode (4) |
| 6–10 | VRT/VD |
destination vector register |
| 11–15 | VRA/VA |
source A vector register |
| 16–20 | VRB/VB |
source B vector register |
| 21–31 | XO |
extended opcode (11 bits) |
Operands
| Field | Role | Description |
|---|---|---|
VA |
vmrglh: read | Source A vector register. |
VB |
vmrglh: read | Source B vector register. |
VD |
vmrglh: write | Destination vector register. |
Register Effects
vmrglh
- Reads (always):
VA,VB - Reads (conditional): none
- Writes (always):
VD - Writes (conditional): none
Status-Register Effects
No condition-register or status-register effects.
Operation (pseudocode)
; No hand-written pseudocode for this instruction yet.
; The authoritative semantics are the Canary emitter snapshot under
; Implementation References; about half of Canary's emitters open
; with the PPC-style definition as a comment (`RD <- (RA) + (RB)`).
; Every side effect is also enumerated in the Register Effects and
; Status-Register Effects tables above.
C Translation Example
/* No hand-written C yet. Translate the Canary emitter snapshot */
/* under Implementation References; its HIR maps directly: */
/* f.LoadGPR(n) / f.StoreGPR(n, v) -> r[n] / r[n] = v */
/* f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n] */
/* f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters */
/* wrap them in f.ByteSwap for the big-endian guest value */
/* f.UpdateCR(n, v) -> CR field n from v's LOW 32 BITS vs 0 */
/* f.LoadCA / f.StoreCA -> xer.CA; f.StoreSAT -> vscr.SAT */
/* i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands */
/* The Register Effects and Status-Register Effects tables above */
/* enumerate every side effect a faithful translation must emit. */
Implementation References
vmrglh
- Canary XML:
tools/ppc-instructions.xml— search formnem="vmrglh" - Canary emitter:
src/xenia/cpu/ppc/ppc_emit_altivec.cc:995 - Sylpheed opcode:
crates/sylpheed-ppc/src/opcode.rs:374 - Sylpheed decoder:
crates/sylpheed-ppc/src/decoder.rs:579
Canary emitter (frozen snapshot @ f21ebd49e9)
int InstrEmit_vmrglh(PPCHIRBuilder& f, const InstrData& i) {
// (VD.w[i]) = (VA.w[i])
// (VD.w[i+1]) = (VB.w[i+1])
// ...
Value* v =
f.Permute(f.LoadConstantVec128(vec128s(4, 12, 5, 13, 6, 14, 7, 15)),
f.LoadVR(i.VX.VA), f.LoadVR(i.VX.VB), INT16_TYPE);
f.StoreVR(i.VX.VD, v);
return 0;
}
Special Cases & Edge Conditions
- Interleave the low (least-significant) four halves of two vectors:
VD = {VA[4], VB[4], VA[5], VB[5], VA[6], VB[6], VA[7], VB[7]}. - Pairs with
vmrghhto interleave the entire 8-half source range. The two instructions plus astvxof each result produces an interleaved 16-half stream from two 8-half streams. - Common usage. Stereo Q15 audio interleave (low half of stream); paired with
vupklshfor sign-extending unpack. - No
VSCRinteraction, no XER, no exceptions. Pure permute. - Aliasing legal.
- No VMX128 sibling.
Related Instructions
vmrghh— the "high half" mirror.vmrglb,vmrglw— low-half merge at byte / word width.vperm,vsldoi— programmable / static permute primitives.vupklsh— sign-extending unpack of the low half (4 halves → 4 words).