21161154d1
- Category pages linked each family as `<slug>.md`, relative to categories/, where no family page lives. They now link `../<category>/<slug>.md`. - Form pages linked a member into its *own* category directory, so every VMX128 sibling (`vsldoi128`) pointed at vmx128/ although its family page is under vmx/. They now link into the family's directory. - Hand-written "Related" and sibling mentions linked other categories' pages as if they were in the same directory. 109 are retargeted through the page index; 29 that pointed a family page at itself (`vrefp128` on vrefp.md) and 6 naming instructions the manual has no page for are plain text now. Regenerated at the existing Canary pin (f21ebd49e): upstream has moved on, and re-pinning belongs in its own change. The generator reports 0 family pages changed and is idempotent; the only dead links left are TEMPLATE.md's placeholders. Co-Authored-By: Claude Opus 5 (1M context) <noreply@anthropic.com>
6.7 KiB
6.7 KiB
vsrw — Vector Shift Right Word
Category: VMX (Altivec) · Form: VX · Opcode:
0x10000284
Assembler Mnemonics
| Mnemonic | XML entry | Flags | Description |
|---|---|---|---|
vsrw |
vsrw |
— | Vector Shift Right Word |
vsrw128 |
vsrw128 |
— | Vector128 Shift Right Word |
Syntax
vsrw [VD], [VA], [VB]
vsrw128 [VD], [VA], [VB]
Encoding
vsrw — form VX
- Opcode word:
0x10000284 - Primary opcode (bits 0–5):
4 - Extended opcode:
644 - Synchronising: no
| Bits | Field | Meaning |
|---|---|---|
| 0–5 | OPCD |
primary opcode (4) |
| 6–10 | VRT/VD |
destination vector register |
| 11–15 | VRA/VA |
source A vector register |
| 16–20 | VRB/VB |
source B vector register |
| 21–31 | XO |
extended opcode (11 bits) |
vsrw128 — form VX128
- Opcode word:
0x180001d0 - Primary opcode (bits 0–5):
6 - Extended opcode:
464 - Synchronising: no
| Bits | Field | Meaning |
|---|---|---|
| 0–5 | OPCD |
primary opcode (4 or 5) |
| 6–10 | VD128l |
destination low 5 bits |
| 11–15 | VA128l |
source A low 5 bits |
| 16–20 | VB128l |
source B low 5 bits |
| 21 | VA128H |
source A high bit |
| 22 | — |
reserved |
| 23–25 | VC |
optional VC / XO sub-field |
| 26 | VA128h |
source A middle bit |
| 27 | — |
reserved |
| 28–29 | VD128h |
destination high 2 bits |
| 30–31 | VB128h |
source B high 2 bits |
Operands
| Field | Role | Description |
|---|---|---|
VA |
vsrw: read; vsrw128: read | Source A vector register. |
VB |
vsrw: read; vsrw128: read | Source B vector register. |
VD |
vsrw: write; vsrw128: write | Destination vector register. |
Register Effects
vsrw
- Reads (always):
VA,VB - Reads (conditional): none
- Writes (always):
VD - Writes (conditional): none
vsrw128
- Reads (always):
VA,VB - Reads (conditional): none
- Writes (always):
VD - Writes (conditional): none
Status-Register Effects
No condition-register or status-register effects.
Operation (pseudocode)
; No hand-written pseudocode for this instruction yet.
; The authoritative semantics are the Canary emitter snapshot under
; Implementation References; about half of Canary's emitters open
; with the PPC-style definition as a comment (`RD <- (RA) + (RB)`).
; Every side effect is also enumerated in the Register Effects and
; Status-Register Effects tables above.
C Translation Example
/* No hand-written C yet. Translate the Canary emitter snapshot */
/* under Implementation References; its HIR maps directly: */
/* f.LoadGPR(n) / f.StoreGPR(n, v) -> r[n] / r[n] = v */
/* f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n] */
/* f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters */
/* wrap them in f.ByteSwap for the big-endian guest value */
/* f.UpdateCR(n, v) -> CR field n from v's LOW 32 BITS vs 0 */
/* f.LoadCA / f.StoreCA -> xer.CA; f.StoreSAT -> vscr.SAT */
/* i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands */
/* The Register Effects and Status-Register Effects tables above */
/* enumerate every side effect a faithful translation must emit. */
Implementation References
vsrw
- Canary XML:
tools/ppc-instructions.xml— search formnem="vsrw" - Canary emitter:
src/xenia/cpu/ppc/ppc_emit_altivec.cc:1650 - Sylpheed opcode:
crates/sylpheed-ppc/src/opcode.rs:466 - Sylpheed decoder:
crates/sylpheed-ppc/src/decoder.rs:606
Canary emitter (frozen snapshot @ f21ebd49e9)
int InstrEmit_vsrw(PPCHIRBuilder& f, const InstrData& i) {
return InstrEmit_vsrw_(f, i.VX.VD, i.VX.VA, i.VX.VB);
}
// ── delegates to (src/xenia/cpu/ppc/ppc_emit_altivec.cc:1644) ──
int InstrEmit_vsrw_(PPCHIRBuilder& f, uint32_t vd, uint32_t va, uint32_t vb) {
// (VD) <- (VA) >> (VB) by words
Value* v = f.VectorShr(f.LoadVR(va), f.LoadVR(vb), INT32_TYPE);
f.StoreVR(vd, v);
return 0;
}
vsrw128
- Canary XML:
tools/ppc-instructions.xml— search formnem="vsrw128" - Canary emitter:
src/xenia/cpu/ppc/ppc_emit_altivec.cc:1653 - Sylpheed opcode:
crates/sylpheed-ppc/src/opcode.rs:467 - Sylpheed decoder:
crates/sylpheed-ppc/src/decoder.rs:810
Canary emitter (frozen snapshot @ f21ebd49e9)
int InstrEmit_vsrw128(PPCHIRBuilder& f, const InstrData& i) {
return InstrEmit_vsrw_(f, VX128_VD128, VX128_VA128, VX128_VB128);
}
// ── delegates to (src/xenia/cpu/ppc/ppc_emit_altivec.cc:1644) ──
int InstrEmit_vsrw_(PPCHIRBuilder& f, uint32_t vd, uint32_t va, uint32_t vb) {
// (VD) <- (VA) >> (VB) by words
Value* v = f.VectorShr(f.LoadVR(va), f.LoadVR(vb), INT32_TYPE);
f.StoreVR(vd, v);
return 0;
}
Special Cases & Edge Conditions
- Per-lane logical right-shift of words.
VD.w[i] = VA.w[i] >> (VB.w[i] & 0x1F)— zero-fill. Low 5 bits of each shift-count word honoured. - Per-lane shift counts. Splat via
vspltw/vspltiswfor uniform shifts. - Zero-fill. Use
vsrawfor sign-preserving right shift. - Big-endian word lanes.
- No flags, no VSCR.
- VMX128 sibling
vsrw128.
Related Instructions
vsraw— arithmetic-right word.vslw— logical-left word.vrlw— word rotate.vsrb,vsrh— byte / half-word logical-right.