84856fc081
The hand-written parts of the manual still described how the retired xenia-rs interpreter behaved: its snapshots, Rust casts and helpers. Each of those 490 statements is now either restated as what Canary's emitters and x64 backend actually do (at the pinned canary_experimental commit), or dropped where it only made sense for xenia-rs. Checking them turned up claims that were wrong, not just outdated: - VSCR[SAT] is never modelled in Canary (DID_SATURATE is a stub and mfvscr cannot see it); the pages said saturating ops set it stickily. - Canary does not implement lswi/lswx/stswi/stswx, dcbi, mtfsb0/mtfsb1, vmsum*, vmhaddshs, vupkhpx/vupklpx, and most SPRs; pages described them as working. - Traps evaluate TO in Canary; stvebx/stvehx/stvewx store one element, not 16 bytes; mtmsrd writes only EE; fres/frsqrte/vrsqrtefp precision claims and the stfs "rounds under RN / sets FPSCR" claim contradicted the spec. - Reservations are a 64 KiB block bitmap plus a value compare, not per-address tracking. Claims that neither Canary's source nor a public spec settles are marked unverified (NI at boot, vmaddcfp128 operand order, estimate bit-exactness). Generated regions are untouched; re-running the generator changes nothing. Co-Authored-By: Claude Opus 5 (1M context) <noreply@anthropic.com>
4.6 KiB
4.6 KiB
vupklpx — Vector Unpack Low Pixel
Category: VMX (Altivec) · Form: VX · Opcode:
0x100003ce
Assembler Mnemonics
| Mnemonic | XML entry | Flags | Description |
|---|---|---|---|
vupklp |
vupklpx |
— | Vector Unpack Low Pixel |
Syntax
vupklpx [VD], [VB]
Encoding
vupklpx — form VX
- Opcode word:
0x100003ce - Primary opcode (bits 0–5):
4 - Extended opcode:
974 - Synchronising: no
| Bits | Field | Meaning |
|---|---|---|
| 0–5 | OPCD |
primary opcode (4) |
| 6–10 | VRT/VD |
destination vector register |
| 11–15 | VRA/VA |
source A vector register |
| 16–20 | VRB/VB |
source B vector register |
| 21–31 | XO |
extended opcode (11 bits) |
Operands
| Field | Role | Description |
|---|---|---|
VB |
vupklpx: read | Source B vector register. |
VD |
vupklpx: write | Destination vector register. |
Register Effects
vupklpx
- Reads (always):
VB - Reads (conditional): none
- Writes (always):
VD - Writes (conditional): none
Status-Register Effects
No condition-register or status-register effects.
Operation (pseudocode)
; No hand-written pseudocode for this instruction yet.
; The authoritative semantics are the Canary emitter snapshot under
; Implementation References; about half of Canary's emitters open
; with the PPC-style definition as a comment (`RD <- (RA) + (RB)`).
; Every side effect is also enumerated in the Register Effects and
; Status-Register Effects tables above.
C Translation Example
/* No hand-written C yet. Translate the Canary emitter snapshot */
/* under Implementation References; its HIR maps directly: */
/* f.LoadGPR(n) / f.StoreGPR(n, v) -> r[n] / r[n] = v */
/* f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n] */
/* f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters */
/* wrap them in f.ByteSwap for the big-endian guest value */
/* f.UpdateCR(n, v) -> CR field n from v's LOW 32 BITS vs 0 */
/* f.LoadCA / f.StoreCA -> xer.CA; f.StoreSAT -> vscr.SAT */
/* i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands */
/* The Register Effects and Status-Register Effects tables above */
/* enumerate every side effect a faithful translation must emit. */
Implementation References
vupklpx
- Canary XML:
tools/ppc-instructions.xml— search formnem="vupklpx" - Canary emitter:
src/xenia/cpu/ppc/ppc_emit_altivec.cc:1993 - Sylpheed opcode:
crates/sylpheed-ppc/src/opcode.rs:490 - Sylpheed decoder:
crates/sylpheed-ppc/src/decoder.rs:633
Canary emitter (frozen snapshot @ f21ebd49e9)
int InstrEmit_vupklpx(PPCHIRBuilder& f, const InstrData& i) {
XEINSTRNOTIMPLEMENTED();
return 1;
}
Special Cases & Edge Conditions
- Unpack the low 4 of 8 pixel half-words. The lower half-words of
VB(VB.h[4..7]) are each decoded from 1-5-5-5 pixel format into a 32-bit word (1.5.5.5 → 1.8.8.8). ⚠️ Canary does not implementvupklpx: its emitter isXEINSTRNOTIMPLEMENTED, so translating one logs "Unimplemented instr" and, with the defaultbreak_on_unimplemented_instructions, breaks. - Output layout.
VD.w[0..3]receive the 4 decoded pixels in big-endian order. - Inverse of the low half of
vpkpx. - No saturation, no flags, no VSCR.
- No VMX128 sibling. VMX128 uses
vupkd3d128for richer formats.
Related Instructions
vupkhpx— high-half pixel unpack.vpkpx— the inverse pack.vupkhsb,vupklsb,vupkhsh,vupklsh— sign-extending unpacks.vupkd3d128— VMX128 D3D-format unpack.