re: read_freg counts SECONDS -- the 32 "flags" are a stopwatch bank
The open question was the unit, not the array. Following the writers of
[phase+88] settles it:
* sub_822710D0(phase, dt), called from ScriptPhase::Update, does
prev[i] = cur[i] then, only while [phase+120][i] == 1, cur[i] += dt --
so +88/+104/+120 are current / previous / running, 32 entries each.
* dt is seconds by a non-circular round trip: frames * (1/60) * 10000
-> clamp 3200 -> * 1e-4, in the timing singleton at [0x828F35B4].
The clamp is 0.32 s, a frame ceiling.
* 675/675 timeline kinds are indices their own phase starts (control
11.2 %), which is why kind is only ever 0 or 5.
Corrects isl-builtins.md twice: set_flag writes 0.0 not 1.0, and
clear_flag clears the running flag rather than the value. Confirms its
grouping of 8/9/93 as one family. Docs only -- all seven ISL artefacts
regenerate byte-identical.
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docs/re/data/isl-timers.txt
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docs/re/data/isl-timers.txt
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# The 32 per-phase stopwatches -- set_flag / read_freg / clear_flag vs the timeline
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Written by hand from tools/re-capture/isl.py; see docs/re/structures/isl-timers.md.
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Claim under test: `[phase+88][i]` only advances while `[phase+120][i] == 1`,
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and built-in 8 is the only thing that sets that flag. So every timeline
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entry's `kind` must be an index its own phase starts, or the entry is dead.
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file phase set_flag(i) started read_freg(i) timeline kinds
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Stage01.ssb 1 [0, 5, 14] [0] {0: 27, 5: 3}
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Stage01.ssb 2 [0, 5, 14] [0] {0: 24, 5: 3}
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Stage02.ssb 1 [0, 5, 8] [0, 8] {0: 21, 5: 4}
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Stage02.ssb 2 [0, 5, 8, 14, 15] [0, 8] {0: 10, 5: 3}
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Stage02.ssb 3 [0, 5, 14, 15] [0] {0: 14, 5: 4}
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Stage03.ssb 1 [0, 5, 14] [0] {0: 16, 5: 4}
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Stage03.ssb 2 [0, 1, 5, 14] [0, 1, 14] {0: 29, 5: 3}
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Stage03.ssb 3 [0, 1, 5, 14, 15] [0, 1] {0: 14, 5: 3}
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Stage04.ssb 1 [0, 5, 14] [0, 14] {0: 8, 5: 3}
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Stage04.ssb 2 [0, 1, 5, 14] [0, 1] {0: 13, 5: 3}
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Stage05.ssb 1 [0, 1, 5] [0, 1] {0: 16, 5: 3}
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Stage05.ssb 2 [0, 5, 8] [0, 8] {0: 6, 5: 3}
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Stage06.ssb 1 [0, 5] [0, 15] {0: 18, 5: 3}
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Stage06.ssb 2 [0, 5, 14, 15] [0] {0: 6, 5: 3}
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Stage06.ssb 3 [0, 1, 5, 14, 15] [0, 1, 15] {0: 7, 5: 3}
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Stage07.ssb 1 [0, 5, 15] [0, 15] {0: 10, 5: 3}
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Stage07.ssb 2 [0, 5, 15] [0, 15] {0: 3, 5: 3}
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Stage08.ssb 1 [0, 1, 5, 15] [0, 1, 15] {0: 17, 5: 5}
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Stage08.ssb 2 [0, 5, 15] [0, 15] {0: 13, 5: 3}
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Stage09.ssb 1 [0, 5, 14, 15] [0] {0: 10, 5: 3}
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Stage09.ssb 2 [0, 5, 14] [0] {0: 7, 5: 3}
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Stage09.ssb 3 [0, 5, 14, 15] [0] {0: 11, 5: 3}
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Stage10.ssb 1 [0, 5, 14, 15] [0] {0: 8, 5: 3}
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Stage11.ssb 1 [0, 5] [0] {0: 14, 5: 3}
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Stage11.ssb 2 [0, 5, 15] [0, 15] {0: 5, 5: 3}
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Stage12.ssb 1 [0, 1, 5, 15] [0, 1, 15] {0: 17, 5: 3}
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Stage13.ssb 1 [0, 2, 5, 15] [0, 2, 15] {0: 25, 5: 3}
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Stage14.ssb 1 [0, 5, 15] [0, 15] {0: 8, 5: 3}
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Stage14.ssb 2 [0, 5, 15] [0, 15] {0: 11, 5: 3}
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Stage15.ssb 1 [0, 5, 15] [0, 15] {0: 20, 5: 3}
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Stage15.ssb 2 [0, 5, 10, 15] [0, 10, 15] {0: 21, 5: 3}
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Stage16.ssb 1 [0, 5] [0] {0: 17, 5: 3}
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Stage18.ssb 1 [0] [] {0: 3}
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Stage19.ssb 1 [0] [] {0: 3}
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Stage20.ssb 1 [0] [] {0: 3}
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Stage21.ssb 1 [0] [] {0: 3}
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Stage22.ssb 1 [0] [] {0: 3}
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Stage23.ssb 1 [0] [] {0: 3}
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Stage24.ssb 1 [0, 1, 5] [0, 1] {0: 11, 5: 3}
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Stage25.ssb 1 [0, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21] [0, 4, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21] {0: 14, 5: 3}
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Stage26.ssb 1 [0, 5] [0] {0: 22, 5: 3}
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Stage27.ssb 1 [0, 5] [0] {0: 16, 5: 3}
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Stage28.ssb 1 [0, 5] [0] {0: 5, 5: 3}
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Stage29.ssb 1 [0, 5] [0] {0: 24, 5: 3}
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timeline entries whose kind is started in the same phase : 675 / 675 = 100.0%
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entry-weighted control (a random index in 0..31) : 11.2%
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read_freg indices started in the same phase : 82 yes / 1 no ['Stage06.ssb ph1 read_freg(15)']
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set_flag argument histogram: {0: 44, 1: 10, 2: 1, 4: 2, 5: 38, 6: 2, 7: 2, 8: 5, 9: 2, 10: 4, 11: 2, 12: 1, 13: 1, 14: 21, 15: 24, 16: 1, 17: 3, 18: 3, 19: 2, 20: 2, 21: 2}
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read_freg argument histogram: {0: 105, 1: 13, 2: 2, 4: 1, 6: 2, 7: 2, 8: 5, 9: 2, 10: 3, 11: 2, 12: 3, 13: 1, 14: 5, 15: 28, 16: 1, 17: 3, 18: 3, 19: 2, 20: 2, 21: 2, None: 31}
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clear_flag argument histogram: {-1: 133}
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