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re(xbg7): the [index][vertex] layout is runtime-verified, and the indices= mystery was batching

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The decoder's central unstated assumption — a block's index buffer sits
immediately before its vertex buffer (`vb - idx_count*2 - pad`, pad <= 3) — was
also the prime suspect for the residual anchor misses, since a capture-proven
`e106_eng_02_l` block was rejected outright. Measured it instead of assuming:

- extended the F10 ship capture to log each draw's index buffer (base, count,
  min/max index) and to key its de-dup on the index range, so every draw batch
  is recorded rather than only the first;
- `examples/capture_ib_truth.rs` places each drawn buffer in the container by its
  dumped positions and scores the capture against our decode.

Stage_S02, 42 drawn buffers placed: our idx_count == the sum of the draw's index
batches for 42/42, the batch union covers the vertex pool exactly for 42/42, and
all 30 single-block cases sit at pad <= 3 (20 at pad 0, 10 at pad 2). The other
12 are grouped pools, where one index pool serves the whole group. So the layout
holds, the decoded index count is exact, and eng_02_l died on the connectivity
gate (since replaced by the winding gate) — not on index location. The shipped
exact-coverage rule is independently confirmed.

The recorded "capture indices=21 vs our 246" disagreement was an artefact of the
old de-dup key: 21 was the first of two batches, 21 + 225 = 246. Any conclusion
from a pre-2026-08-13 capture's `indices=` or `vbase - ibase` is about one batch,
not about the block.

Co-Authored-By: Claude Opus 5 (1M context) <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01NptfmpjdpNCKEez6d2xvA9
This commit is contained in:
Claude (auto-RE)
2026-08-13 05:57:44 +00:00
parent 1b618f500f
commit 6d92e6c114
5 changed files with 334 additions and 5 deletions
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50
docs/re/captures/stage-s02-index-buffer-truth.txt Normal file
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container load constant: vbase - file_offset = 0x17FE3FF4 (93 buffers agree)
decoded 356 resources, 422 distinct vertex offsets
vb 0x13FD6E8 v=25448 batches 8 idx 52077 span 104154 gap 2 decpad 2 cover exact f101_bdy_01(v25448,i52077)
vb 0x192961C v=13172 batches 2 idx 24816 span 49632 gap 0 decpad 0 cover exact f101_bdy_02(v13172,i24816)
vb 0x1BF40F4 v=261 batches 3 idx 498 span 996 gap 41476 decpad 41476 cover exact e_rob_f001(v24,i36) e_rou_f003_Near(v24,i36) e_rou_f101_wep_01(v24,i36) e_rou_f105(v24,i36) _rou_f105_break(v261,i498) e_rou_f106(v24,i36) e_rou_f302_barrel(v24,i36) e_rou_f302_base(v24,i36) e_rou_f303_barrel(v24,i36) e_rou_f303_base(v24,i36) e_rou_e007_Far(v24,i36) e_rou_e007_Near(v24,i36) e_rou_e010_Far(v24,i36) e_rou_e010_Near(v24,i36) e_rou_e105(v24,i36) e_rou_e105_wep_01(v24,i36) e_rou_e106(v24,i36) e_rou_e106_eng(v24,i36) e_rou_e106_wep_02_01(v24,i36) e_rou_e106_wep_02_joint(v24,i36) e_rou_e108_Missile_open(v24,i36) e_rou_e201(v24,i36) e_rou_e302_barrel(v24,i36) e_rou_e302_base(v24,i36) e_rou_e303_barrel_Near(v24,i36) e_rou_e303_base_Near(v24,i36) e_rou_e501(v24,i36)
vb 0x1C0F67C v=82 batches 1 idx 144 span 288 gap 133672 decpad 133672 cover exact _rou_f105_break(v82,i144)
vb 0x1C1D92C v=220 batches 3 idx 384 span 768 gap 179872 decpad 179872 cover exact _rou_f105_break(v220,i384)
vb 0x1C1EDCC v=80 batches 2 idx 132 span 264 gap 184888 decpad 184888 cover exact _rou_f105_break(v80,i132)
vb 0x1C1F54C v=148 batches 3 idx 288 span 576 gap 186232 decpad 186232 cover exact _rou_f105_break(v148,i288)
vb 0x1C2032C v=156 batches 1 idx 246 span 492 gap 189292 decpad 189292 cover exact _rou_f105_break(v156,i246)
vb 0x1C2953C v=84 batches 1 idx 156 span 312 gap 220012 decpad 220012 cover exact _rou_f105_break(v84,i156)
vb 0x1C2AF1C v=122 batches 3 idx 351 span 702 gap 224882 decpad 224882 cover exact _rou_f105_break(v122,i351)
vb 0x1C2BA8C v=24 batches 2 idx 36 span 72 gap 227736 decpad 227736 cover exact _rou_f105_break(v24,i36)
vb 0x1ECB4C0 v=2446 batches 4 idx 5466 span 10932 gap 0 decpad 0 cover exact f105_bdy_01_m(v2446,i5466)
vb 0x227AC94 v=1692 batches 3 idx 3651 span 7302 gap 2 decpad 2 cover exact f106_bdy_02_l(v1692,i3651)
vb 0x22C2EF0 v=686 batches 2 idx 1506 span 3012 gap 0 decpad 0 cover exact f106_bdy_03_l(v686,i1506)
vb 0x22C8F50 v=1558 batches 3 idx 4098 span 8196 gap 0 decpad 0 cover exact f106_bdy_03_m(v1558,i4098)
vb 0x22ED420 v=261 batches 4 idx 561 span 1122 gap 2 decpad 2 cover exact f106_eng_01_l(v261,i561)
vb 0x22F0430 v=1162 batches 4 idx 3018 span 6036 gap 0 decpad 0 cover exact f106_eng_01_m(v1162,i3018)
vb 0x2326C9C v=254 batches 2 idx 495 span 990 gap 2 decpad 2 cover exact f106_sld_01_l(v254,i495)
vb 0x233B3FC v=254 batches 2 idx 495 span 990 gap 2 decpad 2 cover exact f106_sld_02_l(v254,i495)
vb 0x233D700 v=627 batches 3 idx 1434 span 2868 gap 0 decpad 0 cover exact f106_sld_02_m(v627,i1434)
vb 0x24CE5F4 v=32 batches 1 idx 60 span 120 gap 0 decpad 0 cover exact f303_body_l(v32,i60)
vb 0x28EA1D4 v=156 batches 2 idx 228 span 456 gap 0 decpad 0 cover exact e105_bdy_01_l(v156,i228)
vb 0x28F7514 v=107 batches 3 idx 180 span 360 gap 0 decpad 0 cover exact e105_bdy_02_l(v107,i180)
vb 0x291E1E8 v=185 batches 2 idx 285 span 570 gap 2 decpad 2 cover exact e105_bdy_03_l(v185,i285)
vb 0x29A4788 v=181 batches 3 idx 318 span 636 gap 0 decpad 0 cover exact e105_bdy_04_l(v181,i318)
vb 0x29B78B8 v=93 batches 2 idx 117 span 234 gap 2 decpad 2 cover exact e105_bdy_05_l(v93,i117)
vb 0x2A22574 v=41 batches 1 idx 51 span 102 gap 2 decpad 2 cover exact e105_bdy_06_l(v41,i51)
vb 0x2A47BAC v=77 batches 1 idx 111 span 222 gap 2 decpad 2 cover exact e105_brg_l(v77,i111)
vb 0x2A9FDA0 v=76 batches 1 idx 90 span 180 gap 0 decpad 0 cover exact e105_eng_01_l(v76,i90)
vb 0x2ACE840 v=60 batches 1 idx 90 span 180 gap 0 decpad 0 cover exact e105_wep_01_l(v60,i90)
vb 0x2D1FEE8 v=119 batches 2 idx 246 span 492 gap 0 decpad 0 cover exact e106_bdy_01_l(v119,i246)
vb 0x2D315D8 v=119 batches 2 idx 246 span 492 gap 0 decpad 0 cover exact e106_bdy_02_l(v119,i246)
vb 0x2D492C4 v=146 batches 2 idx 324 span 648 gap 0 decpad 0 cover exact e106_bdy_03_l(v146,i324)
vb 0x2D7363C v=179 batches 2 idx 399 span 798 gap 2 decpad 2 cover exact e106_bdy_04_l(v179,i399)
vb 0x2D7A418 v=51 batches 2 idx 126 span 252 gap 0 decpad 0 cover exact e106_brg_01_l(v51,i126)
vb 0x2DB0CCC v=58 batches 2 idx 96 span 192 gap 0 decpad 0 cover exact e106_eng_01_l(v58,i96)
vb 0x2DB632C v=44 batches 2 idx 72 span 144 gap 0 decpad 0 cover exact e106_eng_02_l(v44,i72)
vb 0x2DC305C v=82 batches 2 idx 168 span 336 gap 0 decpad 0 cover exact e106_wep_02_01_l(v82,i168)
vb 0x329077C v=6000 batches 1 idx 6000 span 12000 gap 0 decpad 0 cover exact n006_02(v6000,i6000)
vb 0x3434030 v=4 batches 1 idx 6 span 12 gap 24 decpad 24 cover exact n301_02B(v4,i6)
vb 0x3434090 v=4 batches 1 idx 6 span 12 gap 108 decpad 108 cover exact n301_02B(v4,i6)
vb 0x34340F0 v=4 batches 1 idx 6 span 12 gap 192 decpad 192 cover exact n301_02B(v4,i6)
placed 42 drawn buffers in this container
DECODER layout assumption — whole index buffer at vb - 2*idx_count - pad: pad 0 20 · pad 1..3 10 · elsewhere 12 · not decoded here 0
index extent: our idx_count == sum of captured batches for 42 buffers, differs for 0
vertex-pool coverage by the union of batches: exact 42 · short 0