re: timer_set's second argument is a SECOND countdown, not a warning threshold

mission-phase-timers.md left 180 open as "a limit and a warning
threshold is the obvious reading, but not established".  Reading
sub_822639B8 -- ScriptPhase::Update 0x82263528, same dt as the
stopwatch bank -- settles it the other way:

    if running: [+304] += dt
    if armed:   [+308] -= dt   while [+308] > 0
                else [+312] -= dt, clamped at 0

[+312] is never compared with [+308]; it is decremented, and only in
the A<=0 arm.  Two sequential countdowns.  Disc-wide the second
argument is 180 in all 29 timer_set sites while the first varies
(600 x19, 1200 x8, 900, 1800).

Built-ins 123-127 are vtable slots 90-94 on five scalars at
[phase+304..320].  125 and 126 have ZERO call sites in all 28 scripts:
the script arms, starts and stops this clock but never reads it.

Corrects mission-phase-timers.md, which merged this clock with
stopwatch 0 -- timer_resume starts [+304], set_flag(0) one instruction
later starts the stopwatch the timeline's kind=0 reads.

Docs only; all seven ISL artefacts regenerate byte-identical.

docs/re/structures/isl-timers.md

@@ -109,11 +109,13 @@ in a coherent block of stages) — checked before believing.
 
 ## 🟡 What this leaves
 
-* The **naming**. `set_flag` / `read_freg` / `clear_flag` describe none of this;
-  `timer_start` / `timer_elapsed` / `timer_stop` would. They are not renamed here
-  because built-ins 127/123/124 already hold `timer_set` / `timer_resume` /
-  `timer_stop` in the corpus for a *different* timer, and untangling the two is
-  its own change. Every artefact regenerates byte-identical as a result.
+* The **naming**. `set_flag` / `read_freg` / `clear_flag` describe none of this.
+  ✅ The other timer is now read — [isl-mission-timer](isl-mission-timer.md) —
+  so the collision is understood: 123/124/125/126/127 act on five *scalar*
+  fields (`[phase+304…320]`), this family on a 32-entry *bank*. `stopwatch_start`
+  / `stopwatch_elapsed` / `stopwatch_stop` would separate them. Still not renamed
+  here, so every artefact regenerates byte-identical; the rename is its own
+  change and its own artefact diff.
 * The **one exception**: `read_freg(15)` in Stage 06 phase 1 is not started by a
   `set_flag(15)` in that phase. Cross-phase carry-over or a start in the
   unreached code — not chased.