re: resolve every ISL condition's comparand -- the clear conditions are readable

The deque ops are an EXPRESSION STACK: push the left operand, evaluate the right
(a built-in call, whose result lands in special[0]), pop the comparand back into
special[1], compare.  Tracking that through the linear decode is enough to recover
what each site tests.

Evidence the model is right, not just plausible:
  push vs pop across all 28 stages          1877 vs 1877
  files that underflow or end unbalanced    0 of 28
  Stage 02 pop.i sites followed by cmp.i    319 / 319
  ops immediately before a pop.i            call x313, cmp.a x6

isl.conditions() recovers 7563 condition sites disc-wide with 0.0% left as an
unresolved special[N]; 83.2% have a built-in call as the LHS and 99.7% compare
against a plain number.  Most-tested: hp_pct_test 1955, unit_state 1257,
unit_relation 796, dist_lt 450, unit_alive 413.

They read as conditions now:
  if unit_alive(TCN105) != 1
  if hp_pct_test(ADT308, 0) != 1
  if dist_lt(ADT308, TCN000, 15000) != 1      (world unit = 1 m, so 15 km)
  if unit_state(ADT308) == 1

data/isl-stage02-conditions.txt was a stale artefact with NO generator -- the thing
isl_report.py's docstring complained about.  It has one now (isl_report.py
conditions).  The calls and phase-ends artefacts both regenerate byte-identical, so
the change is additive.

Recorded rather than glossed: 15 of Stage 02's 965 sites (1.6%) attribute the LHS to
end_coroutine, which returns no value -- the tracker sets special[0] on EVERY call,
so those show a stale value and are wrong, not imprecise.  The fix is to set it only
for built-ins that write [phase+164], which the vtable work makes checkable.

docs/re/BACKLOG.md

@@ -1412,9 +1412,26 @@ premise was wrong.**
   db's own `vptr_writes`. `unit_state` = slot 184 = `0x8226ADF0`, which indexes
   `[phase+324]` by `local[4]` and writes its answer to **`[phase+164]` =
   `special[0]`**. So: **result → `special[0]`, comparand popped → `special[1]`,
-  then `cmp.i` + branch.** ▶️ **Still open:** the other 111 vtable slots are a
+  then `cmp.i` + branch.** ~~▶️ **Still open:** the other 111 vtable slots are a
   lookup but unread; which comparand each site pushes (needs `push.i` tracked
-  through the decode); the 35 non-vtable built-ins; the vtable's length. The condition lives in the `op10`/`op13` poll loop upstream of
+  through the decode); the 35 non-vtable built-ins; the vtable's length.~~
+  ✅ **(2026-08-27) COMPARANDS RESOLVED — [structures/isl-conditions](structures/isl-conditions.md).**
+  The deques are an **expression stack**: push the left operand, evaluate the
+  right (result → `special[0]`), pop → `special[1]`, compare. Evidence: push/pop
+  balance **1877/1877 across 28 stages with ZERO underflows**, and **319/319**
+  Stage-02 `pop.i` sites are immediately followed by `cmp.i`. `isl.conditions()`
+  now recovers **7563 condition sites disc-wide with 0.0 % left unresolved**
+  (83.2 % have a built-in call as LHS, 99.7 % compare against a plain number).
+  `data/isl-stage02-conditions.txt` finally has a generator
+  (`isl_report.py conditions`); the other two artefacts regenerate identical.
+  Top predicates: `hp_pct_test` 1955, `unit_state` 1257, `unit_relation` 796,
+  `dist_lt` 450. 🟡 **1.6 % are WRONG:** 15 sites attribute the LHS to
+  `end_coroutine`, which returns nothing — the tracker sets `special[0]` on every
+  call, so those show a stale value. Fix = only set it for built-ins that write
+  `[phase+164]`. ▶️ **Still open:** the 35 unnamed built-ins (`builtin16` 132
+  sites, `builtin105` 117, `builtin103` 115 — each now a vtable-slot lookup);
+  which condition guards each `END_PHASE` (needs the control flow between them);
+  the vtable's length. The condition lives in the `op10`/`op13` poll loop upstream of
   the outro — e.g. phase 3 polls `unit_state(ADT308)` and branches back to
   `0xFEB4` until it passes. Artefact: `data/isl-stage02-phase-ends.txt`.
 * 🐛 **(2026-08-25) The nav fix is NOT fully reliable.** `dialog_up.py` works on