//
// Generated by Microsoft (R) HLSL Shader Compiler 10.1
//
//
// Buffer Definitions: 
//
// cbuffer XeTextureLoadConstants
// {
//
//   uint xe_texture_load_guest_base;   // Offset:    0 Size:     4
//   uint xe_texture_load_guest_pitch;  // Offset:    4 Size:     4
//   uint xe_texture_load_host_base;    // Offset:    8 Size:     4
//   uint xe_texture_load_host_pitch;   // Offset:   12 Size:     4
//   uint3 xe_texture_load_size_texels; // Offset:   16 Size:    12
//   bool xe_texture_load_is_3d;        // Offset:   28 Size:     4
//   uint3 xe_texture_load_size_blocks; // Offset:   32 Size:    12
//   uint xe_texture_load_endianness;   // Offset:   44 Size:     4
//   uint2 xe_texture_guest_storage_width_height;// Offset:   48 Size:     8
//   uint xe_texture_load_guest_format; // Offset:   56 Size:     4 [unused]
//   uint3 xe_texture_load_guest_mip_offset;// Offset:   64 Size:    12
//
// }
//
//
// Resource Bindings:
//
// Name                                 Type  Format         Dim      ID      HLSL Bind  Count
// ------------------------------ ---------- ------- ----------- ------- -------------- ------
// xe_texture_load_source            texture    byte         r/o      T0             t0      1 
// xe_texture_load_dest                  UAV    byte         r/w      U0             u0      1 
// XeTextureLoadConstants            cbuffer      NA          NA     CB0            cb0      1 
//
//
//
// Input signature:
//
// Name                 Index   Mask Register SysValue  Format   Used
// -------------------- ----- ------ -------- -------- ------- ------
// no Input
//
// Output signature:
//
// Name                 Index   Mask Register SysValue  Format   Used
// -------------------- ----- ------ -------- -------- ------- ------
// no Output
cs_5_1
dcl_globalFlags refactoringAllowed
dcl_constantbuffer CB0[0:0][5], immediateIndexed, space=0
dcl_resource_raw T0[0:0], space=0
dcl_uav_raw U0[0:0], space=0
dcl_input vThreadID.xyz
dcl_temps 10
dcl_thread_group 8, 32, 1
ishl r0.x, vThreadID.x, l(2)
mov r0.yz, vThreadID.yyzy
uge r1.xyz, r0.xyzx, CB0[0][2].xyzx
or r0.w, r1.y, r1.x
or r0.w, r1.z, r0.w
if_nz r0.w
  ret 
endif 
iadd r1.xyz, r0.xyzx, CB0[0][4].xyzx
ieq r0.z, CB0[0][0].y, l(-1)
if_nz r0.z
  if_nz CB0[0][1].w
    iadd r2.xyzw, r1.xxxx, l(0, 1, 2, 3)
    ushr r3.xyz, r1.zyyz, l(2, 4, 3, 0)
    ushr r0.zw, CB0[0][3].yyyx, l(0, 0, 4, 5)
    imad r0.z, r3.x, r0.z, r3.y
    iadd r1.w, r3.z, r3.x
    bfi r3.x, l(1), l(1), r1.w, l(0)
    ushr r4.xyzw, r2.xyzw, l(3, 3, 3, 3)
    iadd r3.xyzw, r3.xxxx, r4.xyzw
    bfi r3.xyzw, l(2, 2, 2, 2), l(1, 1, 1, 1), r3.xyzw, l(0, 0, 0, 0)
    bfi r3.xyzw, l(1, 1, 1, 1), l(0, 0, 0, 0), r1.wwww, r3.xyzw
    ishl r1.w, r1.y, l(11)
    and r1.w, r1.w, l(0x00003000)
    bfi r4.xyzw, l(3, 3, 3, 3), l(9, 9, 9, 9), r2.xyzw, r1.wwww
    ushr r4.xyzw, r4.xyzw, l(6, 6, 6, 6)
    ushr r2.xyzw, r2.xyzw, l(5, 5, 5, 5)
    imad r2.xyzw, r0.zzzz, r0.wwww, r2.xyzw
    and r5.xyzw, r4.xyzw, l(240, 240, 240, 240)
    bfi r6.xyzw, l(19, 19, 19, 19), l(11, 11, 11, 11), r2.xyzw, l(0, 0, 0, 0)
    imad r6.xyzw, r5.xyzw, l(2, 2, 2, 2), r6.xyzw
    bfi r6.xyzw, l(4, 4, 4, 4), l(0, 0, 0, 0), r4.xyzw, r6.xyzw
    bfi r6.xyzw, l(2, 2, 2, 2), l(9, 9, 9, 9), r1.zzzz, r6.xyzw
    bfi r7.xyzw, l(1, 1, 1, 1), l(4, 4, 4, 4), r1.yyyy, r6.xyzw
    ubfe r6.xyzw, l(3, 3, 3, 3), l(6, 6, 6, 6), r6.xyzw
    and r8.xyzw, r3.xyzw, l(6, 6, 6, 6)
    bfi r3.xyzw, l(1, 1, 1, 1), l(8, 8, 8, 8), r3.xyzw, l(0, 0, 0, 0)
    imad r3.xyzw, r6.xyzw, l(32, 32, 32, 32), r3.xyzw
    imad r3.xyzw, r8.xyzw, l(4, 4, 4, 4), r3.xyzw
    bfi r2.xyzw, l(19, 19, 19, 19), l(14, 14, 14, 14), r2.xyzw, l(0, 0, 0, 0)
    imad r2.xyzw, r5.xyzw, l(16, 16, 16, 16), r2.xyzw
    bfi r2.xyzw, l(4, 4, 4, 4), l(3, 3, 3, 3), r4.xyzw, r2.xyzw
    bfi r2.xyzw, l(2, 2, 2, 2), l(12, 12, 12, 12), r1.zzzz, r2.xyzw
    bfi r2.xyzw, l(1, 1, 1, 1), l(7, 7, 7, 7), r1.yyyy, r2.xyzw
    bfi r2.xyzw, l(9, 9, 9, 9), l(3, 3, 3, 3), r3.xyzw, r2.xyzw
    bfi r2.xyzw, l(6, 6, 6, 6), l(0, 0, 0, 0), r7.xyzw, r2.xyzw
  else 
    iadd r3.xyzw, r1.xxxx, l(0, 1, 2, 3)
    ushr r4.xyzw, r3.xyzw, l(5, 5, 5, 5)
    ushr r0.zw, r1.yyyy, l(0, 0, 5, 2)
    iadd r1.w, CB0[0][3].x, l(31)
    ushr r1.w, r1.w, l(5)
    imad r4.xyzw, r0.zzzz, r1.wwww, r4.xyzw
    ishl r5.xy, r1.yyyy, l(5, 7, 0, 0)
    and r5.xy, r5.xyxx, l(448, 2048, 0, 0)
    bfi r6.xyzw, l(3, 3, 3, 3), l(3, 3, 3, 3), r3.xyzw, r5.xxxx
    ishl r0.z, r5.x, l(1)
    bfi r7.xyzw, l(3, 3, 3, 3), l(4, 4, 4, 4), r3.xyzw, r0.zzzz
    and r7.xyzw, r7.xyzw, l(992, 992, 992, 992)
    bfi r8.xyzw, l(22, 22, 22, 22), l(10, 10, 10, 10), r4.xyzw, r7.xyzw
    bfi r8.xyzw, l(4, 4, 4, 4), l(0, 0, 0, 0), r6.xyzw, r8.xyzw
    bfi r8.xyzw, l(1, 1, 1, 1), l(4, 4, 4, 4), r1.yyyy, r8.xyzw
    ishl r9.xyzw, r7.xyzw, l(3, 3, 3, 3)
    bfi r9.xyzw, l(22, 22, 22, 22), l(13, 13, 13, 13), r4.xyzw, r9.xyzw
    bfi r9.xyzw, l(4, 4, 4, 4), l(3, 3, 3, 3), r6.xyzw, r9.xyzw
    bfi r9.xyzw, l(1, 1, 1, 1), l(7, 7, 7, 7), r1.yyyy, r9.xyzw
    bfi r5.xyzw, l(12, 12, 12, 12), l(0, 0, 0, 0), r5.yyyy, r9.xyzw
    ishl r7.xyzw, r7.xyzw, l(2, 2, 2, 2)
    bfi r4.xyzw, l(22, 22, 22, 22), l(12, 12, 12, 12), r4.xyzw, r7.xyzw
    bfi r4.xyzw, l(4, 4, 4, 4), l(2, 2, 2, 2), r6.xyzw, r4.xyzw
    bfi r4.xyzw, l(1, 1, 1, 1), l(6, 6, 6, 6), r1.yyyy, r4.xyzw
    and r4.xyzw, r4.xyzw, l(1792, 1792, 1792, 1792)
    iadd r4.xyzw, r5.xyzw, r4.xyzw
    ushr r3.xyzw, r3.xyzw, l(3, 3, 3, 3)
    and r0.z, r0.w, l(2)
    iadd r3.xyzw, r0.zzzz, r3.xyzw
    bfi r3.xyzw, l(2, 2, 2, 2), l(6, 6, 6, 6), r3.xyzw, l(0, 0, 0, 0)
    iadd r3.xyzw, r4.xyzw, r3.xyzw
    bfi r2.xyzw, l(6, 6, 6, 6), l(0, 0, 0, 0), r8.xyzw, r3.xyzw
  endif 
else 
  ishl r0.z, r1.x, l(3)
  iadd r0.w, CB0[0][2].y, l(31)
  and r0.w, r0.w, l(-32)
  imad r0.w, r1.z, r0.w, r1.y
  imad r0.z, r0.w, CB0[0][0].y, r0.z
  iadd r2.xyzw, r0.zzzz, l(0, 8, 16, 24)
endif 
iadd r1.xyzw, r2.xyzw, CB0[0][0].xxxx
ld_raw r2.xz, r1.x, T0[0].yxxx
ld_raw r2.yw, r1.y, T0[0].xyxx
ld_raw r3.xy, r1.z, T0[0].xyxx
ld_raw r3.zw, r1.w, T0[0].xxxy
ushr r0.z, CB0[0][2].w, l(1)
xor r0.z, r0.z, CB0[0][2].w
and r0.z, r0.z, l(1)
if_nz r0.z
  ishl r1.xyzw, r2.zxwy, l(8, 8, 8, 8)
  and r1.xyzw, r1.xyzw, l(0xff00ff00, 0xff00ff00, 0xff00ff00, 0xff00ff00)
  ushr r4.xyzw, r2.zxwy, l(8, 8, 8, 8)
  and r4.xyzw, r4.xyzw, l(0x00ff00ff, 0x00ff00ff, 0x00ff00ff, 0x00ff00ff)
  iadd r2.xyzw, r1.ywxz, r4.ywxz
endif 
and r0.w, CB0[0][2].w, l(2)
if_nz r0.w
  ushr r1.xyzw, r2.zxwy, l(16, 16, 16, 16)
  bfi r2.xyzw, l(16, 16, 16, 16), l(16, 16, 16, 16), r2.xyzw, r1.ywxz
  mov r1.xy, r2.zwzz
else 
  mov r1.xy, r2.zwzz
endif 
if_nz r0.z
  ishl r4.xyzw, r3.xyzw, l(8, 8, 8, 8)
  and r4.xyzw, r4.xyzw, l(0xff00ff00, 0xff00ff00, 0xff00ff00, 0xff00ff00)
  ushr r5.xyzw, r3.xyzw, l(8, 8, 8, 8)
  and r5.xyzw, r5.xyzw, l(0x00ff00ff, 0x00ff00ff, 0x00ff00ff, 0x00ff00ff)
  iadd r3.xyzw, r4.xyzw, r5.xyzw
endif 
if_nz r0.w
  ushr r4.xyzw, r3.xyzw, l(16, 16, 16, 16)
  bfi r4.xyzw, l(16, 16, 16, 16), l(16, 16, 16, 16), r3.xyzw, r4.xyzw
  mov r1.zw, r4.xxxz
  mov r2.zw, r4.yyyw
else 
  mov r1.zw, r3.xxxz
  mov r2.zw, r3.yyyw
endif 
ishl r0.xy, r0.xyxx, l(2, 2, 0, 0)
imad r0.z, vThreadID.z, CB0[0][1].y, r0.y
imad r0.x, r0.z, CB0[0][0].w, r0.x
iadd r0.x, r0.x, CB0[0][0].z
mov r0.z, CB0[0][1].y
mov r0.w, r0.y
mov r3.x, r0.x
mov r3.y, l(0)
loop 
  uge r3.z, r3.y, l(4)
  breakc_nz r3.z
  ult r3.z, r3.y, l(2)
  movc r4.xyzw, r3.zzzz, r1.xyzw, r2.xyzw
  bfi r3.z, l(1), l(4), r3.y, l(0)
  ushr r4.xyzw, r4.xyzw, r3.zzzz
  bfi r5.xyzw, l(8, 8, 8, 8), l(4, 4, 4, 4), r4.xyzw, l(0, 0, 0, 0)
  bfi r5.xyzw, l(4, 4, 4, 4), l(0, 0, 0, 0), r4.xyzw, r5.xyzw
  ishl r6.xyzw, r4.xyzw, l(8, 8, 8, 8)
  and r6.xyzw, r6.xyzw, l(0x000ff000, 0x000ff000, 0x000ff000, 0x000ff000)
  iadd r5.xyzw, r5.xyzw, r6.xyzw
  ishl r6.xyzw, r4.xyzw, l(12, 12, 12, 12)
  and r6.xyzw, r6.xyzw, l(0x0ff00000, 0x0ff00000, 0x0ff00000, 0x0ff00000)
  iadd r5.xyzw, r5.xyzw, r6.xyzw
  ishl r4.xyzw, r4.xyzw, l(16, 16, 16, 16)
  bfi r4.xyzw, l(28, 28, 28, 28), l(0, 0, 0, 0), r5.xyzw, r4.xyzw
  store_raw U0[0].xyzw, r3.x, r4.xyzw
  iadd r0.w, r0.w, l(1)
  uge r3.z, r0.w, r0.z
  if_nz r3.z
    ret 
  endif 
  iadd r3.x, r3.x, CB0[0][0].w
  iadd r3.y, r3.y, l(1)
endloop 
ret 
// Approximately 162 instruction slots used
