//
// Generated by Microsoft (R) HLSL Shader Compiler 10.1
//
//
// Buffer Definitions: 
//
// cbuffer XeTextureLoadConstants
// {
//
//   uint xe_texture_load_guest_base;   // Offset:    0 Size:     4
//   uint xe_texture_load_guest_pitch;  // Offset:    4 Size:     4
//   uint xe_texture_load_host_base;    // Offset:    8 Size:     4
//   uint xe_texture_load_host_pitch;   // Offset:   12 Size:     4
//   uint3 xe_texture_load_size_texels; // Offset:   16 Size:    12 [unused]
//   bool xe_texture_load_is_3d;        // Offset:   28 Size:     4
//   uint3 xe_texture_load_size_blocks; // Offset:   32 Size:    12
//   uint xe_texture_load_endianness;   // Offset:   44 Size:     4
//   uint2 xe_texture_guest_storage_width_height;// Offset:   48 Size:     8
//   uint xe_texture_load_guest_format; // Offset:   56 Size:     4 [unused]
//   uint3 xe_texture_load_guest_mip_offset;// Offset:   64 Size:    12
//
// }
//
//
// Resource Bindings:
//
// Name                                 Type  Format         Dim      ID      HLSL Bind  Count
// ------------------------------ ---------- ------- ----------- ------- -------------- ------
// xe_texture_load_source            texture    byte         r/o      T0             t0      1 
// xe_texture_load_dest                  UAV    byte         r/w      U0             u0      1 
// XeTextureLoadConstants            cbuffer      NA          NA     CB0            cb0      1 
//
//
//
// Input signature:
//
// Name                 Index   Mask Register SysValue  Format   Used
// -------------------- ----- ------ -------- -------- ------- ------
// no Input
//
// Output signature:
//
// Name                 Index   Mask Register SysValue  Format   Used
// -------------------- ----- ------ -------- -------- ------- ------
// no Output
cs_5_1
dcl_globalFlags refactoringAllowed
dcl_constantbuffer CB0[0:0][5], immediateIndexed, space=0
dcl_resource_raw T0[0:0], space=0
dcl_uav_raw U0[0:0], space=0
dcl_input vThreadID.xyz
dcl_temps 7
dcl_thread_group 16, 16, 1
uge r0.xyz, vThreadID.xyzx, CB0[0][2].xyzx
or r0.x, r0.y, r0.x
or r0.x, r0.z, r0.x
if_nz r0.x
  ret 
endif 
iadd r0.xyzw, vThreadID.zyyx, CB0[0][4].zyyx
ieq r1.x, CB0[0][0].y, l(-1)
if_nz r1.x
  if_nz CB0[0][1].w
    ushr r1.xyzw, r0.xyzw, l(2, 4, 3, 3)
    ushr r2.xy, CB0[0][3].yxyy, l(4, 5, 0, 0)
    imad r0.y, r1.x, r2.x, r1.y
    iadd r1.x, r1.z, r1.x
    bfi r1.y, l(1), l(1), r1.x, l(0)
    iadd r1.y, r1.w, r1.y
    bfi r1.y, l(2), l(1), r1.y, l(0)
    bfi r1.x, l(1), l(0), r1.x, r1.y
    ishl r1.y, r0.z, l(12)
    and r1.y, r1.y, l(0x00006000)
    bfi r1.y, l(3), l(10), r0.w, r1.y
    ushr r1.y, r1.y, l(6)
    ushr r1.z, r0.w, l(5)
    imad r0.y, r0.y, r2.y, r1.z
    bfi r1.zw, l(0, 0, 18, 18), l(0, 0, 12, 15), r0.yyyy, l(0, 0, 0, 0)
    imad r1.yz, r1.yyyy, l(0, 2, 16, 0), r1.zzwz
    bfi r1.yz, l(0, 2, 2, 0), l(0, 10, 13, 0), r0.xxxx, r1.yyzy
    bfi r0.y, l(1), l(4), r0.z, l(0)
    ubfe r1.w, l(3), l(6), r1.y
    and r2.x, r1.x, l(6)
    bfi r1.x, l(1), l(8), r1.x, l(0)
    imad r1.x, r1.w, l(32), r1.x
    imad r1.x, r2.x, l(4), r1.x
    bfi r1.yz, l(0, 5, 5, 0), l(0, 0, 3, 0), r0.yyyy, r1.yyzy
    bfi r0.y, l(9), l(3), r1.x, r1.z
    bfi r0.y, l(6), l(0), r1.y, r0.y
  else 
    ushr r1.xyzw, r0.wzwz, l(5, 5, 3, 2)
    iadd r2.x, CB0[0][3].x, l(31)
    ushr r2.x, r2.x, l(5)
    imad r1.x, r1.y, r2.x, r1.x
    ishl r1.y, r0.z, l(7)
    and r2.xy, r1.yyyy, l(1792, 2048, 0, 0)
    bfi r1.y, l(3), l(5), r0.w, r2.x
    bfi r1.y, l(21), l(11), r1.x, r1.y
    bfi r2.z, l(1), l(4), r0.z, l(0)
    iadd r1.y, r1.y, r2.z
    ishl r2.xw, r2.xxxx, l(3, 0, 0, 2)
    bfi r2.xw, l(3, 0, 0, 3), l(8, 0, 0, 7), r0.wwww, r2.xxxw
    bfi r2.xw, l(21, 0, 0, 21), l(14, 0, 0, 13), r1.xxxx, r2.xxxw
    imad r2.xz, r2.zzzz, l(8, 0, 4, 0), r2.xxwx
    bfi r1.x, l(12), l(0), r2.y, r2.x
    and r2.x, r2.z, l(1792)
    iadd r1.x, r1.x, r2.x
    and r1.w, r1.w, l(2)
    iadd r1.z, r1.w, r1.z
    bfi r1.z, l(2), l(6), r1.z, l(0)
    iadd r1.x, r1.x, r1.z
    bfi r0.y, l(6), l(0), r1.y, r1.x
  endif 
else 
  ishl r0.w, r0.w, l(4)
  iadd r1.x, CB0[0][2].y, l(31)
  and r1.x, r1.x, l(-32)
  imad r0.x, r0.x, r1.x, r0.z
  imad r0.y, r0.x, CB0[0][0].y, r0.w
endif 
iadd r0.x, r0.y, CB0[0][0].x
ishl r0.x, r0.x, l(2)
iadd r0.yzw, r0.xxxx, l(0, 16, 32, 48)
ld_raw r1.xyzw, r0.x, T0[0].xyzw
ld_raw r2.xyzw, r0.y, T0[0].xyzw
ld_raw r3.xyzw, r0.z, T0[0].xyzw
ld_raw r0.xyzw, r0.w, T0[0].xyzw
ushr r4.x, CB0[0][2].w, l(1)
xor r4.x, r4.x, CB0[0][2].w
and r4.x, r4.x, l(1)
if_nz r4.x
  ishl r5.xyzw, r1.xyzw, l(8, 8, 8, 8)
  and r5.xyzw, r5.xyzw, l(0xff00ff00, 0xff00ff00, 0xff00ff00, 0xff00ff00)
  ushr r6.xyzw, r1.xyzw, l(8, 8, 8, 8)
  and r6.xyzw, r6.xyzw, l(0x00ff00ff, 0x00ff00ff, 0x00ff00ff, 0x00ff00ff)
  iadd r1.xyzw, r5.xyzw, r6.xyzw
endif 
and r4.y, CB0[0][2].w, l(2)
if_nz r4.y
  ushr r5.xyzw, r1.xyzw, l(16, 16, 16, 16)
  bfi r1.xyzw, l(16, 16, 16, 16), l(16, 16, 16, 16), r1.xyzw, r5.xyzw
endif 
if_nz r4.x
  ishl r5.xyzw, r2.xyzw, l(8, 8, 8, 8)
  and r5.xyzw, r5.xyzw, l(0xff00ff00, 0xff00ff00, 0xff00ff00, 0xff00ff00)
  ushr r6.xyzw, r2.xyzw, l(8, 8, 8, 8)
  and r6.xyzw, r6.xyzw, l(0x00ff00ff, 0x00ff00ff, 0x00ff00ff, 0x00ff00ff)
  iadd r2.xyzw, r5.xyzw, r6.xyzw
endif 
if_nz r4.y
  ushr r5.xyzw, r2.xyzw, l(16, 16, 16, 16)
  bfi r2.xyzw, l(16, 16, 16, 16), l(16, 16, 16, 16), r2.xyzw, r5.xyzw
endif 
if_nz r4.x
  ishl r5.xyzw, r3.xyzw, l(8, 8, 8, 8)
  and r5.xyzw, r5.xyzw, l(0xff00ff00, 0xff00ff00, 0xff00ff00, 0xff00ff00)
  ushr r6.xyzw, r3.xyzw, l(8, 8, 8, 8)
  and r6.xyzw, r6.xyzw, l(0x00ff00ff, 0x00ff00ff, 0x00ff00ff, 0x00ff00ff)
  iadd r3.xyzw, r5.xyzw, r6.xyzw
endif 
if_nz r4.y
  ushr r5.xyzw, r3.xyzw, l(16, 16, 16, 16)
  bfi r3.xyzw, l(16, 16, 16, 16), l(16, 16, 16, 16), r3.xyzw, r5.xyzw
endif 
if_nz r4.x
  ishl r5.xyzw, r0.xyzw, l(8, 8, 8, 8)
  and r5.xyzw, r5.xyzw, l(0xff00ff00, 0xff00ff00, 0xff00ff00, 0xff00ff00)
  ushr r6.xyzw, r0.xyzw, l(8, 8, 8, 8)
  and r6.xyzw, r6.xyzw, l(0x00ff00ff, 0x00ff00ff, 0x00ff00ff, 0x00ff00ff)
  iadd r0.xyzw, r5.xyzw, r6.xyzw
endif 
if_nz r4.y
  ushr r4.xyzw, r0.xyzw, l(16, 16, 16, 16)
  bfi r0.xyzw, l(16, 16, 16, 16), l(16, 16, 16, 16), r0.xyzw, r4.xyzw
endif 
ishl r4.xy, vThreadID.xyxx, l(1, 1, 0, 0)
ishl r4.z, CB0[0][2].y, l(1)
ishl r4.x, r4.x, l(4)
imad r4.y, vThreadID.z, r4.z, r4.y
imad r4.x, r4.y, CB0[0][0].w, r4.x
iadd r4.x, r4.x, CB0[0][0].z
store_raw U0[0].xyzw, r4.x, r1.xyzw
iadd r1.x, r4.x, l(16)
store_raw U0[0].xyzw, r1.x, r2.xyzw
iadd r1.x, r4.x, CB0[0][0].w
store_raw U0[0].xyzw, r1.x, r3.xyzw
iadd r1.y, r1.x, l(16)
store_raw U0[0].xyzw, r1.y, r0.xyzw
ret 
// Approximately 136 instruction slots used
