//
// Generated by Microsoft (R) HLSL Shader Compiler 10.1
//
//
// Buffer Definitions: 
//
// cbuffer XeHostDepthStoreRectangleConstants
// {
//
//   uint xe_host_depth_store_rectangle;// Offset:    0 Size:     4
//
// }
//
// cbuffer XeHostDepthStoreRenderTargetConstants
// {
//
//   uint xe_host_depth_store_render_target;// Offset:    0 Size:     4
//
// }
//
//
// Resource Bindings:
//
// Name                                 Type  Format         Dim      ID      HLSL Bind  Count
// ------------------------------ ---------- ------- ----------- ------- -------------- ------
// xe_host_depth_store_source        texture   float          2d      T0             t0      1 
// xe_host_depth_store_dest              UAV   uint4         buf      U0             u0      1 
// XeHostDepthStoreRectangleConstants    cbuffer      NA          NA     CB0            cb0      1 
// XeHostDepthStoreRenderTargetConstants    cbuffer      NA          NA     CB1            cb1      1 
//
//
//
// Input signature:
//
// Name                 Index   Mask Register SysValue  Format   Used
// -------------------- ----- ------ -------- -------- ------- ------
// no Input
//
// Output signature:
//
// Name                 Index   Mask Register SysValue  Format   Used
// -------------------- ----- ------ -------- -------- ------- ------
// no Output
cs_5_1
dcl_globalFlags refactoringAllowed
dcl_constantbuffer CB0[0:0][1], immediateIndexed, space=0
dcl_constantbuffer CB1[1:1][1], immediateIndexed, space=0
dcl_resource_texture2d (float,float,float,float) T0[0:0], space=0
dcl_uav_typed_buffer (uint,uint,uint,uint) U0[0:0], space=0
dcl_input vThreadID.xy
dcl_temps 4
dcl_thread_group 8, 8, 1
ubfe r0.x, l(2), l(10), CB1[1][0].x
ubfe r0.y, l(10), l(20), CB0[0][0].x
imul null, r0.y, r0.x, r0.y
ult r0.y, r0.y, vThreadID.x
if_nz r0.y
  ret 
endif 
ushr r1.y, CB0[0][0].x, l(10)
mov r1.x, CB0[0][0].x
bfi r0.yz, l(0, 10, 10, 0), l(0, 3, 3, 0), r1.xxyx, l(0, 0, 0, 0)
ishl r1.x, vThreadID.x, l(3)
mov r1.y, vThreadID.y
imad r1.xy, r0.yzyy, r0.xxxx, r1.xyxx
and r0.y, CB1[1][0].x, l(1023)
imul null, r0.xz, r0.xxxx, l(80, 0, 16, 0)
udiv r2.xy, null, r1.xyxx, r0.xzxx
imad r0.y, r2.y, r0.y, r2.x
imad r2.xy, -r2.xyxx, r0.xzxx, r1.xyxx
imul null, r0.z, r0.z, r0.x
imad r0.x, r2.y, r0.x, r2.x
imad r0.x, r0.y, r0.z, r0.x
ushr r0.x, r0.x, l(2)
mov r1.zw, l(0,0,0,0)
ld r2.x, r1.xyww, T0[0].xyzw
iadd r3.xyzw, r1.xyww, l(1, 0, 0, 0)
ld r2.y, r3.xyzw, T0[0].yxzw
iadd r3.xyzw, r1.xyww, l(2, 0, 0, 0)
ld r2.z, r3.xyzw, T0[0].yzxw
iadd r3.xyzw, r1.xyww, l(3, 0, 0, 0)
ld r2.w, r3.xyzw, T0[0].yzwx
store_uav_typed U0[0].xyzw, r0.xxxx, r2.xyzw
iadd r0.y, r0.x, l(1)
iadd r2.xyzw, r1.xyww, l(4, 0, 0, 0)
ld r2.x, r2.xyzw, T0[0].xyzw
iadd r3.xyzw, r1.xyww, l(5, 0, 0, 0)
ld r2.y, r3.xyzw, T0[0].yxzw
iadd r3.xyzw, r1.xyww, l(6, 0, 0, 0)
ld r2.z, r3.xyzw, T0[0].yzxw
iadd r1.xyzw, r1.xyzw, l(7, 0, 0, 0)
ld r2.w, r1.xyzw, T0[0].yzwx
store_uav_typed U0[0].xyzw, r0.yyyy, r2.xyzw
ret 
// Approximately 42 instruction slots used
