//
// Generated by Microsoft (R) HLSL Shader Compiler 10.1
//
//
// Buffer Definitions: 
//
// cbuffer XeHostDepthStoreRectangleConstants
// {
//
//   uint xe_host_depth_store_rectangle;// Offset:    0 Size:     4
//
// }
//
// cbuffer XeHostDepthStoreRenderTargetConstants
// {
//
//   uint xe_host_depth_store_render_target;// Offset:    0 Size:     4
//
// }
//
//
// Resource Bindings:
//
// Name                                 Type  Format         Dim      ID      HLSL Bind  Count
// ------------------------------ ---------- ------- ----------- ------- -------------- ------
// xe_host_depth_store_source        texture   float        2dMS      T0             t0      1 
// xe_host_depth_store_dest              UAV   uint4         buf      U0             u0      1 
// XeHostDepthStoreRectangleConstants    cbuffer      NA          NA     CB0            cb0      1 
// XeHostDepthStoreRenderTargetConstants    cbuffer      NA          NA     CB1            cb1      1 
//
//
//
// Input signature:
//
// Name                 Index   Mask Register SysValue  Format   Used
// -------------------- ----- ------ -------- -------- ------- ------
// no Input
//
// Output signature:
//
// Name                 Index   Mask Register SysValue  Format   Used
// -------------------- ----- ------ -------- -------- ------- ------
// no Output
cs_5_1
dcl_globalFlags refactoringAllowed
dcl_constantbuffer CB0[0:0][1], immediateIndexed, space=0
dcl_constantbuffer CB1[1:1][1], immediateIndexed, space=0
dcl_resource_texture2dms(0) (float,float,float,float) T0[0:0], space=0
dcl_uav_typed_buffer (uint,uint,uint,uint) U0[0:0], space=0
dcl_input vThreadID.xy
dcl_temps 5
dcl_thread_group 8, 8, 1
ubfe r0.x, l(2), l(10), CB1[1][0].x
ushr r0.y, vThreadID.x, l(1)
ubfe r0.z, l(10), l(20), CB0[0][0].x
imul null, r0.z, r0.x, r0.z
ult r0.y, r0.z, r0.y
if_nz r0.y
  ret 
endif 
ushr r1.y, CB0[0][0].x, l(10)
mov r1.x, CB0[0][0].x
bfi r0.yz, l(0, 10, 10, 0), l(0, 3, 3, 0), r1.xxyx, l(0, 0, 0, 0)
ishl r1.x, vThreadID.x, l(2)
ushr r1.y, vThreadID.y, l(1)
imad r1.xy, r0.yzyy, r0.xxxx, r1.xyxx
bfi r0.yz, l(0, 31, 31, 0), l(0, 1, 1, 0), r1.xxyx, vThreadID.xxyx
and r0.w, CB1[1][0].x, l(1023)
imul null, r2.xy, r0.xxxx, l(80, 16, 0, 0)
udiv r2.zw, null, r0.yyyz, r2.xxxy
imad r0.x, r2.w, r0.w, r2.z
imad r0.yz, -r2.zzwz, r2.xxyx, r0.yyzy
imul null, r0.w, r2.y, r2.x
imad r0.y, r0.z, r2.x, r0.y
imad r0.x, r0.x, r0.w, r0.y
ushr r0.x, r0.x, l(2)
bfi r0.y, l(1), l(1), vThreadID.y, l(0)
iadd r0.zw, r0.yyyx, l(0, 0, 1, 1)
mov r1.zw, l(0,0,0,0)
ldms r2.x, r1.xyww, T0[0].xyzw, r0.y
ldms r2.y, r1.xyzw, T0[0].yxzw, r0.z
iadd r3.xyzw, r1.xyxy, l(2, 0, 1, 0)
mov r4.xy, r3.zwzz
mov r4.zw, l(0,0,0,0)
ldms r2.z, r4.xyww, T0[0].yzxw, r0.y
ldms r2.w, r4.xyzw, T0[0].yzwx, r0.z
store_uav_typed U0[0].xyzw, r0.xxxx, r2.xyzw
mov r3.zw, l(0,0,0,0)
ldms r2.x, r3.xyww, T0[0].xyzw, r0.y
ldms r2.y, r3.xyzw, T0[0].yxzw, r0.z
iadd r1.xy, r1.xyxx, l(3, 0, 0, 0)
mov r1.zw, l(0,0,0,0)
ldms r2.z, r1.xyww, T0[0].yzxw, r0.y
ldms r2.w, r1.xyzw, T0[0].yzwx, r0.z
store_uav_typed U0[0].xyzw, r0.wwww, r2.xyzw
ret 
// Approximately 44 instruction slots used
