test_fdiv_1_GEN:
  #_ REGISTER_IN f1 0x0000000000000000
  #_ REGISTER_IN f2 0x0000000000000000
  fdiv f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x0000000000000000
  #_ REGISTER_OUT f2 0x0000000000000000
  #_ REGISTER_OUT f3 0x7FF8000000000000

test_fdiv_1_cr_GEN:
  #_ REGISTER_IN f1 0x0000000000000000
  #_ REGISTER_IN f2 0x0000000000000000
  fdiv. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x0000000000000000
  #_ REGISTER_OUT f2 0x0000000000000000
  #_ REGISTER_OUT f3 0x7FF8000000000000
  #_ REGISTER_OUT cr 0x0A000000

test_fdiv_2_GEN:
  #_ REGISTER_IN f1 0x0000000000000000
  #_ REGISTER_IN f2 0x8000000000000000
  fdiv f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x0000000000000000
  #_ REGISTER_OUT f2 0x8000000000000000
  #_ REGISTER_OUT f3 0x7FF8000000000000

test_fdiv_2_cr_GEN:
  #_ REGISTER_IN f1 0x0000000000000000
  #_ REGISTER_IN f2 0x8000000000000000
  fdiv. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x0000000000000000
  #_ REGISTER_OUT f2 0x8000000000000000
  #_ REGISTER_OUT f3 0x7FF8000000000000
  #_ REGISTER_OUT cr 0x0A000000

test_fdiv_3_GEN:
  #_ REGISTER_IN f1 0x0000000000000000
  #_ REGISTER_IN f2 0x0000000000000001
  fdiv f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x0000000000000000
  #_ REGISTER_OUT f2 0x0000000000000001
  #_ REGISTER_OUT f3 0x0000000000000000

test_fdiv_3_cr_GEN:
  #_ REGISTER_IN f1 0x0000000000000000
  #_ REGISTER_IN f2 0x0000000000000001
  fdiv. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x0000000000000000
  #_ REGISTER_OUT f2 0x0000000000000001
  #_ REGISTER_OUT f3 0x0000000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fdiv_4_GEN:
  #_ REGISTER_IN f1 0x0000000000000000
  #_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
  fdiv f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x0000000000000000
  #_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
  #_ REGISTER_OUT f3 0x0000000000000000

test_fdiv_4_cr_GEN:
  #_ REGISTER_IN f1 0x0000000000000000
  #_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
  fdiv. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x0000000000000000
  #_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
  #_ REGISTER_OUT f3 0x0000000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fdiv_5_GEN:
  #_ REGISTER_IN f1 0x0000000000000000
  #_ REGISTER_IN f2 0x3FF0000000000000
  fdiv f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x0000000000000000
  #_ REGISTER_OUT f2 0x3FF0000000000000
  #_ REGISTER_OUT f3 0x0000000000000000

test_fdiv_5_cr_GEN:
  #_ REGISTER_IN f1 0x0000000000000000
  #_ REGISTER_IN f2 0x3FF0000000000000
  fdiv. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x0000000000000000
  #_ REGISTER_OUT f2 0x3FF0000000000000
  #_ REGISTER_OUT f3 0x0000000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fdiv_6_GEN:
  #_ REGISTER_IN f1 0x0000000000000000
  #_ REGISTER_IN f2 0xBFF0000000000000
  fdiv f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x0000000000000000
  #_ REGISTER_OUT f2 0xBFF0000000000000
  #_ REGISTER_OUT f3 0x8000000000000000

test_fdiv_6_cr_GEN:
  #_ REGISTER_IN f1 0x0000000000000000
  #_ REGISTER_IN f2 0xBFF0000000000000
  fdiv. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x0000000000000000
  #_ REGISTER_OUT f2 0xBFF0000000000000
  #_ REGISTER_OUT f3 0x8000000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fdiv_7_GEN:
  #_ REGISTER_IN f1 0x0000000000000000
  #_ REGISTER_IN f2 0xC1E0000000000000
  fdiv f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x0000000000000000
  #_ REGISTER_OUT f2 0xC1E0000000000000
  #_ REGISTER_OUT f3 0x8000000000000000

test_fdiv_7_cr_GEN:
  #_ REGISTER_IN f1 0x0000000000000000
  #_ REGISTER_IN f2 0xC1E0000000000000
  fdiv. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x0000000000000000
  #_ REGISTER_OUT f2 0xC1E0000000000000
  #_ REGISTER_OUT f3 0x8000000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fdiv_8_GEN:
  #_ REGISTER_IN f1 0x0000000000000000
  #_ REGISTER_IN f2 0x41DFFFFFFFC00000
  fdiv f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x0000000000000000
  #_ REGISTER_OUT f2 0x41DFFFFFFFC00000
  #_ REGISTER_OUT f3 0x0000000000000000

test_fdiv_8_cr_GEN:
  #_ REGISTER_IN f1 0x0000000000000000
  #_ REGISTER_IN f2 0x41DFFFFFFFC00000
  fdiv. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x0000000000000000
  #_ REGISTER_OUT f2 0x41DFFFFFFFC00000
  #_ REGISTER_OUT f3 0x0000000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fdiv_9_GEN:
  #_ REGISTER_IN f1 0x0000000000000000
  #_ REGISTER_IN f2 0x7FF0000000000000
  fdiv f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x0000000000000000
  #_ REGISTER_OUT f2 0x7FF0000000000000
  #_ REGISTER_OUT f3 0x0000000000000000

test_fdiv_9_cr_GEN:
  #_ REGISTER_IN f1 0x0000000000000000
  #_ REGISTER_IN f2 0x7FF0000000000000
  fdiv. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x0000000000000000
  #_ REGISTER_OUT f2 0x7FF0000000000000
  #_ REGISTER_OUT f3 0x0000000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fdiv_10_GEN:
  #_ REGISTER_IN f1 0x0000000000000000
  #_ REGISTER_IN f2 0xFFF0000000000000
  fdiv f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x0000000000000000
  #_ REGISTER_OUT f2 0xFFF0000000000000
  #_ REGISTER_OUT f3 0x8000000000000000

test_fdiv_10_cr_GEN:
  #_ REGISTER_IN f1 0x0000000000000000
  #_ REGISTER_IN f2 0xFFF0000000000000
  fdiv. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x0000000000000000
  #_ REGISTER_OUT f2 0xFFF0000000000000
  #_ REGISTER_OUT f3 0x8000000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fdiv_11_GEN:
  #_ REGISTER_IN f1 0x0000000000000000
  #_ REGISTER_IN f2 0xFFF8000000000000
  fdiv f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x0000000000000000
  #_ REGISTER_OUT f2 0xFFF8000000000000
  #_ REGISTER_OUT f3 0xFFF8000000000000

test_fdiv_11_cr_GEN:
  #_ REGISTER_IN f1 0x0000000000000000
  #_ REGISTER_IN f2 0xFFF8000000000000
  fdiv. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x0000000000000000
  #_ REGISTER_OUT f2 0xFFF8000000000000
  #_ REGISTER_OUT f3 0xFFF8000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fdiv_12_GEN:
  #_ REGISTER_IN f1 0x0000000000000000
  #_ REGISTER_IN f2 0xFFF4000000000000
  fdiv f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x0000000000000000
  #_ REGISTER_OUT f2 0xFFF4000000000000
  #_ REGISTER_OUT f3 0xFFFC000000000000

test_fdiv_12_cr_GEN:
  #_ REGISTER_IN f1 0x0000000000000000
  #_ REGISTER_IN f2 0xFFF4000000000000
  fdiv. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x0000000000000000
  #_ REGISTER_OUT f2 0xFFF4000000000000
  #_ REGISTER_OUT f3 0xFFFC000000000000
  #_ REGISTER_OUT cr 0x0A000000

test_fdiv_13_GEN:
  #_ REGISTER_IN f1 0x8000000000000000
  #_ REGISTER_IN f2 0x0000000000000000
  fdiv f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x8000000000000000
  #_ REGISTER_OUT f2 0x0000000000000000
  #_ REGISTER_OUT f3 0x7FF8000000000000

test_fdiv_13_cr_GEN:
  #_ REGISTER_IN f1 0x8000000000000000
  #_ REGISTER_IN f2 0x0000000000000000
  fdiv. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x8000000000000000
  #_ REGISTER_OUT f2 0x0000000000000000
  #_ REGISTER_OUT f3 0x7FF8000000000000
  #_ REGISTER_OUT cr 0x0A000000

test_fdiv_14_GEN:
  #_ REGISTER_IN f1 0x8000000000000000
  #_ REGISTER_IN f2 0x8000000000000000
  fdiv f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x8000000000000000
  #_ REGISTER_OUT f2 0x8000000000000000
  #_ REGISTER_OUT f3 0x7FF8000000000000

test_fdiv_14_cr_GEN:
  #_ REGISTER_IN f1 0x8000000000000000
  #_ REGISTER_IN f2 0x8000000000000000
  fdiv. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x8000000000000000
  #_ REGISTER_OUT f2 0x8000000000000000
  #_ REGISTER_OUT f3 0x7FF8000000000000
  #_ REGISTER_OUT cr 0x0A000000

test_fdiv_15_GEN:
  #_ REGISTER_IN f1 0x8000000000000000
  #_ REGISTER_IN f2 0x0000000000000001
  fdiv f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x8000000000000000
  #_ REGISTER_OUT f2 0x0000000000000001
  #_ REGISTER_OUT f3 0x8000000000000000

test_fdiv_15_cr_GEN:
  #_ REGISTER_IN f1 0x8000000000000000
  #_ REGISTER_IN f2 0x0000000000000001
  fdiv. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x8000000000000000
  #_ REGISTER_OUT f2 0x0000000000000001
  #_ REGISTER_OUT f3 0x8000000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fdiv_16_GEN:
  #_ REGISTER_IN f1 0x8000000000000000
  #_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
  fdiv f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x8000000000000000
  #_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
  #_ REGISTER_OUT f3 0x8000000000000000

test_fdiv_16_cr_GEN:
  #_ REGISTER_IN f1 0x8000000000000000
  #_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
  fdiv. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x8000000000000000
  #_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
  #_ REGISTER_OUT f3 0x8000000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fdiv_17_GEN:
  #_ REGISTER_IN f1 0x8000000000000000
  #_ REGISTER_IN f2 0x3FF0000000000000
  fdiv f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x8000000000000000
  #_ REGISTER_OUT f2 0x3FF0000000000000
  #_ REGISTER_OUT f3 0x8000000000000000

test_fdiv_17_cr_GEN:
  #_ REGISTER_IN f1 0x8000000000000000
  #_ REGISTER_IN f2 0x3FF0000000000000
  fdiv. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x8000000000000000
  #_ REGISTER_OUT f2 0x3FF0000000000000
  #_ REGISTER_OUT f3 0x8000000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fdiv_18_GEN:
  #_ REGISTER_IN f1 0x8000000000000000
  #_ REGISTER_IN f2 0xBFF0000000000000
  fdiv f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x8000000000000000
  #_ REGISTER_OUT f2 0xBFF0000000000000
  #_ REGISTER_OUT f3 0x0000000000000000

test_fdiv_18_cr_GEN:
  #_ REGISTER_IN f1 0x8000000000000000
  #_ REGISTER_IN f2 0xBFF0000000000000
  fdiv. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x8000000000000000
  #_ REGISTER_OUT f2 0xBFF0000000000000
  #_ REGISTER_OUT f3 0x0000000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fdiv_19_GEN:
  #_ REGISTER_IN f1 0x8000000000000000
  #_ REGISTER_IN f2 0xC1E0000000000000
  fdiv f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x8000000000000000
  #_ REGISTER_OUT f2 0xC1E0000000000000
  #_ REGISTER_OUT f3 0x0000000000000000

test_fdiv_19_cr_GEN:
  #_ REGISTER_IN f1 0x8000000000000000
  #_ REGISTER_IN f2 0xC1E0000000000000
  fdiv. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x8000000000000000
  #_ REGISTER_OUT f2 0xC1E0000000000000
  #_ REGISTER_OUT f3 0x0000000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fdiv_20_GEN:
  #_ REGISTER_IN f1 0x8000000000000000
  #_ REGISTER_IN f2 0x41DFFFFFFFC00000
  fdiv f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x8000000000000000
  #_ REGISTER_OUT f2 0x41DFFFFFFFC00000
  #_ REGISTER_OUT f3 0x8000000000000000

test_fdiv_20_cr_GEN:
  #_ REGISTER_IN f1 0x8000000000000000
  #_ REGISTER_IN f2 0x41DFFFFFFFC00000
  fdiv. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x8000000000000000
  #_ REGISTER_OUT f2 0x41DFFFFFFFC00000
  #_ REGISTER_OUT f3 0x8000000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fdiv_21_GEN:
  #_ REGISTER_IN f1 0x8000000000000000
  #_ REGISTER_IN f2 0x7FF0000000000000
  fdiv f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x8000000000000000
  #_ REGISTER_OUT f2 0x7FF0000000000000
  #_ REGISTER_OUT f3 0x8000000000000000

test_fdiv_21_cr_GEN:
  #_ REGISTER_IN f1 0x8000000000000000
  #_ REGISTER_IN f2 0x7FF0000000000000
  fdiv. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x8000000000000000
  #_ REGISTER_OUT f2 0x7FF0000000000000
  #_ REGISTER_OUT f3 0x8000000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fdiv_22_GEN:
  #_ REGISTER_IN f1 0x8000000000000000
  #_ REGISTER_IN f2 0xFFF0000000000000
  fdiv f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x8000000000000000
  #_ REGISTER_OUT f2 0xFFF0000000000000
  #_ REGISTER_OUT f3 0x0000000000000000

test_fdiv_22_cr_GEN:
  #_ REGISTER_IN f1 0x8000000000000000
  #_ REGISTER_IN f2 0xFFF0000000000000
  fdiv. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x8000000000000000
  #_ REGISTER_OUT f2 0xFFF0000000000000
  #_ REGISTER_OUT f3 0x0000000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fdiv_23_GEN:
  #_ REGISTER_IN f1 0x8000000000000000
  #_ REGISTER_IN f2 0xFFF8000000000000
  fdiv f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x8000000000000000
  #_ REGISTER_OUT f2 0xFFF8000000000000
  #_ REGISTER_OUT f3 0xFFF8000000000000

test_fdiv_23_cr_GEN:
  #_ REGISTER_IN f1 0x8000000000000000
  #_ REGISTER_IN f2 0xFFF8000000000000
  fdiv. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x8000000000000000
  #_ REGISTER_OUT f2 0xFFF8000000000000
  #_ REGISTER_OUT f3 0xFFF8000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fdiv_24_GEN:
  #_ REGISTER_IN f1 0x8000000000000000
  #_ REGISTER_IN f2 0xFFF4000000000000
  fdiv f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x8000000000000000
  #_ REGISTER_OUT f2 0xFFF4000000000000
  #_ REGISTER_OUT f3 0xFFFC000000000000

test_fdiv_24_cr_GEN:
  #_ REGISTER_IN f1 0x8000000000000000
  #_ REGISTER_IN f2 0xFFF4000000000000
  fdiv. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x8000000000000000
  #_ REGISTER_OUT f2 0xFFF4000000000000
  #_ REGISTER_OUT f3 0xFFFC000000000000
  #_ REGISTER_OUT cr 0x0A000000

test_fdiv_25_GEN:
  #_ REGISTER_IN f1 0x0000000000000001
  #_ REGISTER_IN f2 0x0000000000000000
  fdiv f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x0000000000000001
  #_ REGISTER_OUT f2 0x0000000000000000
  #_ REGISTER_OUT f3 0x7FF0000000000000

test_fdiv_25_cr_GEN:
  #_ REGISTER_IN f1 0x0000000000000001
  #_ REGISTER_IN f2 0x0000000000000000
  fdiv. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x0000000000000001
  #_ REGISTER_OUT f2 0x0000000000000000
  #_ REGISTER_OUT f3 0x7FF0000000000000
  #_ REGISTER_OUT cr 0x08000000

test_fdiv_26_GEN:
  #_ REGISTER_IN f1 0x0000000000000001
  #_ REGISTER_IN f2 0x8000000000000000
  fdiv f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x0000000000000001
  #_ REGISTER_OUT f2 0x8000000000000000
  #_ REGISTER_OUT f3 0xFFF0000000000000

test_fdiv_26_cr_GEN:
  #_ REGISTER_IN f1 0x0000000000000001
  #_ REGISTER_IN f2 0x8000000000000000
  fdiv. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x0000000000000001
  #_ REGISTER_OUT f2 0x8000000000000000
  #_ REGISTER_OUT f3 0xFFF0000000000000
  #_ REGISTER_OUT cr 0x08000000

test_fdiv_27_GEN:
  #_ REGISTER_IN f1 0x0000000000000001
  #_ REGISTER_IN f2 0x0000000000000001
  fdiv f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x0000000000000001
  #_ REGISTER_OUT f2 0x0000000000000001
  #_ REGISTER_OUT f3 0x3FF0000000000000

test_fdiv_27_cr_GEN:
  #_ REGISTER_IN f1 0x0000000000000001
  #_ REGISTER_IN f2 0x0000000000000001
  fdiv. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x0000000000000001
  #_ REGISTER_OUT f2 0x0000000000000001
  #_ REGISTER_OUT f3 0x3FF0000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fdiv_28_GEN:
  #_ REGISTER_IN f1 0x0000000000000001
  #_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
  fdiv f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x0000000000000001
  #_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
  #_ REGISTER_OUT f3 0x3CB0000000000001

test_fdiv_28_cr_GEN:
  #_ REGISTER_IN f1 0x0000000000000001
  #_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
  fdiv. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x0000000000000001
  #_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
  #_ REGISTER_OUT f3 0x3CB0000000000001
  #_ REGISTER_OUT cr 0x08000000

test_fdiv_29_GEN:
  #_ REGISTER_IN f1 0x0000000000000001
  #_ REGISTER_IN f2 0x3FF0000000000000
  fdiv f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x0000000000000001
  #_ REGISTER_OUT f2 0x3FF0000000000000
  #_ REGISTER_OUT f3 0x0000000000000001

test_fdiv_29_cr_GEN:
  #_ REGISTER_IN f1 0x0000000000000001
  #_ REGISTER_IN f2 0x3FF0000000000000
  fdiv. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x0000000000000001
  #_ REGISTER_OUT f2 0x3FF0000000000000
  #_ REGISTER_OUT f3 0x0000000000000001
  #_ REGISTER_OUT cr 0x00000000

test_fdiv_30_GEN:
  #_ REGISTER_IN f1 0x0000000000000001
  #_ REGISTER_IN f2 0xBFF0000000000000
  fdiv f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x0000000000000001
  #_ REGISTER_OUT f2 0xBFF0000000000000
  #_ REGISTER_OUT f3 0x8000000000000001

test_fdiv_30_cr_GEN:
  #_ REGISTER_IN f1 0x0000000000000001
  #_ REGISTER_IN f2 0xBFF0000000000000
  fdiv. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x0000000000000001
  #_ REGISTER_OUT f2 0xBFF0000000000000
  #_ REGISTER_OUT f3 0x8000000000000001
  #_ REGISTER_OUT cr 0x00000000

test_fdiv_31_GEN:
  #_ REGISTER_IN f1 0x0000000000000001
  #_ REGISTER_IN f2 0xC1E0000000000000
  fdiv f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x0000000000000001
  #_ REGISTER_OUT f2 0xC1E0000000000000
  #_ REGISTER_OUT f3 0x8000000000000000

test_fdiv_31_cr_GEN:
  #_ REGISTER_IN f1 0x0000000000000001
  #_ REGISTER_IN f2 0xC1E0000000000000
  fdiv. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x0000000000000001
  #_ REGISTER_OUT f2 0xC1E0000000000000
  #_ REGISTER_OUT f3 0x8000000000000000
  #_ REGISTER_OUT cr 0x08000000

test_fdiv_32_GEN:
  #_ REGISTER_IN f1 0x0000000000000001
  #_ REGISTER_IN f2 0x41DFFFFFFFC00000
  fdiv f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x0000000000000001
  #_ REGISTER_OUT f2 0x41DFFFFFFFC00000
  #_ REGISTER_OUT f3 0x0000000000000000

test_fdiv_32_cr_GEN:
  #_ REGISTER_IN f1 0x0000000000000001
  #_ REGISTER_IN f2 0x41DFFFFFFFC00000
  fdiv. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x0000000000000001
  #_ REGISTER_OUT f2 0x41DFFFFFFFC00000
  #_ REGISTER_OUT f3 0x0000000000000000
  #_ REGISTER_OUT cr 0x08000000

test_fdiv_33_GEN:
  #_ REGISTER_IN f1 0x0000000000000001
  #_ REGISTER_IN f2 0x7FF0000000000000
  fdiv f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x0000000000000001
  #_ REGISTER_OUT f2 0x7FF0000000000000
  #_ REGISTER_OUT f3 0x0000000000000000

test_fdiv_33_cr_GEN:
  #_ REGISTER_IN f1 0x0000000000000001
  #_ REGISTER_IN f2 0x7FF0000000000000
  fdiv. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x0000000000000001
  #_ REGISTER_OUT f2 0x7FF0000000000000
  #_ REGISTER_OUT f3 0x0000000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fdiv_34_GEN:
  #_ REGISTER_IN f1 0x0000000000000001
  #_ REGISTER_IN f2 0xFFF0000000000000
  fdiv f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x0000000000000001
  #_ REGISTER_OUT f2 0xFFF0000000000000
  #_ REGISTER_OUT f3 0x8000000000000000

test_fdiv_34_cr_GEN:
  #_ REGISTER_IN f1 0x0000000000000001
  #_ REGISTER_IN f2 0xFFF0000000000000
  fdiv. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x0000000000000001
  #_ REGISTER_OUT f2 0xFFF0000000000000
  #_ REGISTER_OUT f3 0x8000000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fdiv_35_GEN:
  #_ REGISTER_IN f1 0x0000000000000001
  #_ REGISTER_IN f2 0xFFF8000000000000
  fdiv f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x0000000000000001
  #_ REGISTER_OUT f2 0xFFF8000000000000
  #_ REGISTER_OUT f3 0xFFF8000000000000

test_fdiv_35_cr_GEN:
  #_ REGISTER_IN f1 0x0000000000000001
  #_ REGISTER_IN f2 0xFFF8000000000000
  fdiv. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x0000000000000001
  #_ REGISTER_OUT f2 0xFFF8000000000000
  #_ REGISTER_OUT f3 0xFFF8000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fdiv_36_GEN:
  #_ REGISTER_IN f1 0x0000000000000001
  #_ REGISTER_IN f2 0xFFF4000000000000
  fdiv f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x0000000000000001
  #_ REGISTER_OUT f2 0xFFF4000000000000
  #_ REGISTER_OUT f3 0xFFFC000000000000

test_fdiv_36_cr_GEN:
  #_ REGISTER_IN f1 0x0000000000000001
  #_ REGISTER_IN f2 0xFFF4000000000000
  fdiv. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x0000000000000001
  #_ REGISTER_OUT f2 0xFFF4000000000000
  #_ REGISTER_OUT f3 0xFFFC000000000000
  #_ REGISTER_OUT cr 0x0A000000

test_fdiv_37_GEN:
  #_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
  #_ REGISTER_IN f2 0x0000000000000000
  fdiv f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
  #_ REGISTER_OUT f2 0x0000000000000000
  #_ REGISTER_OUT f3 0x7FF0000000000000

test_fdiv_37_cr_GEN:
  #_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
  #_ REGISTER_IN f2 0x0000000000000000
  fdiv. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
  #_ REGISTER_OUT f2 0x0000000000000000
  #_ REGISTER_OUT f3 0x7FF0000000000000
  #_ REGISTER_OUT cr 0x08000000

test_fdiv_38_GEN:
  #_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
  #_ REGISTER_IN f2 0x8000000000000000
  fdiv f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
  #_ REGISTER_OUT f2 0x8000000000000000
  #_ REGISTER_OUT f3 0xFFF0000000000000

test_fdiv_38_cr_GEN:
  #_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
  #_ REGISTER_IN f2 0x8000000000000000
  fdiv. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
  #_ REGISTER_OUT f2 0x8000000000000000
  #_ REGISTER_OUT f3 0xFFF0000000000000
  #_ REGISTER_OUT cr 0x08000000

test_fdiv_39_GEN:
  #_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
  #_ REGISTER_IN f2 0x0000000000000001
  fdiv f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
  #_ REGISTER_OUT f2 0x0000000000000001
  #_ REGISTER_OUT f3 0x432FFFFFFFFFFFFE

test_fdiv_39_cr_GEN:
  #_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
  #_ REGISTER_IN f2 0x0000000000000001
  fdiv. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
  #_ REGISTER_OUT f2 0x0000000000000001
  #_ REGISTER_OUT f3 0x432FFFFFFFFFFFFE
  #_ REGISTER_OUT cr 0x00000000

test_fdiv_40_GEN:
  #_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
  #_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
  fdiv f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
  #_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
  #_ REGISTER_OUT f3 0x3FF0000000000000

test_fdiv_40_cr_GEN:
  #_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
  #_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
  fdiv. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
  #_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
  #_ REGISTER_OUT f3 0x3FF0000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fdiv_41_GEN:
  #_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
  #_ REGISTER_IN f2 0x3FF0000000000000
  fdiv f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
  #_ REGISTER_OUT f2 0x3FF0000000000000
  #_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF

test_fdiv_41_cr_GEN:
  #_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
  #_ REGISTER_IN f2 0x3FF0000000000000
  fdiv. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
  #_ REGISTER_OUT f2 0x3FF0000000000000
  #_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
  #_ REGISTER_OUT cr 0x00000000

test_fdiv_42_GEN:
  #_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
  #_ REGISTER_IN f2 0xBFF0000000000000
  fdiv f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
  #_ REGISTER_OUT f2 0xBFF0000000000000
  #_ REGISTER_OUT f3 0x800FFFFFFFFFFFFF

test_fdiv_42_cr_GEN:
  #_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
  #_ REGISTER_IN f2 0xBFF0000000000000
  fdiv. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
  #_ REGISTER_OUT f2 0xBFF0000000000000
  #_ REGISTER_OUT f3 0x800FFFFFFFFFFFFF
  #_ REGISTER_OUT cr 0x00000000

test_fdiv_43_GEN:
  #_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
  #_ REGISTER_IN f2 0xC1E0000000000000
  fdiv f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
  #_ REGISTER_OUT f2 0xC1E0000000000000
  #_ REGISTER_OUT f3 0x8000000000200000

test_fdiv_43_cr_GEN:
  #_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
  #_ REGISTER_IN f2 0xC1E0000000000000
  fdiv. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
  #_ REGISTER_OUT f2 0xC1E0000000000000
  #_ REGISTER_OUT f3 0x8000000000200000
  #_ REGISTER_OUT cr 0x08000000

test_fdiv_44_GEN:
  #_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
  #_ REGISTER_IN f2 0x41DFFFFFFFC00000
  fdiv f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
  #_ REGISTER_OUT f2 0x41DFFFFFFFC00000
  #_ REGISTER_OUT f3 0x0000000000200000

test_fdiv_44_cr_GEN:
  #_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
  #_ REGISTER_IN f2 0x41DFFFFFFFC00000
  fdiv. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
  #_ REGISTER_OUT f2 0x41DFFFFFFFC00000
  #_ REGISTER_OUT f3 0x0000000000200000
  #_ REGISTER_OUT cr 0x08000000

test_fdiv_45_GEN:
  #_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
  #_ REGISTER_IN f2 0x7FF0000000000000
  fdiv f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
  #_ REGISTER_OUT f2 0x7FF0000000000000
  #_ REGISTER_OUT f3 0x0000000000000000

test_fdiv_45_cr_GEN:
  #_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
  #_ REGISTER_IN f2 0x7FF0000000000000
  fdiv. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
  #_ REGISTER_OUT f2 0x7FF0000000000000
  #_ REGISTER_OUT f3 0x0000000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fdiv_46_GEN:
  #_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
  #_ REGISTER_IN f2 0xFFF0000000000000
  fdiv f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
  #_ REGISTER_OUT f2 0xFFF0000000000000
  #_ REGISTER_OUT f3 0x8000000000000000

test_fdiv_46_cr_GEN:
  #_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
  #_ REGISTER_IN f2 0xFFF0000000000000
  fdiv. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
  #_ REGISTER_OUT f2 0xFFF0000000000000
  #_ REGISTER_OUT f3 0x8000000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fdiv_47_GEN:
  #_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
  #_ REGISTER_IN f2 0xFFF8000000000000
  fdiv f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
  #_ REGISTER_OUT f2 0xFFF8000000000000
  #_ REGISTER_OUT f3 0xFFF8000000000000

test_fdiv_47_cr_GEN:
  #_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
  #_ REGISTER_IN f2 0xFFF8000000000000
  fdiv. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
  #_ REGISTER_OUT f2 0xFFF8000000000000
  #_ REGISTER_OUT f3 0xFFF8000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fdiv_48_GEN:
  #_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
  #_ REGISTER_IN f2 0xFFF4000000000000
  fdiv f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
  #_ REGISTER_OUT f2 0xFFF4000000000000
  #_ REGISTER_OUT f3 0xFFFC000000000000

test_fdiv_48_cr_GEN:
  #_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
  #_ REGISTER_IN f2 0xFFF4000000000000
  fdiv. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
  #_ REGISTER_OUT f2 0xFFF4000000000000
  #_ REGISTER_OUT f3 0xFFFC000000000000
  #_ REGISTER_OUT cr 0x0A000000

test_fdiv_49_GEN:
  #_ REGISTER_IN f1 0x3FF0000000000000
  #_ REGISTER_IN f2 0x0000000000000000
  fdiv f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x3FF0000000000000
  #_ REGISTER_OUT f2 0x0000000000000000
  #_ REGISTER_OUT f3 0x7FF0000000000000

test_fdiv_49_cr_GEN:
  #_ REGISTER_IN f1 0x3FF0000000000000
  #_ REGISTER_IN f2 0x0000000000000000
  fdiv. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x3FF0000000000000
  #_ REGISTER_OUT f2 0x0000000000000000
  #_ REGISTER_OUT f3 0x7FF0000000000000
  #_ REGISTER_OUT cr 0x08000000

test_fdiv_50_GEN:
  #_ REGISTER_IN f1 0x3FF0000000000000
  #_ REGISTER_IN f2 0x8000000000000000
  fdiv f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x3FF0000000000000
  #_ REGISTER_OUT f2 0x8000000000000000
  #_ REGISTER_OUT f3 0xFFF0000000000000

test_fdiv_50_cr_GEN:
  #_ REGISTER_IN f1 0x3FF0000000000000
  #_ REGISTER_IN f2 0x8000000000000000
  fdiv. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x3FF0000000000000
  #_ REGISTER_OUT f2 0x8000000000000000
  #_ REGISTER_OUT f3 0xFFF0000000000000
  #_ REGISTER_OUT cr 0x08000000

test_fdiv_51_GEN:
  #_ REGISTER_IN f1 0x3FF0000000000000
  #_ REGISTER_IN f2 0x0000000000000001
  fdiv f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x3FF0000000000000
  #_ REGISTER_OUT f2 0x0000000000000001
  #_ REGISTER_OUT f3 0x7FF0000000000000

test_fdiv_51_cr_GEN:
  #_ REGISTER_IN f1 0x3FF0000000000000
  #_ REGISTER_IN f2 0x0000000000000001
  fdiv. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x3FF0000000000000
  #_ REGISTER_OUT f2 0x0000000000000001
  #_ REGISTER_OUT f3 0x7FF0000000000000
  #_ REGISTER_OUT cr 0x09000000

test_fdiv_52_GEN:
  #_ REGISTER_IN f1 0x3FF0000000000000
  #_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
  fdiv f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x3FF0000000000000
  #_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
  #_ REGISTER_OUT f3 0x7FD0000000000001

test_fdiv_52_cr_GEN:
  #_ REGISTER_IN f1 0x3FF0000000000000
  #_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
  fdiv. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x3FF0000000000000
  #_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
  #_ REGISTER_OUT f3 0x7FD0000000000001
  #_ REGISTER_OUT cr 0x08000000

test_fdiv_53_GEN:
  #_ REGISTER_IN f1 0x3FF0000000000000
  #_ REGISTER_IN f2 0x3FF0000000000000
  fdiv f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x3FF0000000000000
  #_ REGISTER_OUT f2 0x3FF0000000000000
  #_ REGISTER_OUT f3 0x3FF0000000000000

test_fdiv_53_cr_GEN:
  #_ REGISTER_IN f1 0x3FF0000000000000
  #_ REGISTER_IN f2 0x3FF0000000000000
  fdiv. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x3FF0000000000000
  #_ REGISTER_OUT f2 0x3FF0000000000000
  #_ REGISTER_OUT f3 0x3FF0000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fdiv_54_GEN:
  #_ REGISTER_IN f1 0x3FF0000000000000
  #_ REGISTER_IN f2 0xBFF0000000000000
  fdiv f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x3FF0000000000000
  #_ REGISTER_OUT f2 0xBFF0000000000000
  #_ REGISTER_OUT f3 0xBFF0000000000000

test_fdiv_54_cr_GEN:
  #_ REGISTER_IN f1 0x3FF0000000000000
  #_ REGISTER_IN f2 0xBFF0000000000000
  fdiv. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x3FF0000000000000
  #_ REGISTER_OUT f2 0xBFF0000000000000
  #_ REGISTER_OUT f3 0xBFF0000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fdiv_55_GEN:
  #_ REGISTER_IN f1 0x3FF0000000000000
  #_ REGISTER_IN f2 0xC1E0000000000000
  fdiv f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x3FF0000000000000
  #_ REGISTER_OUT f2 0xC1E0000000000000
  #_ REGISTER_OUT f3 0xBE00000000000000

test_fdiv_55_cr_GEN:
  #_ REGISTER_IN f1 0x3FF0000000000000
  #_ REGISTER_IN f2 0xC1E0000000000000
  fdiv. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x3FF0000000000000
  #_ REGISTER_OUT f2 0xC1E0000000000000
  #_ REGISTER_OUT f3 0xBE00000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fdiv_56_GEN:
  #_ REGISTER_IN f1 0x3FF0000000000000
  #_ REGISTER_IN f2 0x41DFFFFFFFC00000
  fdiv f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x3FF0000000000000
  #_ REGISTER_OUT f2 0x41DFFFFFFFC00000
  #_ REGISTER_OUT f3 0x3E00000000200000

test_fdiv_56_cr_GEN:
  #_ REGISTER_IN f1 0x3FF0000000000000
  #_ REGISTER_IN f2 0x41DFFFFFFFC00000
  fdiv. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x3FF0000000000000
  #_ REGISTER_OUT f2 0x41DFFFFFFFC00000
  #_ REGISTER_OUT f3 0x3E00000000200000
  #_ REGISTER_OUT cr 0x08000000

test_fdiv_57_GEN:
  #_ REGISTER_IN f1 0x3FF0000000000000
  #_ REGISTER_IN f2 0x7FF0000000000000
  fdiv f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x3FF0000000000000
  #_ REGISTER_OUT f2 0x7FF0000000000000
  #_ REGISTER_OUT f3 0x0000000000000000

test_fdiv_57_cr_GEN:
  #_ REGISTER_IN f1 0x3FF0000000000000
  #_ REGISTER_IN f2 0x7FF0000000000000
  fdiv. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x3FF0000000000000
  #_ REGISTER_OUT f2 0x7FF0000000000000
  #_ REGISTER_OUT f3 0x0000000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fdiv_58_GEN:
  #_ REGISTER_IN f1 0x3FF0000000000000
  #_ REGISTER_IN f2 0xFFF0000000000000
  fdiv f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x3FF0000000000000
  #_ REGISTER_OUT f2 0xFFF0000000000000
  #_ REGISTER_OUT f3 0x8000000000000000

test_fdiv_58_cr_GEN:
  #_ REGISTER_IN f1 0x3FF0000000000000
  #_ REGISTER_IN f2 0xFFF0000000000000
  fdiv. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x3FF0000000000000
  #_ REGISTER_OUT f2 0xFFF0000000000000
  #_ REGISTER_OUT f3 0x8000000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fdiv_59_GEN:
  #_ REGISTER_IN f1 0x3FF0000000000000
  #_ REGISTER_IN f2 0xFFF8000000000000
  fdiv f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x3FF0000000000000
  #_ REGISTER_OUT f2 0xFFF8000000000000
  #_ REGISTER_OUT f3 0xFFF8000000000000

test_fdiv_59_cr_GEN:
  #_ REGISTER_IN f1 0x3FF0000000000000
  #_ REGISTER_IN f2 0xFFF8000000000000
  fdiv. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x3FF0000000000000
  #_ REGISTER_OUT f2 0xFFF8000000000000
  #_ REGISTER_OUT f3 0xFFF8000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fdiv_60_GEN:
  #_ REGISTER_IN f1 0x3FF0000000000000
  #_ REGISTER_IN f2 0xFFF4000000000000
  fdiv f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x3FF0000000000000
  #_ REGISTER_OUT f2 0xFFF4000000000000
  #_ REGISTER_OUT f3 0xFFFC000000000000

test_fdiv_60_cr_GEN:
  #_ REGISTER_IN f1 0x3FF0000000000000
  #_ REGISTER_IN f2 0xFFF4000000000000
  fdiv. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x3FF0000000000000
  #_ REGISTER_OUT f2 0xFFF4000000000000
  #_ REGISTER_OUT f3 0xFFFC000000000000
  #_ REGISTER_OUT cr 0x0A000000

test_fdiv_61_GEN:
  #_ REGISTER_IN f1 0xBFF0000000000000
  #_ REGISTER_IN f2 0x0000000000000000
  fdiv f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xBFF0000000000000
  #_ REGISTER_OUT f2 0x0000000000000000
  #_ REGISTER_OUT f3 0xFFF0000000000000

test_fdiv_61_cr_GEN:
  #_ REGISTER_IN f1 0xBFF0000000000000
  #_ REGISTER_IN f2 0x0000000000000000
  fdiv. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xBFF0000000000000
  #_ REGISTER_OUT f2 0x0000000000000000
  #_ REGISTER_OUT f3 0xFFF0000000000000
  #_ REGISTER_OUT cr 0x08000000

test_fdiv_62_GEN:
  #_ REGISTER_IN f1 0xBFF0000000000000
  #_ REGISTER_IN f2 0x8000000000000000
  fdiv f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xBFF0000000000000
  #_ REGISTER_OUT f2 0x8000000000000000
  #_ REGISTER_OUT f3 0x7FF0000000000000

test_fdiv_62_cr_GEN:
  #_ REGISTER_IN f1 0xBFF0000000000000
  #_ REGISTER_IN f2 0x8000000000000000
  fdiv. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xBFF0000000000000
  #_ REGISTER_OUT f2 0x8000000000000000
  #_ REGISTER_OUT f3 0x7FF0000000000000
  #_ REGISTER_OUT cr 0x08000000

test_fdiv_63_GEN:
  #_ REGISTER_IN f1 0xBFF0000000000000
  #_ REGISTER_IN f2 0x0000000000000001
  fdiv f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xBFF0000000000000
  #_ REGISTER_OUT f2 0x0000000000000001
  #_ REGISTER_OUT f3 0xFFF0000000000000

test_fdiv_63_cr_GEN:
  #_ REGISTER_IN f1 0xBFF0000000000000
  #_ REGISTER_IN f2 0x0000000000000001
  fdiv. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xBFF0000000000000
  #_ REGISTER_OUT f2 0x0000000000000001
  #_ REGISTER_OUT f3 0xFFF0000000000000
  #_ REGISTER_OUT cr 0x09000000

test_fdiv_64_GEN:
  #_ REGISTER_IN f1 0xBFF0000000000000
  #_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
  fdiv f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xBFF0000000000000
  #_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
  #_ REGISTER_OUT f3 0xFFD0000000000001

test_fdiv_64_cr_GEN:
  #_ REGISTER_IN f1 0xBFF0000000000000
  #_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
  fdiv. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xBFF0000000000000
  #_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
  #_ REGISTER_OUT f3 0xFFD0000000000001
  #_ REGISTER_OUT cr 0x08000000

test_fdiv_65_GEN:
  #_ REGISTER_IN f1 0xBFF0000000000000
  #_ REGISTER_IN f2 0x3FF0000000000000
  fdiv f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xBFF0000000000000
  #_ REGISTER_OUT f2 0x3FF0000000000000
  #_ REGISTER_OUT f3 0xBFF0000000000000

test_fdiv_65_cr_GEN:
  #_ REGISTER_IN f1 0xBFF0000000000000
  #_ REGISTER_IN f2 0x3FF0000000000000
  fdiv. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xBFF0000000000000
  #_ REGISTER_OUT f2 0x3FF0000000000000
  #_ REGISTER_OUT f3 0xBFF0000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fdiv_66_GEN:
  #_ REGISTER_IN f1 0xBFF0000000000000
  #_ REGISTER_IN f2 0xBFF0000000000000
  fdiv f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xBFF0000000000000
  #_ REGISTER_OUT f2 0xBFF0000000000000
  #_ REGISTER_OUT f3 0x3FF0000000000000

test_fdiv_66_cr_GEN:
  #_ REGISTER_IN f1 0xBFF0000000000000
  #_ REGISTER_IN f2 0xBFF0000000000000
  fdiv. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xBFF0000000000000
  #_ REGISTER_OUT f2 0xBFF0000000000000
  #_ REGISTER_OUT f3 0x3FF0000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fdiv_67_GEN:
  #_ REGISTER_IN f1 0xBFF0000000000000
  #_ REGISTER_IN f2 0xC1E0000000000000
  fdiv f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xBFF0000000000000
  #_ REGISTER_OUT f2 0xC1E0000000000000
  #_ REGISTER_OUT f3 0x3E00000000000000

test_fdiv_67_cr_GEN:
  #_ REGISTER_IN f1 0xBFF0000000000000
  #_ REGISTER_IN f2 0xC1E0000000000000
  fdiv. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xBFF0000000000000
  #_ REGISTER_OUT f2 0xC1E0000000000000
  #_ REGISTER_OUT f3 0x3E00000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fdiv_68_GEN:
  #_ REGISTER_IN f1 0xBFF0000000000000
  #_ REGISTER_IN f2 0x41DFFFFFFFC00000
  fdiv f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xBFF0000000000000
  #_ REGISTER_OUT f2 0x41DFFFFFFFC00000
  #_ REGISTER_OUT f3 0xBE00000000200000

test_fdiv_68_cr_GEN:
  #_ REGISTER_IN f1 0xBFF0000000000000
  #_ REGISTER_IN f2 0x41DFFFFFFFC00000
  fdiv. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xBFF0000000000000
  #_ REGISTER_OUT f2 0x41DFFFFFFFC00000
  #_ REGISTER_OUT f3 0xBE00000000200000
  #_ REGISTER_OUT cr 0x08000000

test_fdiv_69_GEN:
  #_ REGISTER_IN f1 0xBFF0000000000000
  #_ REGISTER_IN f2 0x7FF0000000000000
  fdiv f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xBFF0000000000000
  #_ REGISTER_OUT f2 0x7FF0000000000000
  #_ REGISTER_OUT f3 0x8000000000000000

test_fdiv_69_cr_GEN:
  #_ REGISTER_IN f1 0xBFF0000000000000
  #_ REGISTER_IN f2 0x7FF0000000000000
  fdiv. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xBFF0000000000000
  #_ REGISTER_OUT f2 0x7FF0000000000000
  #_ REGISTER_OUT f3 0x8000000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fdiv_70_GEN:
  #_ REGISTER_IN f1 0xBFF0000000000000
  #_ REGISTER_IN f2 0xFFF0000000000000
  fdiv f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xBFF0000000000000
  #_ REGISTER_OUT f2 0xFFF0000000000000
  #_ REGISTER_OUT f3 0x0000000000000000

test_fdiv_70_cr_GEN:
  #_ REGISTER_IN f1 0xBFF0000000000000
  #_ REGISTER_IN f2 0xFFF0000000000000
  fdiv. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xBFF0000000000000
  #_ REGISTER_OUT f2 0xFFF0000000000000
  #_ REGISTER_OUT f3 0x0000000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fdiv_71_GEN:
  #_ REGISTER_IN f1 0xBFF0000000000000
  #_ REGISTER_IN f2 0xFFF8000000000000
  fdiv f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xBFF0000000000000
  #_ REGISTER_OUT f2 0xFFF8000000000000
  #_ REGISTER_OUT f3 0xFFF8000000000000

test_fdiv_71_cr_GEN:
  #_ REGISTER_IN f1 0xBFF0000000000000
  #_ REGISTER_IN f2 0xFFF8000000000000
  fdiv. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xBFF0000000000000
  #_ REGISTER_OUT f2 0xFFF8000000000000
  #_ REGISTER_OUT f3 0xFFF8000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fdiv_72_GEN:
  #_ REGISTER_IN f1 0xBFF0000000000000
  #_ REGISTER_IN f2 0xFFF4000000000000
  fdiv f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xBFF0000000000000
  #_ REGISTER_OUT f2 0xFFF4000000000000
  #_ REGISTER_OUT f3 0xFFFC000000000000

test_fdiv_72_cr_GEN:
  #_ REGISTER_IN f1 0xBFF0000000000000
  #_ REGISTER_IN f2 0xFFF4000000000000
  fdiv. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xBFF0000000000000
  #_ REGISTER_OUT f2 0xFFF4000000000000
  #_ REGISTER_OUT f3 0xFFFC000000000000
  #_ REGISTER_OUT cr 0x0A000000

test_fdiv_73_GEN:
  #_ REGISTER_IN f1 0xC1E0000000000000
  #_ REGISTER_IN f2 0x0000000000000000
  fdiv f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xC1E0000000000000
  #_ REGISTER_OUT f2 0x0000000000000000
  #_ REGISTER_OUT f3 0xFFF0000000000000

test_fdiv_73_cr_GEN:
  #_ REGISTER_IN f1 0xC1E0000000000000
  #_ REGISTER_IN f2 0x0000000000000000
  fdiv. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xC1E0000000000000
  #_ REGISTER_OUT f2 0x0000000000000000
  #_ REGISTER_OUT f3 0xFFF0000000000000
  #_ REGISTER_OUT cr 0x08000000

test_fdiv_74_GEN:
  #_ REGISTER_IN f1 0xC1E0000000000000
  #_ REGISTER_IN f2 0x8000000000000000
  fdiv f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xC1E0000000000000
  #_ REGISTER_OUT f2 0x8000000000000000
  #_ REGISTER_OUT f3 0x7FF0000000000000

test_fdiv_74_cr_GEN:
  #_ REGISTER_IN f1 0xC1E0000000000000
  #_ REGISTER_IN f2 0x8000000000000000
  fdiv. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xC1E0000000000000
  #_ REGISTER_OUT f2 0x8000000000000000
  #_ REGISTER_OUT f3 0x7FF0000000000000
  #_ REGISTER_OUT cr 0x08000000

test_fdiv_75_GEN:
  #_ REGISTER_IN f1 0xC1E0000000000000
  #_ REGISTER_IN f2 0x0000000000000001
  fdiv f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xC1E0000000000000
  #_ REGISTER_OUT f2 0x0000000000000001
  #_ REGISTER_OUT f3 0xFFF0000000000000

test_fdiv_75_cr_GEN:
  #_ REGISTER_IN f1 0xC1E0000000000000
  #_ REGISTER_IN f2 0x0000000000000001
  fdiv. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xC1E0000000000000
  #_ REGISTER_OUT f2 0x0000000000000001
  #_ REGISTER_OUT f3 0xFFF0000000000000
  #_ REGISTER_OUT cr 0x09000000

test_fdiv_76_GEN:
  #_ REGISTER_IN f1 0xC1E0000000000000
  #_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
  fdiv f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xC1E0000000000000
  #_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
  #_ REGISTER_OUT f3 0xFFF0000000000000

test_fdiv_76_cr_GEN:
  #_ REGISTER_IN f1 0xC1E0000000000000
  #_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
  fdiv. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xC1E0000000000000
  #_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
  #_ REGISTER_OUT f3 0xFFF0000000000000
  #_ REGISTER_OUT cr 0x09000000

test_fdiv_77_GEN:
  #_ REGISTER_IN f1 0xC1E0000000000000
  #_ REGISTER_IN f2 0x3FF0000000000000
  fdiv f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xC1E0000000000000
  #_ REGISTER_OUT f2 0x3FF0000000000000
  #_ REGISTER_OUT f3 0xC1E0000000000000

test_fdiv_77_cr_GEN:
  #_ REGISTER_IN f1 0xC1E0000000000000
  #_ REGISTER_IN f2 0x3FF0000000000000
  fdiv. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xC1E0000000000000
  #_ REGISTER_OUT f2 0x3FF0000000000000
  #_ REGISTER_OUT f3 0xC1E0000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fdiv_78_GEN:
  #_ REGISTER_IN f1 0xC1E0000000000000
  #_ REGISTER_IN f2 0xBFF0000000000000
  fdiv f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xC1E0000000000000
  #_ REGISTER_OUT f2 0xBFF0000000000000
  #_ REGISTER_OUT f3 0x41E0000000000000

test_fdiv_78_cr_GEN:
  #_ REGISTER_IN f1 0xC1E0000000000000
  #_ REGISTER_IN f2 0xBFF0000000000000
  fdiv. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xC1E0000000000000
  #_ REGISTER_OUT f2 0xBFF0000000000000
  #_ REGISTER_OUT f3 0x41E0000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fdiv_79_GEN:
  #_ REGISTER_IN f1 0xC1E0000000000000
  #_ REGISTER_IN f2 0xC1E0000000000000
  fdiv f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xC1E0000000000000
  #_ REGISTER_OUT f2 0xC1E0000000000000
  #_ REGISTER_OUT f3 0x3FF0000000000000

test_fdiv_79_cr_GEN:
  #_ REGISTER_IN f1 0xC1E0000000000000
  #_ REGISTER_IN f2 0xC1E0000000000000
  fdiv. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xC1E0000000000000
  #_ REGISTER_OUT f2 0xC1E0000000000000
  #_ REGISTER_OUT f3 0x3FF0000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fdiv_80_GEN:
  #_ REGISTER_IN f1 0xC1E0000000000000
  #_ REGISTER_IN f2 0x41DFFFFFFFC00000
  fdiv f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xC1E0000000000000
  #_ REGISTER_OUT f2 0x41DFFFFFFFC00000
  #_ REGISTER_OUT f3 0xBFF0000000200000

test_fdiv_80_cr_GEN:
  #_ REGISTER_IN f1 0xC1E0000000000000
  #_ REGISTER_IN f2 0x41DFFFFFFFC00000
  fdiv. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xC1E0000000000000
  #_ REGISTER_OUT f2 0x41DFFFFFFFC00000
  #_ REGISTER_OUT f3 0xBFF0000000200000
  #_ REGISTER_OUT cr 0x08000000

test_fdiv_81_GEN:
  #_ REGISTER_IN f1 0xC1E0000000000000
  #_ REGISTER_IN f2 0x7FF0000000000000
  fdiv f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xC1E0000000000000
  #_ REGISTER_OUT f2 0x7FF0000000000000
  #_ REGISTER_OUT f3 0x8000000000000000

test_fdiv_81_cr_GEN:
  #_ REGISTER_IN f1 0xC1E0000000000000
  #_ REGISTER_IN f2 0x7FF0000000000000
  fdiv. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xC1E0000000000000
  #_ REGISTER_OUT f2 0x7FF0000000000000
  #_ REGISTER_OUT f3 0x8000000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fdiv_82_GEN:
  #_ REGISTER_IN f1 0xC1E0000000000000
  #_ REGISTER_IN f2 0xFFF0000000000000
  fdiv f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xC1E0000000000000
  #_ REGISTER_OUT f2 0xFFF0000000000000
  #_ REGISTER_OUT f3 0x0000000000000000

test_fdiv_82_cr_GEN:
  #_ REGISTER_IN f1 0xC1E0000000000000
  #_ REGISTER_IN f2 0xFFF0000000000000
  fdiv. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xC1E0000000000000
  #_ REGISTER_OUT f2 0xFFF0000000000000
  #_ REGISTER_OUT f3 0x0000000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fdiv_83_GEN:
  #_ REGISTER_IN f1 0xC1E0000000000000
  #_ REGISTER_IN f2 0xFFF8000000000000
  fdiv f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xC1E0000000000000
  #_ REGISTER_OUT f2 0xFFF8000000000000
  #_ REGISTER_OUT f3 0xFFF8000000000000

test_fdiv_83_cr_GEN:
  #_ REGISTER_IN f1 0xC1E0000000000000
  #_ REGISTER_IN f2 0xFFF8000000000000
  fdiv. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xC1E0000000000000
  #_ REGISTER_OUT f2 0xFFF8000000000000
  #_ REGISTER_OUT f3 0xFFF8000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fdiv_84_GEN:
  #_ REGISTER_IN f1 0xC1E0000000000000
  #_ REGISTER_IN f2 0xFFF4000000000000
  fdiv f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xC1E0000000000000
  #_ REGISTER_OUT f2 0xFFF4000000000000
  #_ REGISTER_OUT f3 0xFFFC000000000000

test_fdiv_84_cr_GEN:
  #_ REGISTER_IN f1 0xC1E0000000000000
  #_ REGISTER_IN f2 0xFFF4000000000000
  fdiv. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xC1E0000000000000
  #_ REGISTER_OUT f2 0xFFF4000000000000
  #_ REGISTER_OUT f3 0xFFFC000000000000
  #_ REGISTER_OUT cr 0x0A000000

test_fdiv_85_GEN:
  #_ REGISTER_IN f1 0x41DFFFFFFFC00000
  #_ REGISTER_IN f2 0x0000000000000000
  fdiv f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x41DFFFFFFFC00000
  #_ REGISTER_OUT f2 0x0000000000000000
  #_ REGISTER_OUT f3 0x7FF0000000000000

test_fdiv_85_cr_GEN:
  #_ REGISTER_IN f1 0x41DFFFFFFFC00000
  #_ REGISTER_IN f2 0x0000000000000000
  fdiv. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x41DFFFFFFFC00000
  #_ REGISTER_OUT f2 0x0000000000000000
  #_ REGISTER_OUT f3 0x7FF0000000000000
  #_ REGISTER_OUT cr 0x08000000

test_fdiv_86_GEN:
  #_ REGISTER_IN f1 0x41DFFFFFFFC00000
  #_ REGISTER_IN f2 0x8000000000000000
  fdiv f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x41DFFFFFFFC00000
  #_ REGISTER_OUT f2 0x8000000000000000
  #_ REGISTER_OUT f3 0xFFF0000000000000

test_fdiv_86_cr_GEN:
  #_ REGISTER_IN f1 0x41DFFFFFFFC00000
  #_ REGISTER_IN f2 0x8000000000000000
  fdiv. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x41DFFFFFFFC00000
  #_ REGISTER_OUT f2 0x8000000000000000
  #_ REGISTER_OUT f3 0xFFF0000000000000
  #_ REGISTER_OUT cr 0x08000000

test_fdiv_87_GEN:
  #_ REGISTER_IN f1 0x41DFFFFFFFC00000
  #_ REGISTER_IN f2 0x0000000000000001
  fdiv f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x41DFFFFFFFC00000
  #_ REGISTER_OUT f2 0x0000000000000001
  #_ REGISTER_OUT f3 0x7FF0000000000000

test_fdiv_87_cr_GEN:
  #_ REGISTER_IN f1 0x41DFFFFFFFC00000
  #_ REGISTER_IN f2 0x0000000000000001
  fdiv. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x41DFFFFFFFC00000
  #_ REGISTER_OUT f2 0x0000000000000001
  #_ REGISTER_OUT f3 0x7FF0000000000000
  #_ REGISTER_OUT cr 0x09000000

test_fdiv_88_GEN:
  #_ REGISTER_IN f1 0x41DFFFFFFFC00000
  #_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
  fdiv f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x41DFFFFFFFC00000
  #_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
  #_ REGISTER_OUT f3 0x7FF0000000000000

test_fdiv_88_cr_GEN:
  #_ REGISTER_IN f1 0x41DFFFFFFFC00000
  #_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
  fdiv. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x41DFFFFFFFC00000
  #_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
  #_ REGISTER_OUT f3 0x7FF0000000000000
  #_ REGISTER_OUT cr 0x09000000

test_fdiv_89_GEN:
  #_ REGISTER_IN f1 0x41DFFFFFFFC00000
  #_ REGISTER_IN f2 0x3FF0000000000000
  fdiv f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x41DFFFFFFFC00000
  #_ REGISTER_OUT f2 0x3FF0000000000000
  #_ REGISTER_OUT f3 0x41DFFFFFFFC00000

test_fdiv_89_cr_GEN:
  #_ REGISTER_IN f1 0x41DFFFFFFFC00000
  #_ REGISTER_IN f2 0x3FF0000000000000
  fdiv. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x41DFFFFFFFC00000
  #_ REGISTER_OUT f2 0x3FF0000000000000
  #_ REGISTER_OUT f3 0x41DFFFFFFFC00000
  #_ REGISTER_OUT cr 0x00000000

test_fdiv_90_GEN:
  #_ REGISTER_IN f1 0x41DFFFFFFFC00000
  #_ REGISTER_IN f2 0xBFF0000000000000
  fdiv f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x41DFFFFFFFC00000
  #_ REGISTER_OUT f2 0xBFF0000000000000
  #_ REGISTER_OUT f3 0xC1DFFFFFFFC00000

test_fdiv_90_cr_GEN:
  #_ REGISTER_IN f1 0x41DFFFFFFFC00000
  #_ REGISTER_IN f2 0xBFF0000000000000
  fdiv. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x41DFFFFFFFC00000
  #_ REGISTER_OUT f2 0xBFF0000000000000
  #_ REGISTER_OUT f3 0xC1DFFFFFFFC00000
  #_ REGISTER_OUT cr 0x00000000

test_fdiv_91_GEN:
  #_ REGISTER_IN f1 0x41DFFFFFFFC00000
  #_ REGISTER_IN f2 0xC1E0000000000000
  fdiv f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x41DFFFFFFFC00000
  #_ REGISTER_OUT f2 0xC1E0000000000000
  #_ REGISTER_OUT f3 0xBFEFFFFFFFC00000

test_fdiv_91_cr_GEN:
  #_ REGISTER_IN f1 0x41DFFFFFFFC00000
  #_ REGISTER_IN f2 0xC1E0000000000000
  fdiv. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x41DFFFFFFFC00000
  #_ REGISTER_OUT f2 0xC1E0000000000000
  #_ REGISTER_OUT f3 0xBFEFFFFFFFC00000
  #_ REGISTER_OUT cr 0x00000000

test_fdiv_92_GEN:
  #_ REGISTER_IN f1 0x41DFFFFFFFC00000
  #_ REGISTER_IN f2 0x41DFFFFFFFC00000
  fdiv f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x41DFFFFFFFC00000
  #_ REGISTER_OUT f2 0x41DFFFFFFFC00000
  #_ REGISTER_OUT f3 0x3FF0000000000000

test_fdiv_92_cr_GEN:
  #_ REGISTER_IN f1 0x41DFFFFFFFC00000
  #_ REGISTER_IN f2 0x41DFFFFFFFC00000
  fdiv. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x41DFFFFFFFC00000
  #_ REGISTER_OUT f2 0x41DFFFFFFFC00000
  #_ REGISTER_OUT f3 0x3FF0000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fdiv_93_GEN:
  #_ REGISTER_IN f1 0x41DFFFFFFFC00000
  #_ REGISTER_IN f2 0x7FF0000000000000
  fdiv f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x41DFFFFFFFC00000
  #_ REGISTER_OUT f2 0x7FF0000000000000
  #_ REGISTER_OUT f3 0x0000000000000000

test_fdiv_93_cr_GEN:
  #_ REGISTER_IN f1 0x41DFFFFFFFC00000
  #_ REGISTER_IN f2 0x7FF0000000000000
  fdiv. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x41DFFFFFFFC00000
  #_ REGISTER_OUT f2 0x7FF0000000000000
  #_ REGISTER_OUT f3 0x0000000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fdiv_94_GEN:
  #_ REGISTER_IN f1 0x41DFFFFFFFC00000
  #_ REGISTER_IN f2 0xFFF0000000000000
  fdiv f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x41DFFFFFFFC00000
  #_ REGISTER_OUT f2 0xFFF0000000000000
  #_ REGISTER_OUT f3 0x8000000000000000

test_fdiv_94_cr_GEN:
  #_ REGISTER_IN f1 0x41DFFFFFFFC00000
  #_ REGISTER_IN f2 0xFFF0000000000000
  fdiv. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x41DFFFFFFFC00000
  #_ REGISTER_OUT f2 0xFFF0000000000000
  #_ REGISTER_OUT f3 0x8000000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fdiv_95_GEN:
  #_ REGISTER_IN f1 0x41DFFFFFFFC00000
  #_ REGISTER_IN f2 0xFFF8000000000000
  fdiv f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x41DFFFFFFFC00000
  #_ REGISTER_OUT f2 0xFFF8000000000000
  #_ REGISTER_OUT f3 0xFFF8000000000000

test_fdiv_95_cr_GEN:
  #_ REGISTER_IN f1 0x41DFFFFFFFC00000
  #_ REGISTER_IN f2 0xFFF8000000000000
  fdiv. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x41DFFFFFFFC00000
  #_ REGISTER_OUT f2 0xFFF8000000000000
  #_ REGISTER_OUT f3 0xFFF8000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fdiv_96_GEN:
  #_ REGISTER_IN f1 0x41DFFFFFFFC00000
  #_ REGISTER_IN f2 0xFFF4000000000000
  fdiv f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x41DFFFFFFFC00000
  #_ REGISTER_OUT f2 0xFFF4000000000000
  #_ REGISTER_OUT f3 0xFFFC000000000000

test_fdiv_96_cr_GEN:
  #_ REGISTER_IN f1 0x41DFFFFFFFC00000
  #_ REGISTER_IN f2 0xFFF4000000000000
  fdiv. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x41DFFFFFFFC00000
  #_ REGISTER_OUT f2 0xFFF4000000000000
  #_ REGISTER_OUT f3 0xFFFC000000000000
  #_ REGISTER_OUT cr 0x0A000000

test_fdiv_97_GEN:
  #_ REGISTER_IN f1 0x7FF0000000000000
  #_ REGISTER_IN f2 0x0000000000000000
  fdiv f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x7FF0000000000000
  #_ REGISTER_OUT f2 0x0000000000000000
  #_ REGISTER_OUT f3 0x7FF0000000000000

test_fdiv_97_cr_GEN:
  #_ REGISTER_IN f1 0x7FF0000000000000
  #_ REGISTER_IN f2 0x0000000000000000
  fdiv. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x7FF0000000000000
  #_ REGISTER_OUT f2 0x0000000000000000
  #_ REGISTER_OUT f3 0x7FF0000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fdiv_98_GEN:
  #_ REGISTER_IN f1 0x7FF0000000000000
  #_ REGISTER_IN f2 0x8000000000000000
  fdiv f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x7FF0000000000000
  #_ REGISTER_OUT f2 0x8000000000000000
  #_ REGISTER_OUT f3 0xFFF0000000000000

test_fdiv_98_cr_GEN:
  #_ REGISTER_IN f1 0x7FF0000000000000
  #_ REGISTER_IN f2 0x8000000000000000
  fdiv. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x7FF0000000000000
  #_ REGISTER_OUT f2 0x8000000000000000
  #_ REGISTER_OUT f3 0xFFF0000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fdiv_99_GEN:
  #_ REGISTER_IN f1 0x7FF0000000000000
  #_ REGISTER_IN f2 0x0000000000000001
  fdiv f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x7FF0000000000000
  #_ REGISTER_OUT f2 0x0000000000000001
  #_ REGISTER_OUT f3 0x7FF0000000000000

test_fdiv_99_cr_GEN:
  #_ REGISTER_IN f1 0x7FF0000000000000
  #_ REGISTER_IN f2 0x0000000000000001
  fdiv. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x7FF0000000000000
  #_ REGISTER_OUT f2 0x0000000000000001
  #_ REGISTER_OUT f3 0x7FF0000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fdiv_100_GEN:
  #_ REGISTER_IN f1 0x7FF0000000000000
  #_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
  fdiv f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x7FF0000000000000
  #_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
  #_ REGISTER_OUT f3 0x7FF0000000000000

test_fdiv_100_cr_GEN:
  #_ REGISTER_IN f1 0x7FF0000000000000
  #_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
  fdiv. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x7FF0000000000000
  #_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
  #_ REGISTER_OUT f3 0x7FF0000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fdiv_101_GEN:
  #_ REGISTER_IN f1 0x7FF0000000000000
  #_ REGISTER_IN f2 0x3FF0000000000000
  fdiv f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x7FF0000000000000
  #_ REGISTER_OUT f2 0x3FF0000000000000
  #_ REGISTER_OUT f3 0x7FF0000000000000

test_fdiv_101_cr_GEN:
  #_ REGISTER_IN f1 0x7FF0000000000000
  #_ REGISTER_IN f2 0x3FF0000000000000
  fdiv. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x7FF0000000000000
  #_ REGISTER_OUT f2 0x3FF0000000000000
  #_ REGISTER_OUT f3 0x7FF0000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fdiv_102_GEN:
  #_ REGISTER_IN f1 0x7FF0000000000000
  #_ REGISTER_IN f2 0xBFF0000000000000
  fdiv f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x7FF0000000000000
  #_ REGISTER_OUT f2 0xBFF0000000000000
  #_ REGISTER_OUT f3 0xFFF0000000000000

test_fdiv_102_cr_GEN:
  #_ REGISTER_IN f1 0x7FF0000000000000
  #_ REGISTER_IN f2 0xBFF0000000000000
  fdiv. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x7FF0000000000000
  #_ REGISTER_OUT f2 0xBFF0000000000000
  #_ REGISTER_OUT f3 0xFFF0000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fdiv_103_GEN:
  #_ REGISTER_IN f1 0x7FF0000000000000
  #_ REGISTER_IN f2 0xC1E0000000000000
  fdiv f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x7FF0000000000000
  #_ REGISTER_OUT f2 0xC1E0000000000000
  #_ REGISTER_OUT f3 0xFFF0000000000000

test_fdiv_103_cr_GEN:
  #_ REGISTER_IN f1 0x7FF0000000000000
  #_ REGISTER_IN f2 0xC1E0000000000000
  fdiv. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x7FF0000000000000
  #_ REGISTER_OUT f2 0xC1E0000000000000
  #_ REGISTER_OUT f3 0xFFF0000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fdiv_104_GEN:
  #_ REGISTER_IN f1 0x7FF0000000000000
  #_ REGISTER_IN f2 0x41DFFFFFFFC00000
  fdiv f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x7FF0000000000000
  #_ REGISTER_OUT f2 0x41DFFFFFFFC00000
  #_ REGISTER_OUT f3 0x7FF0000000000000

test_fdiv_104_cr_GEN:
  #_ REGISTER_IN f1 0x7FF0000000000000
  #_ REGISTER_IN f2 0x41DFFFFFFFC00000
  fdiv. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x7FF0000000000000
  #_ REGISTER_OUT f2 0x41DFFFFFFFC00000
  #_ REGISTER_OUT f3 0x7FF0000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fdiv_105_GEN:
  #_ REGISTER_IN f1 0x7FF0000000000000
  #_ REGISTER_IN f2 0x7FF0000000000000
  fdiv f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x7FF0000000000000
  #_ REGISTER_OUT f2 0x7FF0000000000000
  #_ REGISTER_OUT f3 0x7FF8000000000000

test_fdiv_105_cr_GEN:
  #_ REGISTER_IN f1 0x7FF0000000000000
  #_ REGISTER_IN f2 0x7FF0000000000000
  fdiv. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x7FF0000000000000
  #_ REGISTER_OUT f2 0x7FF0000000000000
  #_ REGISTER_OUT f3 0x7FF8000000000000
  #_ REGISTER_OUT cr 0x0A000000

test_fdiv_106_GEN:
  #_ REGISTER_IN f1 0x7FF0000000000000
  #_ REGISTER_IN f2 0xFFF0000000000000
  fdiv f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x7FF0000000000000
  #_ REGISTER_OUT f2 0xFFF0000000000000
  #_ REGISTER_OUT f3 0x7FF8000000000000

test_fdiv_106_cr_GEN:
  #_ REGISTER_IN f1 0x7FF0000000000000
  #_ REGISTER_IN f2 0xFFF0000000000000
  fdiv. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x7FF0000000000000
  #_ REGISTER_OUT f2 0xFFF0000000000000
  #_ REGISTER_OUT f3 0x7FF8000000000000
  #_ REGISTER_OUT cr 0x0A000000

test_fdiv_107_GEN:
  #_ REGISTER_IN f1 0x7FF0000000000000
  #_ REGISTER_IN f2 0xFFF8000000000000
  fdiv f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x7FF0000000000000
  #_ REGISTER_OUT f2 0xFFF8000000000000
  #_ REGISTER_OUT f3 0xFFF8000000000000

test_fdiv_107_cr_GEN:
  #_ REGISTER_IN f1 0x7FF0000000000000
  #_ REGISTER_IN f2 0xFFF8000000000000
  fdiv. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x7FF0000000000000
  #_ REGISTER_OUT f2 0xFFF8000000000000
  #_ REGISTER_OUT f3 0xFFF8000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fdiv_108_GEN:
  #_ REGISTER_IN f1 0x7FF0000000000000
  #_ REGISTER_IN f2 0xFFF4000000000000
  fdiv f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x7FF0000000000000
  #_ REGISTER_OUT f2 0xFFF4000000000000
  #_ REGISTER_OUT f3 0xFFFC000000000000

test_fdiv_108_cr_GEN:
  #_ REGISTER_IN f1 0x7FF0000000000000
  #_ REGISTER_IN f2 0xFFF4000000000000
  fdiv. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x7FF0000000000000
  #_ REGISTER_OUT f2 0xFFF4000000000000
  #_ REGISTER_OUT f3 0xFFFC000000000000
  #_ REGISTER_OUT cr 0x0A000000

test_fdiv_109_GEN:
  #_ REGISTER_IN f1 0xFFF0000000000000
  #_ REGISTER_IN f2 0x0000000000000000
  fdiv f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF0000000000000
  #_ REGISTER_OUT f2 0x0000000000000000
  #_ REGISTER_OUT f3 0xFFF0000000000000

test_fdiv_109_cr_GEN:
  #_ REGISTER_IN f1 0xFFF0000000000000
  #_ REGISTER_IN f2 0x0000000000000000
  fdiv. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF0000000000000
  #_ REGISTER_OUT f2 0x0000000000000000
  #_ REGISTER_OUT f3 0xFFF0000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fdiv_110_GEN:
  #_ REGISTER_IN f1 0xFFF0000000000000
  #_ REGISTER_IN f2 0x8000000000000000
  fdiv f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF0000000000000
  #_ REGISTER_OUT f2 0x8000000000000000
  #_ REGISTER_OUT f3 0x7FF0000000000000

test_fdiv_110_cr_GEN:
  #_ REGISTER_IN f1 0xFFF0000000000000
  #_ REGISTER_IN f2 0x8000000000000000
  fdiv. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF0000000000000
  #_ REGISTER_OUT f2 0x8000000000000000
  #_ REGISTER_OUT f3 0x7FF0000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fdiv_111_GEN:
  #_ REGISTER_IN f1 0xFFF0000000000000
  #_ REGISTER_IN f2 0x0000000000000001
  fdiv f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF0000000000000
  #_ REGISTER_OUT f2 0x0000000000000001
  #_ REGISTER_OUT f3 0xFFF0000000000000

test_fdiv_111_cr_GEN:
  #_ REGISTER_IN f1 0xFFF0000000000000
  #_ REGISTER_IN f2 0x0000000000000001
  fdiv. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF0000000000000
  #_ REGISTER_OUT f2 0x0000000000000001
  #_ REGISTER_OUT f3 0xFFF0000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fdiv_112_GEN:
  #_ REGISTER_IN f1 0xFFF0000000000000
  #_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
  fdiv f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF0000000000000
  #_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
  #_ REGISTER_OUT f3 0xFFF0000000000000

test_fdiv_112_cr_GEN:
  #_ REGISTER_IN f1 0xFFF0000000000000
  #_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
  fdiv. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF0000000000000
  #_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
  #_ REGISTER_OUT f3 0xFFF0000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fdiv_113_GEN:
  #_ REGISTER_IN f1 0xFFF0000000000000
  #_ REGISTER_IN f2 0x3FF0000000000000
  fdiv f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF0000000000000
  #_ REGISTER_OUT f2 0x3FF0000000000000
  #_ REGISTER_OUT f3 0xFFF0000000000000

test_fdiv_113_cr_GEN:
  #_ REGISTER_IN f1 0xFFF0000000000000
  #_ REGISTER_IN f2 0x3FF0000000000000
  fdiv. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF0000000000000
  #_ REGISTER_OUT f2 0x3FF0000000000000
  #_ REGISTER_OUT f3 0xFFF0000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fdiv_114_GEN:
  #_ REGISTER_IN f1 0xFFF0000000000000
  #_ REGISTER_IN f2 0xBFF0000000000000
  fdiv f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF0000000000000
  #_ REGISTER_OUT f2 0xBFF0000000000000
  #_ REGISTER_OUT f3 0x7FF0000000000000

test_fdiv_114_cr_GEN:
  #_ REGISTER_IN f1 0xFFF0000000000000
  #_ REGISTER_IN f2 0xBFF0000000000000
  fdiv. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF0000000000000
  #_ REGISTER_OUT f2 0xBFF0000000000000
  #_ REGISTER_OUT f3 0x7FF0000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fdiv_115_GEN:
  #_ REGISTER_IN f1 0xFFF0000000000000
  #_ REGISTER_IN f2 0xC1E0000000000000
  fdiv f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF0000000000000
  #_ REGISTER_OUT f2 0xC1E0000000000000
  #_ REGISTER_OUT f3 0x7FF0000000000000

test_fdiv_115_cr_GEN:
  #_ REGISTER_IN f1 0xFFF0000000000000
  #_ REGISTER_IN f2 0xC1E0000000000000
  fdiv. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF0000000000000
  #_ REGISTER_OUT f2 0xC1E0000000000000
  #_ REGISTER_OUT f3 0x7FF0000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fdiv_116_GEN:
  #_ REGISTER_IN f1 0xFFF0000000000000
  #_ REGISTER_IN f2 0x41DFFFFFFFC00000
  fdiv f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF0000000000000
  #_ REGISTER_OUT f2 0x41DFFFFFFFC00000
  #_ REGISTER_OUT f3 0xFFF0000000000000

test_fdiv_116_cr_GEN:
  #_ REGISTER_IN f1 0xFFF0000000000000
  #_ REGISTER_IN f2 0x41DFFFFFFFC00000
  fdiv. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF0000000000000
  #_ REGISTER_OUT f2 0x41DFFFFFFFC00000
  #_ REGISTER_OUT f3 0xFFF0000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fdiv_117_GEN:
  #_ REGISTER_IN f1 0xFFF0000000000000
  #_ REGISTER_IN f2 0x7FF0000000000000
  fdiv f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF0000000000000
  #_ REGISTER_OUT f2 0x7FF0000000000000
  #_ REGISTER_OUT f3 0x7FF8000000000000

test_fdiv_117_cr_GEN:
  #_ REGISTER_IN f1 0xFFF0000000000000
  #_ REGISTER_IN f2 0x7FF0000000000000
  fdiv. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF0000000000000
  #_ REGISTER_OUT f2 0x7FF0000000000000
  #_ REGISTER_OUT f3 0x7FF8000000000000
  #_ REGISTER_OUT cr 0x0A000000

test_fdiv_118_GEN:
  #_ REGISTER_IN f1 0xFFF0000000000000
  #_ REGISTER_IN f2 0xFFF0000000000000
  fdiv f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF0000000000000
  #_ REGISTER_OUT f2 0xFFF0000000000000
  #_ REGISTER_OUT f3 0x7FF8000000000000

test_fdiv_118_cr_GEN:
  #_ REGISTER_IN f1 0xFFF0000000000000
  #_ REGISTER_IN f2 0xFFF0000000000000
  fdiv. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF0000000000000
  #_ REGISTER_OUT f2 0xFFF0000000000000
  #_ REGISTER_OUT f3 0x7FF8000000000000
  #_ REGISTER_OUT cr 0x0A000000

test_fdiv_119_GEN:
  #_ REGISTER_IN f1 0xFFF0000000000000
  #_ REGISTER_IN f2 0xFFF8000000000000
  fdiv f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF0000000000000
  #_ REGISTER_OUT f2 0xFFF8000000000000
  #_ REGISTER_OUT f3 0xFFF8000000000000

test_fdiv_119_cr_GEN:
  #_ REGISTER_IN f1 0xFFF0000000000000
  #_ REGISTER_IN f2 0xFFF8000000000000
  fdiv. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF0000000000000
  #_ REGISTER_OUT f2 0xFFF8000000000000
  #_ REGISTER_OUT f3 0xFFF8000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fdiv_120_GEN:
  #_ REGISTER_IN f1 0xFFF0000000000000
  #_ REGISTER_IN f2 0xFFF4000000000000
  fdiv f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF0000000000000
  #_ REGISTER_OUT f2 0xFFF4000000000000
  #_ REGISTER_OUT f3 0xFFFC000000000000

test_fdiv_120_cr_GEN:
  #_ REGISTER_IN f1 0xFFF0000000000000
  #_ REGISTER_IN f2 0xFFF4000000000000
  fdiv. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF0000000000000
  #_ REGISTER_OUT f2 0xFFF4000000000000
  #_ REGISTER_OUT f3 0xFFFC000000000000
  #_ REGISTER_OUT cr 0x0A000000

test_fdiv_121_GEN:
  #_ REGISTER_IN f1 0xFFF8000000000000
  #_ REGISTER_IN f2 0x0000000000000000
  fdiv f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF8000000000000
  #_ REGISTER_OUT f2 0x0000000000000000
  #_ REGISTER_OUT f3 0xFFF8000000000000

test_fdiv_121_cr_GEN:
  #_ REGISTER_IN f1 0xFFF8000000000000
  #_ REGISTER_IN f2 0x0000000000000000
  fdiv. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF8000000000000
  #_ REGISTER_OUT f2 0x0000000000000000
  #_ REGISTER_OUT f3 0xFFF8000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fdiv_122_GEN:
  #_ REGISTER_IN f1 0xFFF8000000000000
  #_ REGISTER_IN f2 0x8000000000000000
  fdiv f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF8000000000000
  #_ REGISTER_OUT f2 0x8000000000000000
  #_ REGISTER_OUT f3 0xFFF8000000000000

test_fdiv_122_cr_GEN:
  #_ REGISTER_IN f1 0xFFF8000000000000
  #_ REGISTER_IN f2 0x8000000000000000
  fdiv. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF8000000000000
  #_ REGISTER_OUT f2 0x8000000000000000
  #_ REGISTER_OUT f3 0xFFF8000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fdiv_123_GEN:
  #_ REGISTER_IN f1 0xFFF8000000000000
  #_ REGISTER_IN f2 0x0000000000000001
  fdiv f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF8000000000000
  #_ REGISTER_OUT f2 0x0000000000000001
  #_ REGISTER_OUT f3 0xFFF8000000000000

test_fdiv_123_cr_GEN:
  #_ REGISTER_IN f1 0xFFF8000000000000
  #_ REGISTER_IN f2 0x0000000000000001
  fdiv. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF8000000000000
  #_ REGISTER_OUT f2 0x0000000000000001
  #_ REGISTER_OUT f3 0xFFF8000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fdiv_124_GEN:
  #_ REGISTER_IN f1 0xFFF8000000000000
  #_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
  fdiv f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF8000000000000
  #_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
  #_ REGISTER_OUT f3 0xFFF8000000000000

test_fdiv_124_cr_GEN:
  #_ REGISTER_IN f1 0xFFF8000000000000
  #_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
  fdiv. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF8000000000000
  #_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
  #_ REGISTER_OUT f3 0xFFF8000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fdiv_125_GEN:
  #_ REGISTER_IN f1 0xFFF8000000000000
  #_ REGISTER_IN f2 0x3FF0000000000000
  fdiv f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF8000000000000
  #_ REGISTER_OUT f2 0x3FF0000000000000
  #_ REGISTER_OUT f3 0xFFF8000000000000

test_fdiv_125_cr_GEN:
  #_ REGISTER_IN f1 0xFFF8000000000000
  #_ REGISTER_IN f2 0x3FF0000000000000
  fdiv. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF8000000000000
  #_ REGISTER_OUT f2 0x3FF0000000000000
  #_ REGISTER_OUT f3 0xFFF8000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fdiv_126_GEN:
  #_ REGISTER_IN f1 0xFFF8000000000000
  #_ REGISTER_IN f2 0xBFF0000000000000
  fdiv f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF8000000000000
  #_ REGISTER_OUT f2 0xBFF0000000000000
  #_ REGISTER_OUT f3 0xFFF8000000000000

test_fdiv_126_cr_GEN:
  #_ REGISTER_IN f1 0xFFF8000000000000
  #_ REGISTER_IN f2 0xBFF0000000000000
  fdiv. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF8000000000000
  #_ REGISTER_OUT f2 0xBFF0000000000000
  #_ REGISTER_OUT f3 0xFFF8000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fdiv_127_GEN:
  #_ REGISTER_IN f1 0xFFF8000000000000
  #_ REGISTER_IN f2 0xC1E0000000000000
  fdiv f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF8000000000000
  #_ REGISTER_OUT f2 0xC1E0000000000000
  #_ REGISTER_OUT f3 0xFFF8000000000000

test_fdiv_127_cr_GEN:
  #_ REGISTER_IN f1 0xFFF8000000000000
  #_ REGISTER_IN f2 0xC1E0000000000000
  fdiv. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF8000000000000
  #_ REGISTER_OUT f2 0xC1E0000000000000
  #_ REGISTER_OUT f3 0xFFF8000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fdiv_128_GEN:
  #_ REGISTER_IN f1 0xFFF8000000000000
  #_ REGISTER_IN f2 0x41DFFFFFFFC00000
  fdiv f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF8000000000000
  #_ REGISTER_OUT f2 0x41DFFFFFFFC00000
  #_ REGISTER_OUT f3 0xFFF8000000000000

test_fdiv_128_cr_GEN:
  #_ REGISTER_IN f1 0xFFF8000000000000
  #_ REGISTER_IN f2 0x41DFFFFFFFC00000
  fdiv. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF8000000000000
  #_ REGISTER_OUT f2 0x41DFFFFFFFC00000
  #_ REGISTER_OUT f3 0xFFF8000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fdiv_129_GEN:
  #_ REGISTER_IN f1 0xFFF8000000000000
  #_ REGISTER_IN f2 0x7FF0000000000000
  fdiv f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF8000000000000
  #_ REGISTER_OUT f2 0x7FF0000000000000
  #_ REGISTER_OUT f3 0xFFF8000000000000

test_fdiv_129_cr_GEN:
  #_ REGISTER_IN f1 0xFFF8000000000000
  #_ REGISTER_IN f2 0x7FF0000000000000
  fdiv. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF8000000000000
  #_ REGISTER_OUT f2 0x7FF0000000000000
  #_ REGISTER_OUT f3 0xFFF8000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fdiv_130_GEN:
  #_ REGISTER_IN f1 0xFFF8000000000000
  #_ REGISTER_IN f2 0xFFF0000000000000
  fdiv f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF8000000000000
  #_ REGISTER_OUT f2 0xFFF0000000000000
  #_ REGISTER_OUT f3 0xFFF8000000000000

test_fdiv_130_cr_GEN:
  #_ REGISTER_IN f1 0xFFF8000000000000
  #_ REGISTER_IN f2 0xFFF0000000000000
  fdiv. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF8000000000000
  #_ REGISTER_OUT f2 0xFFF0000000000000
  #_ REGISTER_OUT f3 0xFFF8000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fdiv_131_GEN:
  #_ REGISTER_IN f1 0xFFF8000000000000
  #_ REGISTER_IN f2 0xFFF8000000000000
  fdiv f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF8000000000000
  #_ REGISTER_OUT f2 0xFFF8000000000000
  #_ REGISTER_OUT f3 0xFFF8000000000000

test_fdiv_131_cr_GEN:
  #_ REGISTER_IN f1 0xFFF8000000000000
  #_ REGISTER_IN f2 0xFFF8000000000000
  fdiv. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF8000000000000
  #_ REGISTER_OUT f2 0xFFF8000000000000
  #_ REGISTER_OUT f3 0xFFF8000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fdiv_132_GEN:
  #_ REGISTER_IN f1 0xFFF8000000000000
  #_ REGISTER_IN f2 0xFFF4000000000000
  fdiv f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF8000000000000
  #_ REGISTER_OUT f2 0xFFF4000000000000
  #_ REGISTER_OUT f3 0xFFF8000000000000

test_fdiv_132_cr_GEN:
  #_ REGISTER_IN f1 0xFFF8000000000000
  #_ REGISTER_IN f2 0xFFF4000000000000
  fdiv. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF8000000000000
  #_ REGISTER_OUT f2 0xFFF4000000000000
  #_ REGISTER_OUT f3 0xFFF8000000000000
  #_ REGISTER_OUT cr 0x0A000000

test_fdiv_133_GEN:
  #_ REGISTER_IN f1 0xFFF4000000000000
  #_ REGISTER_IN f2 0x0000000000000000
  fdiv f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF4000000000000
  #_ REGISTER_OUT f2 0x0000000000000000
  #_ REGISTER_OUT f3 0xFFFC000000000000

test_fdiv_133_cr_GEN:
  #_ REGISTER_IN f1 0xFFF4000000000000
  #_ REGISTER_IN f2 0x0000000000000000
  fdiv. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF4000000000000
  #_ REGISTER_OUT f2 0x0000000000000000
  #_ REGISTER_OUT f3 0xFFFC000000000000
  #_ REGISTER_OUT cr 0x0A000000

test_fdiv_134_GEN:
  #_ REGISTER_IN f1 0xFFF4000000000000
  #_ REGISTER_IN f2 0x8000000000000000
  fdiv f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF4000000000000
  #_ REGISTER_OUT f2 0x8000000000000000
  #_ REGISTER_OUT f3 0xFFFC000000000000

test_fdiv_134_cr_GEN:
  #_ REGISTER_IN f1 0xFFF4000000000000
  #_ REGISTER_IN f2 0x8000000000000000
  fdiv. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF4000000000000
  #_ REGISTER_OUT f2 0x8000000000000000
  #_ REGISTER_OUT f3 0xFFFC000000000000
  #_ REGISTER_OUT cr 0x0A000000

test_fdiv_135_GEN:
  #_ REGISTER_IN f1 0xFFF4000000000000
  #_ REGISTER_IN f2 0x0000000000000001
  fdiv f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF4000000000000
  #_ REGISTER_OUT f2 0x0000000000000001
  #_ REGISTER_OUT f3 0xFFFC000000000000

test_fdiv_135_cr_GEN:
  #_ REGISTER_IN f1 0xFFF4000000000000
  #_ REGISTER_IN f2 0x0000000000000001
  fdiv. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF4000000000000
  #_ REGISTER_OUT f2 0x0000000000000001
  #_ REGISTER_OUT f3 0xFFFC000000000000
  #_ REGISTER_OUT cr 0x0A000000

test_fdiv_136_GEN:
  #_ REGISTER_IN f1 0xFFF4000000000000
  #_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
  fdiv f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF4000000000000
  #_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
  #_ REGISTER_OUT f3 0xFFFC000000000000

test_fdiv_136_cr_GEN:
  #_ REGISTER_IN f1 0xFFF4000000000000
  #_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
  fdiv. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF4000000000000
  #_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
  #_ REGISTER_OUT f3 0xFFFC000000000000
  #_ REGISTER_OUT cr 0x0A000000

test_fdiv_137_GEN:
  #_ REGISTER_IN f1 0xFFF4000000000000
  #_ REGISTER_IN f2 0x3FF0000000000000
  fdiv f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF4000000000000
  #_ REGISTER_OUT f2 0x3FF0000000000000
  #_ REGISTER_OUT f3 0xFFFC000000000000

test_fdiv_137_cr_GEN:
  #_ REGISTER_IN f1 0xFFF4000000000000
  #_ REGISTER_IN f2 0x3FF0000000000000
  fdiv. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF4000000000000
  #_ REGISTER_OUT f2 0x3FF0000000000000
  #_ REGISTER_OUT f3 0xFFFC000000000000
  #_ REGISTER_OUT cr 0x0A000000

test_fdiv_138_GEN:
  #_ REGISTER_IN f1 0xFFF4000000000000
  #_ REGISTER_IN f2 0xBFF0000000000000
  fdiv f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF4000000000000
  #_ REGISTER_OUT f2 0xBFF0000000000000
  #_ REGISTER_OUT f3 0xFFFC000000000000

test_fdiv_138_cr_GEN:
  #_ REGISTER_IN f1 0xFFF4000000000000
  #_ REGISTER_IN f2 0xBFF0000000000000
  fdiv. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF4000000000000
  #_ REGISTER_OUT f2 0xBFF0000000000000
  #_ REGISTER_OUT f3 0xFFFC000000000000
  #_ REGISTER_OUT cr 0x0A000000

test_fdiv_139_GEN:
  #_ REGISTER_IN f1 0xFFF4000000000000
  #_ REGISTER_IN f2 0xC1E0000000000000
  fdiv f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF4000000000000
  #_ REGISTER_OUT f2 0xC1E0000000000000
  #_ REGISTER_OUT f3 0xFFFC000000000000

test_fdiv_139_cr_GEN:
  #_ REGISTER_IN f1 0xFFF4000000000000
  #_ REGISTER_IN f2 0xC1E0000000000000
  fdiv. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF4000000000000
  #_ REGISTER_OUT f2 0xC1E0000000000000
  #_ REGISTER_OUT f3 0xFFFC000000000000
  #_ REGISTER_OUT cr 0x0A000000

test_fdiv_140_GEN:
  #_ REGISTER_IN f1 0xFFF4000000000000
  #_ REGISTER_IN f2 0x41DFFFFFFFC00000
  fdiv f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF4000000000000
  #_ REGISTER_OUT f2 0x41DFFFFFFFC00000
  #_ REGISTER_OUT f3 0xFFFC000000000000

test_fdiv_140_cr_GEN:
  #_ REGISTER_IN f1 0xFFF4000000000000
  #_ REGISTER_IN f2 0x41DFFFFFFFC00000
  fdiv. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF4000000000000
  #_ REGISTER_OUT f2 0x41DFFFFFFFC00000
  #_ REGISTER_OUT f3 0xFFFC000000000000
  #_ REGISTER_OUT cr 0x0A000000

test_fdiv_141_GEN:
  #_ REGISTER_IN f1 0xFFF4000000000000
  #_ REGISTER_IN f2 0x7FF0000000000000
  fdiv f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF4000000000000
  #_ REGISTER_OUT f2 0x7FF0000000000000
  #_ REGISTER_OUT f3 0xFFFC000000000000

test_fdiv_141_cr_GEN:
  #_ REGISTER_IN f1 0xFFF4000000000000
  #_ REGISTER_IN f2 0x7FF0000000000000
  fdiv. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF4000000000000
  #_ REGISTER_OUT f2 0x7FF0000000000000
  #_ REGISTER_OUT f3 0xFFFC000000000000
  #_ REGISTER_OUT cr 0x0A000000

test_fdiv_142_GEN:
  #_ REGISTER_IN f1 0xFFF4000000000000
  #_ REGISTER_IN f2 0xFFF0000000000000
  fdiv f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF4000000000000
  #_ REGISTER_OUT f2 0xFFF0000000000000
  #_ REGISTER_OUT f3 0xFFFC000000000000

test_fdiv_142_cr_GEN:
  #_ REGISTER_IN f1 0xFFF4000000000000
  #_ REGISTER_IN f2 0xFFF0000000000000
  fdiv. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF4000000000000
  #_ REGISTER_OUT f2 0xFFF0000000000000
  #_ REGISTER_OUT f3 0xFFFC000000000000
  #_ REGISTER_OUT cr 0x0A000000

test_fdiv_143_GEN:
  #_ REGISTER_IN f1 0xFFF4000000000000
  #_ REGISTER_IN f2 0xFFF8000000000000
  fdiv f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF4000000000000
  #_ REGISTER_OUT f2 0xFFF8000000000000
  #_ REGISTER_OUT f3 0xFFFC000000000000

test_fdiv_143_cr_GEN:
  #_ REGISTER_IN f1 0xFFF4000000000000
  #_ REGISTER_IN f2 0xFFF8000000000000
  fdiv. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF4000000000000
  #_ REGISTER_OUT f2 0xFFF8000000000000
  #_ REGISTER_OUT f3 0xFFFC000000000000
  #_ REGISTER_OUT cr 0x0A000000

test_fdiv_144_GEN:
  #_ REGISTER_IN f1 0xFFF4000000000000
  #_ REGISTER_IN f2 0xFFF4000000000000
  fdiv f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF4000000000000
  #_ REGISTER_OUT f2 0xFFF4000000000000
  #_ REGISTER_OUT f3 0xFFFC000000000000

test_fdiv_144_cr_GEN:
  #_ REGISTER_IN f1 0xFFF4000000000000
  #_ REGISTER_IN f2 0xFFF4000000000000
  fdiv. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF4000000000000
  #_ REGISTER_OUT f2 0xFFF4000000000000
  #_ REGISTER_OUT f3 0xFFFC000000000000
  #_ REGISTER_OUT cr 0x0A000000

