test_fsubs_1_GEN:
  #_ REGISTER_IN f1 0x0000000000000000
  #_ REGISTER_IN f2 0x0000000000000000
  fsubs f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x0000000000000000
  #_ REGISTER_OUT f2 0x0000000000000000
  #_ REGISTER_OUT f3 0x0000000000000000

test_fsubs_1_cr_GEN:
  #_ REGISTER_IN f1 0x0000000000000000
  #_ REGISTER_IN f2 0x0000000000000000
  fsubs. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x0000000000000000
  #_ REGISTER_OUT f2 0x0000000000000000
  #_ REGISTER_OUT f3 0x0000000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fsubs_2_GEN:
  #_ REGISTER_IN f1 0x0000000000000000
  #_ REGISTER_IN f2 0x8000000000000000
  fsubs f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x0000000000000000
  #_ REGISTER_OUT f2 0x8000000000000000
  #_ REGISTER_OUT f3 0x0000000000000000

test_fsubs_2_cr_GEN:
  #_ REGISTER_IN f1 0x0000000000000000
  #_ REGISTER_IN f2 0x8000000000000000
  fsubs. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x0000000000000000
  #_ REGISTER_OUT f2 0x8000000000000000
  #_ REGISTER_OUT f3 0x0000000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fsubs_3_GEN:
  #_ REGISTER_IN f1 0x0000000000000000
  #_ REGISTER_IN f2 0x0000000000000001
  fsubs f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x0000000000000000
  #_ REGISTER_OUT f2 0x0000000000000001
  #_ REGISTER_OUT f3 0x7FF8000000000000

test_fsubs_3_cr_GEN:
  #_ REGISTER_IN f1 0x0000000000000000
  #_ REGISTER_IN f2 0x0000000000000001
  fsubs. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x0000000000000000
  #_ REGISTER_OUT f2 0x0000000000000001
  #_ REGISTER_OUT f3 0x7FF8000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fsubs_4_GEN:
  #_ REGISTER_IN f1 0x0000000000000000
  #_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
  fsubs f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x0000000000000000
  #_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
  #_ REGISTER_OUT f3 0x7FF8000000000000

test_fsubs_4_cr_GEN:
  #_ REGISTER_IN f1 0x0000000000000000
  #_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
  fsubs. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x0000000000000000
  #_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
  #_ REGISTER_OUT f3 0x7FF8000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fsubs_5_GEN:
  #_ REGISTER_IN f1 0x0000000000000000
  #_ REGISTER_IN f2 0x3FF0000000000000
  fsubs f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x0000000000000000
  #_ REGISTER_OUT f2 0x3FF0000000000000
  #_ REGISTER_OUT f3 0xBFF0000000000000

test_fsubs_5_cr_GEN:
  #_ REGISTER_IN f1 0x0000000000000000
  #_ REGISTER_IN f2 0x3FF0000000000000
  fsubs. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x0000000000000000
  #_ REGISTER_OUT f2 0x3FF0000000000000
  #_ REGISTER_OUT f3 0xBFF0000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fsubs_6_GEN:
  #_ REGISTER_IN f1 0x0000000000000000
  #_ REGISTER_IN f2 0xBFF0000000000000
  fsubs f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x0000000000000000
  #_ REGISTER_OUT f2 0xBFF0000000000000
  #_ REGISTER_OUT f3 0x3FF0000000000000

test_fsubs_6_cr_GEN:
  #_ REGISTER_IN f1 0x0000000000000000
  #_ REGISTER_IN f2 0xBFF0000000000000
  fsubs. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x0000000000000000
  #_ REGISTER_OUT f2 0xBFF0000000000000
  #_ REGISTER_OUT f3 0x3FF0000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fsubs_7_GEN:
  #_ REGISTER_IN f1 0x0000000000000000
  #_ REGISTER_IN f2 0xC1E0000000000000
  fsubs f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x0000000000000000
  #_ REGISTER_OUT f2 0xC1E0000000000000
  #_ REGISTER_OUT f3 0x41E0000000000000

test_fsubs_7_cr_GEN:
  #_ REGISTER_IN f1 0x0000000000000000
  #_ REGISTER_IN f2 0xC1E0000000000000
  fsubs. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x0000000000000000
  #_ REGISTER_OUT f2 0xC1E0000000000000
  #_ REGISTER_OUT f3 0x41E0000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fsubs_8_GEN:
  #_ REGISTER_IN f1 0x0000000000000000
  #_ REGISTER_IN f2 0x41DFFFFFFFC00000
  fsubs f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x0000000000000000
  #_ REGISTER_OUT f2 0x41DFFFFFFFC00000
  #_ REGISTER_OUT f3 0xC1E0000000000000

test_fsubs_8_cr_GEN:
  #_ REGISTER_IN f1 0x0000000000000000
  #_ REGISTER_IN f2 0x41DFFFFFFFC00000
  fsubs. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x0000000000000000
  #_ REGISTER_OUT f2 0x41DFFFFFFFC00000
  #_ REGISTER_OUT f3 0xC1E0000000000000
  #_ REGISTER_OUT cr 0x08000000

test_fsubs_9_GEN:
  #_ REGISTER_IN f1 0x0000000000000000
  #_ REGISTER_IN f2 0x7FF0000000000000
  fsubs f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x0000000000000000
  #_ REGISTER_OUT f2 0x7FF0000000000000
  #_ REGISTER_OUT f3 0xFFF0000000000000

test_fsubs_9_cr_GEN:
  #_ REGISTER_IN f1 0x0000000000000000
  #_ REGISTER_IN f2 0x7FF0000000000000
  fsubs. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x0000000000000000
  #_ REGISTER_OUT f2 0x7FF0000000000000
  #_ REGISTER_OUT f3 0xFFF0000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fsubs_10_GEN:
  #_ REGISTER_IN f1 0x0000000000000000
  #_ REGISTER_IN f2 0xFFF0000000000000
  fsubs f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x0000000000000000
  #_ REGISTER_OUT f2 0xFFF0000000000000
  #_ REGISTER_OUT f3 0x7FF0000000000000

test_fsubs_10_cr_GEN:
  #_ REGISTER_IN f1 0x0000000000000000
  #_ REGISTER_IN f2 0xFFF0000000000000
  fsubs. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x0000000000000000
  #_ REGISTER_OUT f2 0xFFF0000000000000
  #_ REGISTER_OUT f3 0x7FF0000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fsubs_11_GEN:
  #_ REGISTER_IN f1 0x0000000000000000
  #_ REGISTER_IN f2 0xFFF8000000000000
  fsubs f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x0000000000000000
  #_ REGISTER_OUT f2 0xFFF8000000000000
  #_ REGISTER_OUT f3 0xFFF8000000000000

test_fsubs_11_cr_GEN:
  #_ REGISTER_IN f1 0x0000000000000000
  #_ REGISTER_IN f2 0xFFF8000000000000
  fsubs. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x0000000000000000
  #_ REGISTER_OUT f2 0xFFF8000000000000
  #_ REGISTER_OUT f3 0xFFF8000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fsubs_12_GEN:
  #_ REGISTER_IN f1 0x0000000000000000
  #_ REGISTER_IN f2 0xFFF4000000000000
  fsubs f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x0000000000000000
  #_ REGISTER_OUT f2 0xFFF4000000000000
  #_ REGISTER_OUT f3 0xFFFC000000000000

test_fsubs_12_cr_GEN:
  #_ REGISTER_IN f1 0x0000000000000000
  #_ REGISTER_IN f2 0xFFF4000000000000
  fsubs. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x0000000000000000
  #_ REGISTER_OUT f2 0xFFF4000000000000
  #_ REGISTER_OUT f3 0xFFFC000000000000
  #_ REGISTER_OUT cr 0x0A000000

test_fsubs_13_GEN:
  #_ REGISTER_IN f1 0x8000000000000000
  #_ REGISTER_IN f2 0x0000000000000000
  fsubs f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x8000000000000000
  #_ REGISTER_OUT f2 0x0000000000000000
  #_ REGISTER_OUT f3 0x8000000000000000

test_fsubs_13_cr_GEN:
  #_ REGISTER_IN f1 0x8000000000000000
  #_ REGISTER_IN f2 0x0000000000000000
  fsubs. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x8000000000000000
  #_ REGISTER_OUT f2 0x0000000000000000
  #_ REGISTER_OUT f3 0x8000000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fsubs_14_GEN:
  #_ REGISTER_IN f1 0x8000000000000000
  #_ REGISTER_IN f2 0x8000000000000000
  fsubs f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x8000000000000000
  #_ REGISTER_OUT f2 0x8000000000000000
  #_ REGISTER_OUT f3 0x0000000000000000

test_fsubs_14_cr_GEN:
  #_ REGISTER_IN f1 0x8000000000000000
  #_ REGISTER_IN f2 0x8000000000000000
  fsubs. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x8000000000000000
  #_ REGISTER_OUT f2 0x8000000000000000
  #_ REGISTER_OUT f3 0x0000000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fsubs_15_GEN:
  #_ REGISTER_IN f1 0x8000000000000000
  #_ REGISTER_IN f2 0x0000000000000001
  fsubs f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x8000000000000000
  #_ REGISTER_OUT f2 0x0000000000000001
  #_ REGISTER_OUT f3 0x7FF8000000000000

test_fsubs_15_cr_GEN:
  #_ REGISTER_IN f1 0x8000000000000000
  #_ REGISTER_IN f2 0x0000000000000001
  fsubs. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x8000000000000000
  #_ REGISTER_OUT f2 0x0000000000000001
  #_ REGISTER_OUT f3 0x7FF8000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fsubs_16_GEN:
  #_ REGISTER_IN f1 0x8000000000000000
  #_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
  fsubs f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x8000000000000000
  #_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
  #_ REGISTER_OUT f3 0x7FF8000000000000

test_fsubs_16_cr_GEN:
  #_ REGISTER_IN f1 0x8000000000000000
  #_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
  fsubs. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x8000000000000000
  #_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
  #_ REGISTER_OUT f3 0x7FF8000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fsubs_17_GEN:
  #_ REGISTER_IN f1 0x8000000000000000
  #_ REGISTER_IN f2 0x3FF0000000000000
  fsubs f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x8000000000000000
  #_ REGISTER_OUT f2 0x3FF0000000000000
  #_ REGISTER_OUT f3 0xBFF0000000000000

test_fsubs_17_cr_GEN:
  #_ REGISTER_IN f1 0x8000000000000000
  #_ REGISTER_IN f2 0x3FF0000000000000
  fsubs. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x8000000000000000
  #_ REGISTER_OUT f2 0x3FF0000000000000
  #_ REGISTER_OUT f3 0xBFF0000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fsubs_18_GEN:
  #_ REGISTER_IN f1 0x8000000000000000
  #_ REGISTER_IN f2 0xBFF0000000000000
  fsubs f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x8000000000000000
  #_ REGISTER_OUT f2 0xBFF0000000000000
  #_ REGISTER_OUT f3 0x3FF0000000000000

test_fsubs_18_cr_GEN:
  #_ REGISTER_IN f1 0x8000000000000000
  #_ REGISTER_IN f2 0xBFF0000000000000
  fsubs. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x8000000000000000
  #_ REGISTER_OUT f2 0xBFF0000000000000
  #_ REGISTER_OUT f3 0x3FF0000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fsubs_19_GEN:
  #_ REGISTER_IN f1 0x8000000000000000
  #_ REGISTER_IN f2 0xC1E0000000000000
  fsubs f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x8000000000000000
  #_ REGISTER_OUT f2 0xC1E0000000000000
  #_ REGISTER_OUT f3 0x41E0000000000000

test_fsubs_19_cr_GEN:
  #_ REGISTER_IN f1 0x8000000000000000
  #_ REGISTER_IN f2 0xC1E0000000000000
  fsubs. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x8000000000000000
  #_ REGISTER_OUT f2 0xC1E0000000000000
  #_ REGISTER_OUT f3 0x41E0000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fsubs_20_GEN:
  #_ REGISTER_IN f1 0x8000000000000000
  #_ REGISTER_IN f2 0x41DFFFFFFFC00000
  fsubs f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x8000000000000000
  #_ REGISTER_OUT f2 0x41DFFFFFFFC00000
  #_ REGISTER_OUT f3 0xC1E0000000000000

test_fsubs_20_cr_GEN:
  #_ REGISTER_IN f1 0x8000000000000000
  #_ REGISTER_IN f2 0x41DFFFFFFFC00000
  fsubs. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x8000000000000000
  #_ REGISTER_OUT f2 0x41DFFFFFFFC00000
  #_ REGISTER_OUT f3 0xC1E0000000000000
  #_ REGISTER_OUT cr 0x08000000

test_fsubs_21_GEN:
  #_ REGISTER_IN f1 0x8000000000000000
  #_ REGISTER_IN f2 0x7FF0000000000000
  fsubs f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x8000000000000000
  #_ REGISTER_OUT f2 0x7FF0000000000000
  #_ REGISTER_OUT f3 0xFFF0000000000000

test_fsubs_21_cr_GEN:
  #_ REGISTER_IN f1 0x8000000000000000
  #_ REGISTER_IN f2 0x7FF0000000000000
  fsubs. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x8000000000000000
  #_ REGISTER_OUT f2 0x7FF0000000000000
  #_ REGISTER_OUT f3 0xFFF0000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fsubs_22_GEN:
  #_ REGISTER_IN f1 0x8000000000000000
  #_ REGISTER_IN f2 0xFFF0000000000000
  fsubs f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x8000000000000000
  #_ REGISTER_OUT f2 0xFFF0000000000000
  #_ REGISTER_OUT f3 0x7FF0000000000000

test_fsubs_22_cr_GEN:
  #_ REGISTER_IN f1 0x8000000000000000
  #_ REGISTER_IN f2 0xFFF0000000000000
  fsubs. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x8000000000000000
  #_ REGISTER_OUT f2 0xFFF0000000000000
  #_ REGISTER_OUT f3 0x7FF0000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fsubs_23_GEN:
  #_ REGISTER_IN f1 0x8000000000000000
  #_ REGISTER_IN f2 0xFFF8000000000000
  fsubs f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x8000000000000000
  #_ REGISTER_OUT f2 0xFFF8000000000000
  #_ REGISTER_OUT f3 0xFFF8000000000000

test_fsubs_23_cr_GEN:
  #_ REGISTER_IN f1 0x8000000000000000
  #_ REGISTER_IN f2 0xFFF8000000000000
  fsubs. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x8000000000000000
  #_ REGISTER_OUT f2 0xFFF8000000000000
  #_ REGISTER_OUT f3 0xFFF8000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fsubs_24_GEN:
  #_ REGISTER_IN f1 0x8000000000000000
  #_ REGISTER_IN f2 0xFFF4000000000000
  fsubs f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x8000000000000000
  #_ REGISTER_OUT f2 0xFFF4000000000000
  #_ REGISTER_OUT f3 0xFFFC000000000000

test_fsubs_24_cr_GEN:
  #_ REGISTER_IN f1 0x8000000000000000
  #_ REGISTER_IN f2 0xFFF4000000000000
  fsubs. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x8000000000000000
  #_ REGISTER_OUT f2 0xFFF4000000000000
  #_ REGISTER_OUT f3 0xFFFC000000000000
  #_ REGISTER_OUT cr 0x0A000000

test_fsubs_25_GEN:
  #_ REGISTER_IN f1 0x0000000000000001
  #_ REGISTER_IN f2 0x0000000000000000
  fsubs f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x0000000000000001
  #_ REGISTER_OUT f2 0x0000000000000000
  #_ REGISTER_OUT f3 0x7FF8000000000000

test_fsubs_25_cr_GEN:
  #_ REGISTER_IN f1 0x0000000000000001
  #_ REGISTER_IN f2 0x0000000000000000
  fsubs. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x0000000000000001
  #_ REGISTER_OUT f2 0x0000000000000000
  #_ REGISTER_OUT f3 0x7FF8000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fsubs_26_GEN:
  #_ REGISTER_IN f1 0x0000000000000001
  #_ REGISTER_IN f2 0x8000000000000000
  fsubs f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x0000000000000001
  #_ REGISTER_OUT f2 0x8000000000000000
  #_ REGISTER_OUT f3 0x7FF8000000000000

test_fsubs_26_cr_GEN:
  #_ REGISTER_IN f1 0x0000000000000001
  #_ REGISTER_IN f2 0x8000000000000000
  fsubs. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x0000000000000001
  #_ REGISTER_OUT f2 0x8000000000000000
  #_ REGISTER_OUT f3 0x7FF8000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fsubs_27_GEN:
  #_ REGISTER_IN f1 0x0000000000000001
  #_ REGISTER_IN f2 0x0000000000000001
  fsubs f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x0000000000000001
  #_ REGISTER_OUT f2 0x0000000000000001
  #_ REGISTER_OUT f3 0x7FF8000000000000

test_fsubs_27_cr_GEN:
  #_ REGISTER_IN f1 0x0000000000000001
  #_ REGISTER_IN f2 0x0000000000000001
  fsubs. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x0000000000000001
  #_ REGISTER_OUT f2 0x0000000000000001
  #_ REGISTER_OUT f3 0x7FF8000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fsubs_28_GEN:
  #_ REGISTER_IN f1 0x0000000000000001
  #_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
  fsubs f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x0000000000000001
  #_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
  #_ REGISTER_OUT f3 0x7FF8000000000000

test_fsubs_28_cr_GEN:
  #_ REGISTER_IN f1 0x0000000000000001
  #_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
  fsubs. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x0000000000000001
  #_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
  #_ REGISTER_OUT f3 0x7FF8000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fsubs_29_GEN:
  #_ REGISTER_IN f1 0x0000000000000001
  #_ REGISTER_IN f2 0x3FF0000000000000
  fsubs f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x0000000000000001
  #_ REGISTER_OUT f2 0x3FF0000000000000
  #_ REGISTER_OUT f3 0x7FF8000000000000

test_fsubs_29_cr_GEN:
  #_ REGISTER_IN f1 0x0000000000000001
  #_ REGISTER_IN f2 0x3FF0000000000000
  fsubs. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x0000000000000001
  #_ REGISTER_OUT f2 0x3FF0000000000000
  #_ REGISTER_OUT f3 0x7FF8000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fsubs_30_GEN:
  #_ REGISTER_IN f1 0x0000000000000001
  #_ REGISTER_IN f2 0xBFF0000000000000
  fsubs f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x0000000000000001
  #_ REGISTER_OUT f2 0xBFF0000000000000
  #_ REGISTER_OUT f3 0x7FF8000000000000

test_fsubs_30_cr_GEN:
  #_ REGISTER_IN f1 0x0000000000000001
  #_ REGISTER_IN f2 0xBFF0000000000000
  fsubs. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x0000000000000001
  #_ REGISTER_OUT f2 0xBFF0000000000000
  #_ REGISTER_OUT f3 0x7FF8000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fsubs_31_GEN:
  #_ REGISTER_IN f1 0x0000000000000001
  #_ REGISTER_IN f2 0xC1E0000000000000
  fsubs f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x0000000000000001
  #_ REGISTER_OUT f2 0xC1E0000000000000
  #_ REGISTER_OUT f3 0x7FF8000000000000

test_fsubs_31_cr_GEN:
  #_ REGISTER_IN f1 0x0000000000000001
  #_ REGISTER_IN f2 0xC1E0000000000000
  fsubs. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x0000000000000001
  #_ REGISTER_OUT f2 0xC1E0000000000000
  #_ REGISTER_OUT f3 0x7FF8000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fsubs_32_GEN:
  #_ REGISTER_IN f1 0x0000000000000001
  #_ REGISTER_IN f2 0x41DFFFFFFFC00000
  fsubs f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x0000000000000001
  #_ REGISTER_OUT f2 0x41DFFFFFFFC00000
  #_ REGISTER_OUT f3 0x7FF8000000000000

test_fsubs_32_cr_GEN:
  #_ REGISTER_IN f1 0x0000000000000001
  #_ REGISTER_IN f2 0x41DFFFFFFFC00000
  fsubs. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x0000000000000001
  #_ REGISTER_OUT f2 0x41DFFFFFFFC00000
  #_ REGISTER_OUT f3 0x7FF8000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fsubs_33_GEN:
  #_ REGISTER_IN f1 0x0000000000000001
  #_ REGISTER_IN f2 0x7FF0000000000000
  fsubs f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x0000000000000001
  #_ REGISTER_OUT f2 0x7FF0000000000000
  #_ REGISTER_OUT f3 0xFFF0000000000000

test_fsubs_33_cr_GEN:
  #_ REGISTER_IN f1 0x0000000000000001
  #_ REGISTER_IN f2 0x7FF0000000000000
  fsubs. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x0000000000000001
  #_ REGISTER_OUT f2 0x7FF0000000000000
  #_ REGISTER_OUT f3 0xFFF0000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fsubs_34_GEN:
  #_ REGISTER_IN f1 0x0000000000000001
  #_ REGISTER_IN f2 0xFFF0000000000000
  fsubs f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x0000000000000001
  #_ REGISTER_OUT f2 0xFFF0000000000000
  #_ REGISTER_OUT f3 0x7FF0000000000000

test_fsubs_34_cr_GEN:
  #_ REGISTER_IN f1 0x0000000000000001
  #_ REGISTER_IN f2 0xFFF0000000000000
  fsubs. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x0000000000000001
  #_ REGISTER_OUT f2 0xFFF0000000000000
  #_ REGISTER_OUT f3 0x7FF0000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fsubs_35_GEN:
  #_ REGISTER_IN f1 0x0000000000000001
  #_ REGISTER_IN f2 0xFFF8000000000000
  fsubs f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x0000000000000001
  #_ REGISTER_OUT f2 0xFFF8000000000000
  #_ REGISTER_OUT f3 0xFFF8000000000000

test_fsubs_35_cr_GEN:
  #_ REGISTER_IN f1 0x0000000000000001
  #_ REGISTER_IN f2 0xFFF8000000000000
  fsubs. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x0000000000000001
  #_ REGISTER_OUT f2 0xFFF8000000000000
  #_ REGISTER_OUT f3 0xFFF8000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fsubs_36_GEN:
  #_ REGISTER_IN f1 0x0000000000000001
  #_ REGISTER_IN f2 0xFFF4000000000000
  fsubs f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x0000000000000001
  #_ REGISTER_OUT f2 0xFFF4000000000000
  #_ REGISTER_OUT f3 0xFFFC000000000000

test_fsubs_36_cr_GEN:
  #_ REGISTER_IN f1 0x0000000000000001
  #_ REGISTER_IN f2 0xFFF4000000000000
  fsubs. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x0000000000000001
  #_ REGISTER_OUT f2 0xFFF4000000000000
  #_ REGISTER_OUT f3 0xFFFC000000000000
  #_ REGISTER_OUT cr 0x0A000000

test_fsubs_37_GEN:
  #_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
  #_ REGISTER_IN f2 0x0000000000000000
  fsubs f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
  #_ REGISTER_OUT f2 0x0000000000000000
  #_ REGISTER_OUT f3 0x7FF8000000000000

test_fsubs_37_cr_GEN:
  #_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
  #_ REGISTER_IN f2 0x0000000000000000
  fsubs. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
  #_ REGISTER_OUT f2 0x0000000000000000
  #_ REGISTER_OUT f3 0x7FF8000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fsubs_38_GEN:
  #_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
  #_ REGISTER_IN f2 0x8000000000000000
  fsubs f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
  #_ REGISTER_OUT f2 0x8000000000000000
  #_ REGISTER_OUT f3 0x7FF8000000000000

test_fsubs_38_cr_GEN:
  #_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
  #_ REGISTER_IN f2 0x8000000000000000
  fsubs. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
  #_ REGISTER_OUT f2 0x8000000000000000
  #_ REGISTER_OUT f3 0x7FF8000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fsubs_39_GEN:
  #_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
  #_ REGISTER_IN f2 0x0000000000000001
  fsubs f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
  #_ REGISTER_OUT f2 0x0000000000000001
  #_ REGISTER_OUT f3 0x7FF8000000000000

test_fsubs_39_cr_GEN:
  #_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
  #_ REGISTER_IN f2 0x0000000000000001
  fsubs. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
  #_ REGISTER_OUT f2 0x0000000000000001
  #_ REGISTER_OUT f3 0x7FF8000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fsubs_40_GEN:
  #_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
  #_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
  fsubs f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
  #_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
  #_ REGISTER_OUT f3 0x7FF8000000000000

test_fsubs_40_cr_GEN:
  #_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
  #_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
  fsubs. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
  #_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
  #_ REGISTER_OUT f3 0x7FF8000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fsubs_41_GEN:
  #_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
  #_ REGISTER_IN f2 0x3FF0000000000000
  fsubs f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
  #_ REGISTER_OUT f2 0x3FF0000000000000
  #_ REGISTER_OUT f3 0x7FF8000000000000

test_fsubs_41_cr_GEN:
  #_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
  #_ REGISTER_IN f2 0x3FF0000000000000
  fsubs. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
  #_ REGISTER_OUT f2 0x3FF0000000000000
  #_ REGISTER_OUT f3 0x7FF8000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fsubs_42_GEN:
  #_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
  #_ REGISTER_IN f2 0xBFF0000000000000
  fsubs f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
  #_ REGISTER_OUT f2 0xBFF0000000000000
  #_ REGISTER_OUT f3 0x7FF8000000000000

test_fsubs_42_cr_GEN:
  #_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
  #_ REGISTER_IN f2 0xBFF0000000000000
  fsubs. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
  #_ REGISTER_OUT f2 0xBFF0000000000000
  #_ REGISTER_OUT f3 0x7FF8000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fsubs_43_GEN:
  #_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
  #_ REGISTER_IN f2 0xC1E0000000000000
  fsubs f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
  #_ REGISTER_OUT f2 0xC1E0000000000000
  #_ REGISTER_OUT f3 0x7FF8000000000000

test_fsubs_43_cr_GEN:
  #_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
  #_ REGISTER_IN f2 0xC1E0000000000000
  fsubs. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
  #_ REGISTER_OUT f2 0xC1E0000000000000
  #_ REGISTER_OUT f3 0x7FF8000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fsubs_44_GEN:
  #_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
  #_ REGISTER_IN f2 0x41DFFFFFFFC00000
  fsubs f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
  #_ REGISTER_OUT f2 0x41DFFFFFFFC00000
  #_ REGISTER_OUT f3 0x7FF8000000000000

test_fsubs_44_cr_GEN:
  #_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
  #_ REGISTER_IN f2 0x41DFFFFFFFC00000
  fsubs. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
  #_ REGISTER_OUT f2 0x41DFFFFFFFC00000
  #_ REGISTER_OUT f3 0x7FF8000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fsubs_45_GEN:
  #_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
  #_ REGISTER_IN f2 0x7FF0000000000000
  fsubs f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
  #_ REGISTER_OUT f2 0x7FF0000000000000
  #_ REGISTER_OUT f3 0xFFF0000000000000

test_fsubs_45_cr_GEN:
  #_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
  #_ REGISTER_IN f2 0x7FF0000000000000
  fsubs. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
  #_ REGISTER_OUT f2 0x7FF0000000000000
  #_ REGISTER_OUT f3 0xFFF0000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fsubs_46_GEN:
  #_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
  #_ REGISTER_IN f2 0xFFF0000000000000
  fsubs f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
  #_ REGISTER_OUT f2 0xFFF0000000000000
  #_ REGISTER_OUT f3 0x7FF0000000000000

test_fsubs_46_cr_GEN:
  #_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
  #_ REGISTER_IN f2 0xFFF0000000000000
  fsubs. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
  #_ REGISTER_OUT f2 0xFFF0000000000000
  #_ REGISTER_OUT f3 0x7FF0000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fsubs_47_GEN:
  #_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
  #_ REGISTER_IN f2 0xFFF8000000000000
  fsubs f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
  #_ REGISTER_OUT f2 0xFFF8000000000000
  #_ REGISTER_OUT f3 0xFFF8000000000000

test_fsubs_47_cr_GEN:
  #_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
  #_ REGISTER_IN f2 0xFFF8000000000000
  fsubs. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
  #_ REGISTER_OUT f2 0xFFF8000000000000
  #_ REGISTER_OUT f3 0xFFF8000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fsubs_48_GEN:
  #_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
  #_ REGISTER_IN f2 0xFFF4000000000000
  fsubs f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
  #_ REGISTER_OUT f2 0xFFF4000000000000
  #_ REGISTER_OUT f3 0xFFFC000000000000

test_fsubs_48_cr_GEN:
  #_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
  #_ REGISTER_IN f2 0xFFF4000000000000
  fsubs. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
  #_ REGISTER_OUT f2 0xFFF4000000000000
  #_ REGISTER_OUT f3 0xFFFC000000000000
  #_ REGISTER_OUT cr 0x0A000000

test_fsubs_49_GEN:
  #_ REGISTER_IN f1 0x3FF0000000000000
  #_ REGISTER_IN f2 0x0000000000000000
  fsubs f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x3FF0000000000000
  #_ REGISTER_OUT f2 0x0000000000000000
  #_ REGISTER_OUT f3 0x3FF0000000000000

test_fsubs_49_cr_GEN:
  #_ REGISTER_IN f1 0x3FF0000000000000
  #_ REGISTER_IN f2 0x0000000000000000
  fsubs. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x3FF0000000000000
  #_ REGISTER_OUT f2 0x0000000000000000
  #_ REGISTER_OUT f3 0x3FF0000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fsubs_50_GEN:
  #_ REGISTER_IN f1 0x3FF0000000000000
  #_ REGISTER_IN f2 0x8000000000000000
  fsubs f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x3FF0000000000000
  #_ REGISTER_OUT f2 0x8000000000000000
  #_ REGISTER_OUT f3 0x3FF0000000000000

test_fsubs_50_cr_GEN:
  #_ REGISTER_IN f1 0x3FF0000000000000
  #_ REGISTER_IN f2 0x8000000000000000
  fsubs. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x3FF0000000000000
  #_ REGISTER_OUT f2 0x8000000000000000
  #_ REGISTER_OUT f3 0x3FF0000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fsubs_51_GEN:
  #_ REGISTER_IN f1 0x3FF0000000000000
  #_ REGISTER_IN f2 0x0000000000000001
  fsubs f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x3FF0000000000000
  #_ REGISTER_OUT f2 0x0000000000000001
  #_ REGISTER_OUT f3 0x7FF8000000000000

test_fsubs_51_cr_GEN:
  #_ REGISTER_IN f1 0x3FF0000000000000
  #_ REGISTER_IN f2 0x0000000000000001
  fsubs. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x3FF0000000000000
  #_ REGISTER_OUT f2 0x0000000000000001
  #_ REGISTER_OUT f3 0x7FF8000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fsubs_52_GEN:
  #_ REGISTER_IN f1 0x3FF0000000000000
  #_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
  fsubs f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x3FF0000000000000
  #_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
  #_ REGISTER_OUT f3 0x7FF8000000000000

test_fsubs_52_cr_GEN:
  #_ REGISTER_IN f1 0x3FF0000000000000
  #_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
  fsubs. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x3FF0000000000000
  #_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
  #_ REGISTER_OUT f3 0x7FF8000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fsubs_53_GEN:
  #_ REGISTER_IN f1 0x3FF0000000000000
  #_ REGISTER_IN f2 0x3FF0000000000000
  fsubs f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x3FF0000000000000
  #_ REGISTER_OUT f2 0x3FF0000000000000
  #_ REGISTER_OUT f3 0x0000000000000000

test_fsubs_53_cr_GEN:
  #_ REGISTER_IN f1 0x3FF0000000000000
  #_ REGISTER_IN f2 0x3FF0000000000000
  fsubs. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x3FF0000000000000
  #_ REGISTER_OUT f2 0x3FF0000000000000
  #_ REGISTER_OUT f3 0x0000000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fsubs_54_GEN:
  #_ REGISTER_IN f1 0x3FF0000000000000
  #_ REGISTER_IN f2 0xBFF0000000000000
  fsubs f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x3FF0000000000000
  #_ REGISTER_OUT f2 0xBFF0000000000000
  #_ REGISTER_OUT f3 0x4000000000000000

test_fsubs_54_cr_GEN:
  #_ REGISTER_IN f1 0x3FF0000000000000
  #_ REGISTER_IN f2 0xBFF0000000000000
  fsubs. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x3FF0000000000000
  #_ REGISTER_OUT f2 0xBFF0000000000000
  #_ REGISTER_OUT f3 0x4000000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fsubs_55_GEN:
  #_ REGISTER_IN f1 0x3FF0000000000000
  #_ REGISTER_IN f2 0xC1E0000000000000
  fsubs f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x3FF0000000000000
  #_ REGISTER_OUT f2 0xC1E0000000000000
  #_ REGISTER_OUT f3 0x41E0000000000000

test_fsubs_55_cr_GEN:
  #_ REGISTER_IN f1 0x3FF0000000000000
  #_ REGISTER_IN f2 0xC1E0000000000000
  fsubs. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x3FF0000000000000
  #_ REGISTER_OUT f2 0xC1E0000000000000
  #_ REGISTER_OUT f3 0x41E0000000000000
  #_ REGISTER_OUT cr 0x08000000

test_fsubs_56_GEN:
  #_ REGISTER_IN f1 0x3FF0000000000000
  #_ REGISTER_IN f2 0x41DFFFFFFFC00000
  fsubs f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x3FF0000000000000
  #_ REGISTER_OUT f2 0x41DFFFFFFFC00000
  #_ REGISTER_OUT f3 0xC1E0000000000000

test_fsubs_56_cr_GEN:
  #_ REGISTER_IN f1 0x3FF0000000000000
  #_ REGISTER_IN f2 0x41DFFFFFFFC00000
  fsubs. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x3FF0000000000000
  #_ REGISTER_OUT f2 0x41DFFFFFFFC00000
  #_ REGISTER_OUT f3 0xC1E0000000000000
  #_ REGISTER_OUT cr 0x08000000

test_fsubs_57_GEN:
  #_ REGISTER_IN f1 0x3FF0000000000000
  #_ REGISTER_IN f2 0x7FF0000000000000
  fsubs f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x3FF0000000000000
  #_ REGISTER_OUT f2 0x7FF0000000000000
  #_ REGISTER_OUT f3 0xFFF0000000000000

test_fsubs_57_cr_GEN:
  #_ REGISTER_IN f1 0x3FF0000000000000
  #_ REGISTER_IN f2 0x7FF0000000000000
  fsubs. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x3FF0000000000000
  #_ REGISTER_OUT f2 0x7FF0000000000000
  #_ REGISTER_OUT f3 0xFFF0000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fsubs_58_GEN:
  #_ REGISTER_IN f1 0x3FF0000000000000
  #_ REGISTER_IN f2 0xFFF0000000000000
  fsubs f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x3FF0000000000000
  #_ REGISTER_OUT f2 0xFFF0000000000000
  #_ REGISTER_OUT f3 0x7FF0000000000000

test_fsubs_58_cr_GEN:
  #_ REGISTER_IN f1 0x3FF0000000000000
  #_ REGISTER_IN f2 0xFFF0000000000000
  fsubs. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x3FF0000000000000
  #_ REGISTER_OUT f2 0xFFF0000000000000
  #_ REGISTER_OUT f3 0x7FF0000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fsubs_59_GEN:
  #_ REGISTER_IN f1 0x3FF0000000000000
  #_ REGISTER_IN f2 0xFFF8000000000000
  fsubs f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x3FF0000000000000
  #_ REGISTER_OUT f2 0xFFF8000000000000
  #_ REGISTER_OUT f3 0xFFF8000000000000

test_fsubs_59_cr_GEN:
  #_ REGISTER_IN f1 0x3FF0000000000000
  #_ REGISTER_IN f2 0xFFF8000000000000
  fsubs. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x3FF0000000000000
  #_ REGISTER_OUT f2 0xFFF8000000000000
  #_ REGISTER_OUT f3 0xFFF8000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fsubs_60_GEN:
  #_ REGISTER_IN f1 0x3FF0000000000000
  #_ REGISTER_IN f2 0xFFF4000000000000
  fsubs f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x3FF0000000000000
  #_ REGISTER_OUT f2 0xFFF4000000000000
  #_ REGISTER_OUT f3 0xFFFC000000000000

test_fsubs_60_cr_GEN:
  #_ REGISTER_IN f1 0x3FF0000000000000
  #_ REGISTER_IN f2 0xFFF4000000000000
  fsubs. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x3FF0000000000000
  #_ REGISTER_OUT f2 0xFFF4000000000000
  #_ REGISTER_OUT f3 0xFFFC000000000000
  #_ REGISTER_OUT cr 0x0A000000

test_fsubs_61_GEN:
  #_ REGISTER_IN f1 0xBFF0000000000000
  #_ REGISTER_IN f2 0x0000000000000000
  fsubs f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xBFF0000000000000
  #_ REGISTER_OUT f2 0x0000000000000000
  #_ REGISTER_OUT f3 0xBFF0000000000000

test_fsubs_61_cr_GEN:
  #_ REGISTER_IN f1 0xBFF0000000000000
  #_ REGISTER_IN f2 0x0000000000000000
  fsubs. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xBFF0000000000000
  #_ REGISTER_OUT f2 0x0000000000000000
  #_ REGISTER_OUT f3 0xBFF0000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fsubs_62_GEN:
  #_ REGISTER_IN f1 0xBFF0000000000000
  #_ REGISTER_IN f2 0x8000000000000000
  fsubs f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xBFF0000000000000
  #_ REGISTER_OUT f2 0x8000000000000000
  #_ REGISTER_OUT f3 0xBFF0000000000000

test_fsubs_62_cr_GEN:
  #_ REGISTER_IN f1 0xBFF0000000000000
  #_ REGISTER_IN f2 0x8000000000000000
  fsubs. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xBFF0000000000000
  #_ REGISTER_OUT f2 0x8000000000000000
  #_ REGISTER_OUT f3 0xBFF0000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fsubs_63_GEN:
  #_ REGISTER_IN f1 0xBFF0000000000000
  #_ REGISTER_IN f2 0x0000000000000001
  fsubs f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xBFF0000000000000
  #_ REGISTER_OUT f2 0x0000000000000001
  #_ REGISTER_OUT f3 0x7FF8000000000000

test_fsubs_63_cr_GEN:
  #_ REGISTER_IN f1 0xBFF0000000000000
  #_ REGISTER_IN f2 0x0000000000000001
  fsubs. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xBFF0000000000000
  #_ REGISTER_OUT f2 0x0000000000000001
  #_ REGISTER_OUT f3 0x7FF8000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fsubs_64_GEN:
  #_ REGISTER_IN f1 0xBFF0000000000000
  #_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
  fsubs f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xBFF0000000000000
  #_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
  #_ REGISTER_OUT f3 0x7FF8000000000000

test_fsubs_64_cr_GEN:
  #_ REGISTER_IN f1 0xBFF0000000000000
  #_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
  fsubs. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xBFF0000000000000
  #_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
  #_ REGISTER_OUT f3 0x7FF8000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fsubs_65_GEN:
  #_ REGISTER_IN f1 0xBFF0000000000000
  #_ REGISTER_IN f2 0x3FF0000000000000
  fsubs f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xBFF0000000000000
  #_ REGISTER_OUT f2 0x3FF0000000000000
  #_ REGISTER_OUT f3 0xC000000000000000

test_fsubs_65_cr_GEN:
  #_ REGISTER_IN f1 0xBFF0000000000000
  #_ REGISTER_IN f2 0x3FF0000000000000
  fsubs. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xBFF0000000000000
  #_ REGISTER_OUT f2 0x3FF0000000000000
  #_ REGISTER_OUT f3 0xC000000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fsubs_66_GEN:
  #_ REGISTER_IN f1 0xBFF0000000000000
  #_ REGISTER_IN f2 0xBFF0000000000000
  fsubs f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xBFF0000000000000
  #_ REGISTER_OUT f2 0xBFF0000000000000
  #_ REGISTER_OUT f3 0x0000000000000000

test_fsubs_66_cr_GEN:
  #_ REGISTER_IN f1 0xBFF0000000000000
  #_ REGISTER_IN f2 0xBFF0000000000000
  fsubs. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xBFF0000000000000
  #_ REGISTER_OUT f2 0xBFF0000000000000
  #_ REGISTER_OUT f3 0x0000000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fsubs_67_GEN:
  #_ REGISTER_IN f1 0xBFF0000000000000
  #_ REGISTER_IN f2 0xC1E0000000000000
  fsubs f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xBFF0000000000000
  #_ REGISTER_OUT f2 0xC1E0000000000000
  #_ REGISTER_OUT f3 0x41E0000000000000

test_fsubs_67_cr_GEN:
  #_ REGISTER_IN f1 0xBFF0000000000000
  #_ REGISTER_IN f2 0xC1E0000000000000
  fsubs. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xBFF0000000000000
  #_ REGISTER_OUT f2 0xC1E0000000000000
  #_ REGISTER_OUT f3 0x41E0000000000000
  #_ REGISTER_OUT cr 0x08000000

test_fsubs_68_GEN:
  #_ REGISTER_IN f1 0xBFF0000000000000
  #_ REGISTER_IN f2 0x41DFFFFFFFC00000
  fsubs f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xBFF0000000000000
  #_ REGISTER_OUT f2 0x41DFFFFFFFC00000
  #_ REGISTER_OUT f3 0xC1E0000000000000

test_fsubs_68_cr_GEN:
  #_ REGISTER_IN f1 0xBFF0000000000000
  #_ REGISTER_IN f2 0x41DFFFFFFFC00000
  fsubs. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xBFF0000000000000
  #_ REGISTER_OUT f2 0x41DFFFFFFFC00000
  #_ REGISTER_OUT f3 0xC1E0000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fsubs_69_GEN:
  #_ REGISTER_IN f1 0xBFF0000000000000
  #_ REGISTER_IN f2 0x7FF0000000000000
  fsubs f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xBFF0000000000000
  #_ REGISTER_OUT f2 0x7FF0000000000000
  #_ REGISTER_OUT f3 0xFFF0000000000000

test_fsubs_69_cr_GEN:
  #_ REGISTER_IN f1 0xBFF0000000000000
  #_ REGISTER_IN f2 0x7FF0000000000000
  fsubs. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xBFF0000000000000
  #_ REGISTER_OUT f2 0x7FF0000000000000
  #_ REGISTER_OUT f3 0xFFF0000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fsubs_70_GEN:
  #_ REGISTER_IN f1 0xBFF0000000000000
  #_ REGISTER_IN f2 0xFFF0000000000000
  fsubs f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xBFF0000000000000
  #_ REGISTER_OUT f2 0xFFF0000000000000
  #_ REGISTER_OUT f3 0x7FF0000000000000

test_fsubs_70_cr_GEN:
  #_ REGISTER_IN f1 0xBFF0000000000000
  #_ REGISTER_IN f2 0xFFF0000000000000
  fsubs. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xBFF0000000000000
  #_ REGISTER_OUT f2 0xFFF0000000000000
  #_ REGISTER_OUT f3 0x7FF0000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fsubs_71_GEN:
  #_ REGISTER_IN f1 0xBFF0000000000000
  #_ REGISTER_IN f2 0xFFF8000000000000
  fsubs f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xBFF0000000000000
  #_ REGISTER_OUT f2 0xFFF8000000000000
  #_ REGISTER_OUT f3 0xFFF8000000000000

test_fsubs_71_cr_GEN:
  #_ REGISTER_IN f1 0xBFF0000000000000
  #_ REGISTER_IN f2 0xFFF8000000000000
  fsubs. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xBFF0000000000000
  #_ REGISTER_OUT f2 0xFFF8000000000000
  #_ REGISTER_OUT f3 0xFFF8000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fsubs_72_GEN:
  #_ REGISTER_IN f1 0xBFF0000000000000
  #_ REGISTER_IN f2 0xFFF4000000000000
  fsubs f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xBFF0000000000000
  #_ REGISTER_OUT f2 0xFFF4000000000000
  #_ REGISTER_OUT f3 0xFFFC000000000000

test_fsubs_72_cr_GEN:
  #_ REGISTER_IN f1 0xBFF0000000000000
  #_ REGISTER_IN f2 0xFFF4000000000000
  fsubs. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xBFF0000000000000
  #_ REGISTER_OUT f2 0xFFF4000000000000
  #_ REGISTER_OUT f3 0xFFFC000000000000
  #_ REGISTER_OUT cr 0x0A000000

test_fsubs_73_GEN:
  #_ REGISTER_IN f1 0xC1E0000000000000
  #_ REGISTER_IN f2 0x0000000000000000
  fsubs f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xC1E0000000000000
  #_ REGISTER_OUT f2 0x0000000000000000
  #_ REGISTER_OUT f3 0xC1E0000000000000

test_fsubs_73_cr_GEN:
  #_ REGISTER_IN f1 0xC1E0000000000000
  #_ REGISTER_IN f2 0x0000000000000000
  fsubs. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xC1E0000000000000
  #_ REGISTER_OUT f2 0x0000000000000000
  #_ REGISTER_OUT f3 0xC1E0000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fsubs_74_GEN:
  #_ REGISTER_IN f1 0xC1E0000000000000
  #_ REGISTER_IN f2 0x8000000000000000
  fsubs f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xC1E0000000000000
  #_ REGISTER_OUT f2 0x8000000000000000
  #_ REGISTER_OUT f3 0xC1E0000000000000

test_fsubs_74_cr_GEN:
  #_ REGISTER_IN f1 0xC1E0000000000000
  #_ REGISTER_IN f2 0x8000000000000000
  fsubs. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xC1E0000000000000
  #_ REGISTER_OUT f2 0x8000000000000000
  #_ REGISTER_OUT f3 0xC1E0000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fsubs_75_GEN:
  #_ REGISTER_IN f1 0xC1E0000000000000
  #_ REGISTER_IN f2 0x0000000000000001
  fsubs f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xC1E0000000000000
  #_ REGISTER_OUT f2 0x0000000000000001
  #_ REGISTER_OUT f3 0x7FF8000000000000

test_fsubs_75_cr_GEN:
  #_ REGISTER_IN f1 0xC1E0000000000000
  #_ REGISTER_IN f2 0x0000000000000001
  fsubs. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xC1E0000000000000
  #_ REGISTER_OUT f2 0x0000000000000001
  #_ REGISTER_OUT f3 0x7FF8000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fsubs_76_GEN:
  #_ REGISTER_IN f1 0xC1E0000000000000
  #_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
  fsubs f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xC1E0000000000000
  #_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
  #_ REGISTER_OUT f3 0x7FF8000000000000

test_fsubs_76_cr_GEN:
  #_ REGISTER_IN f1 0xC1E0000000000000
  #_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
  fsubs. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xC1E0000000000000
  #_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
  #_ REGISTER_OUT f3 0x7FF8000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fsubs_77_GEN:
  #_ REGISTER_IN f1 0xC1E0000000000000
  #_ REGISTER_IN f2 0x3FF0000000000000
  fsubs f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xC1E0000000000000
  #_ REGISTER_OUT f2 0x3FF0000000000000
  #_ REGISTER_OUT f3 0xC1E0000000000000

test_fsubs_77_cr_GEN:
  #_ REGISTER_IN f1 0xC1E0000000000000
  #_ REGISTER_IN f2 0x3FF0000000000000
  fsubs. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xC1E0000000000000
  #_ REGISTER_OUT f2 0x3FF0000000000000
  #_ REGISTER_OUT f3 0xC1E0000000000000
  #_ REGISTER_OUT cr 0x08000000

test_fsubs_78_GEN:
  #_ REGISTER_IN f1 0xC1E0000000000000
  #_ REGISTER_IN f2 0xBFF0000000000000
  fsubs f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xC1E0000000000000
  #_ REGISTER_OUT f2 0xBFF0000000000000
  #_ REGISTER_OUT f3 0xC1E0000000000000

test_fsubs_78_cr_GEN:
  #_ REGISTER_IN f1 0xC1E0000000000000
  #_ REGISTER_IN f2 0xBFF0000000000000
  fsubs. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xC1E0000000000000
  #_ REGISTER_OUT f2 0xBFF0000000000000
  #_ REGISTER_OUT f3 0xC1E0000000000000
  #_ REGISTER_OUT cr 0x08000000

test_fsubs_79_GEN:
  #_ REGISTER_IN f1 0xC1E0000000000000
  #_ REGISTER_IN f2 0xC1E0000000000000
  fsubs f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xC1E0000000000000
  #_ REGISTER_OUT f2 0xC1E0000000000000
  #_ REGISTER_OUT f3 0x0000000000000000

test_fsubs_79_cr_GEN:
  #_ REGISTER_IN f1 0xC1E0000000000000
  #_ REGISTER_IN f2 0xC1E0000000000000
  fsubs. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xC1E0000000000000
  #_ REGISTER_OUT f2 0xC1E0000000000000
  #_ REGISTER_OUT f3 0x0000000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fsubs_80_GEN:
  #_ REGISTER_IN f1 0xC1E0000000000000
  #_ REGISTER_IN f2 0x41DFFFFFFFC00000
  fsubs f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xC1E0000000000000
  #_ REGISTER_OUT f2 0x41DFFFFFFFC00000
  #_ REGISTER_OUT f3 0xC1F0000000000000

test_fsubs_80_cr_GEN:
  #_ REGISTER_IN f1 0xC1E0000000000000
  #_ REGISTER_IN f2 0x41DFFFFFFFC00000
  fsubs. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xC1E0000000000000
  #_ REGISTER_OUT f2 0x41DFFFFFFFC00000
  #_ REGISTER_OUT f3 0xC1F0000000000000
  #_ REGISTER_OUT cr 0x08000000

test_fsubs_81_GEN:
  #_ REGISTER_IN f1 0xC1E0000000000000
  #_ REGISTER_IN f2 0x7FF0000000000000
  fsubs f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xC1E0000000000000
  #_ REGISTER_OUT f2 0x7FF0000000000000
  #_ REGISTER_OUT f3 0xFFF0000000000000

test_fsubs_81_cr_GEN:
  #_ REGISTER_IN f1 0xC1E0000000000000
  #_ REGISTER_IN f2 0x7FF0000000000000
  fsubs. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xC1E0000000000000
  #_ REGISTER_OUT f2 0x7FF0000000000000
  #_ REGISTER_OUT f3 0xFFF0000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fsubs_82_GEN:
  #_ REGISTER_IN f1 0xC1E0000000000000
  #_ REGISTER_IN f2 0xFFF0000000000000
  fsubs f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xC1E0000000000000
  #_ REGISTER_OUT f2 0xFFF0000000000000
  #_ REGISTER_OUT f3 0x7FF0000000000000

test_fsubs_82_cr_GEN:
  #_ REGISTER_IN f1 0xC1E0000000000000
  #_ REGISTER_IN f2 0xFFF0000000000000
  fsubs. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xC1E0000000000000
  #_ REGISTER_OUT f2 0xFFF0000000000000
  #_ REGISTER_OUT f3 0x7FF0000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fsubs_83_GEN:
  #_ REGISTER_IN f1 0xC1E0000000000000
  #_ REGISTER_IN f2 0xFFF8000000000000
  fsubs f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xC1E0000000000000
  #_ REGISTER_OUT f2 0xFFF8000000000000
  #_ REGISTER_OUT f3 0xFFF8000000000000

test_fsubs_83_cr_GEN:
  #_ REGISTER_IN f1 0xC1E0000000000000
  #_ REGISTER_IN f2 0xFFF8000000000000
  fsubs. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xC1E0000000000000
  #_ REGISTER_OUT f2 0xFFF8000000000000
  #_ REGISTER_OUT f3 0xFFF8000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fsubs_84_GEN:
  #_ REGISTER_IN f1 0xC1E0000000000000
  #_ REGISTER_IN f2 0xFFF4000000000000
  fsubs f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xC1E0000000000000
  #_ REGISTER_OUT f2 0xFFF4000000000000
  #_ REGISTER_OUT f3 0xFFFC000000000000

test_fsubs_84_cr_GEN:
  #_ REGISTER_IN f1 0xC1E0000000000000
  #_ REGISTER_IN f2 0xFFF4000000000000
  fsubs. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xC1E0000000000000
  #_ REGISTER_OUT f2 0xFFF4000000000000
  #_ REGISTER_OUT f3 0xFFFC000000000000
  #_ REGISTER_OUT cr 0x0A000000

test_fsubs_85_GEN:
  #_ REGISTER_IN f1 0x41DFFFFFFFC00000
  #_ REGISTER_IN f2 0x0000000000000000
  fsubs f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x41DFFFFFFFC00000
  #_ REGISTER_OUT f2 0x0000000000000000
  #_ REGISTER_OUT f3 0x41E0000000000000

test_fsubs_85_cr_GEN:
  #_ REGISTER_IN f1 0x41DFFFFFFFC00000
  #_ REGISTER_IN f2 0x0000000000000000
  fsubs. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x41DFFFFFFFC00000
  #_ REGISTER_OUT f2 0x0000000000000000
  #_ REGISTER_OUT f3 0x41E0000000000000
  #_ REGISTER_OUT cr 0x08000000

test_fsubs_86_GEN:
  #_ REGISTER_IN f1 0x41DFFFFFFFC00000
  #_ REGISTER_IN f2 0x8000000000000000
  fsubs f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x41DFFFFFFFC00000
  #_ REGISTER_OUT f2 0x8000000000000000
  #_ REGISTER_OUT f3 0x41E0000000000000

test_fsubs_86_cr_GEN:
  #_ REGISTER_IN f1 0x41DFFFFFFFC00000
  #_ REGISTER_IN f2 0x8000000000000000
  fsubs. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x41DFFFFFFFC00000
  #_ REGISTER_OUT f2 0x8000000000000000
  #_ REGISTER_OUT f3 0x41E0000000000000
  #_ REGISTER_OUT cr 0x08000000

test_fsubs_87_GEN:
  #_ REGISTER_IN f1 0x41DFFFFFFFC00000
  #_ REGISTER_IN f2 0x0000000000000001
  fsubs f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x41DFFFFFFFC00000
  #_ REGISTER_OUT f2 0x0000000000000001
  #_ REGISTER_OUT f3 0x7FF8000000000000

test_fsubs_87_cr_GEN:
  #_ REGISTER_IN f1 0x41DFFFFFFFC00000
  #_ REGISTER_IN f2 0x0000000000000001
  fsubs. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x41DFFFFFFFC00000
  #_ REGISTER_OUT f2 0x0000000000000001
  #_ REGISTER_OUT f3 0x7FF8000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fsubs_88_GEN:
  #_ REGISTER_IN f1 0x41DFFFFFFFC00000
  #_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
  fsubs f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x41DFFFFFFFC00000
  #_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
  #_ REGISTER_OUT f3 0x7FF8000000000000

test_fsubs_88_cr_GEN:
  #_ REGISTER_IN f1 0x41DFFFFFFFC00000
  #_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
  fsubs. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x41DFFFFFFFC00000
  #_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
  #_ REGISTER_OUT f3 0x7FF8000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fsubs_89_GEN:
  #_ REGISTER_IN f1 0x41DFFFFFFFC00000
  #_ REGISTER_IN f2 0x3FF0000000000000
  fsubs f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x41DFFFFFFFC00000
  #_ REGISTER_OUT f2 0x3FF0000000000000
  #_ REGISTER_OUT f3 0x41E0000000000000

test_fsubs_89_cr_GEN:
  #_ REGISTER_IN f1 0x41DFFFFFFFC00000
  #_ REGISTER_IN f2 0x3FF0000000000000
  fsubs. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x41DFFFFFFFC00000
  #_ REGISTER_OUT f2 0x3FF0000000000000
  #_ REGISTER_OUT f3 0x41E0000000000000
  #_ REGISTER_OUT cr 0x08000000

test_fsubs_90_GEN:
  #_ REGISTER_IN f1 0x41DFFFFFFFC00000
  #_ REGISTER_IN f2 0xBFF0000000000000
  fsubs f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x41DFFFFFFFC00000
  #_ REGISTER_OUT f2 0xBFF0000000000000
  #_ REGISTER_OUT f3 0x41E0000000000000

test_fsubs_90_cr_GEN:
  #_ REGISTER_IN f1 0x41DFFFFFFFC00000
  #_ REGISTER_IN f2 0xBFF0000000000000
  fsubs. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x41DFFFFFFFC00000
  #_ REGISTER_OUT f2 0xBFF0000000000000
  #_ REGISTER_OUT f3 0x41E0000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fsubs_91_GEN:
  #_ REGISTER_IN f1 0x41DFFFFFFFC00000
  #_ REGISTER_IN f2 0xC1E0000000000000
  fsubs f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x41DFFFFFFFC00000
  #_ REGISTER_OUT f2 0xC1E0000000000000
  #_ REGISTER_OUT f3 0x41F0000000000000

test_fsubs_91_cr_GEN:
  #_ REGISTER_IN f1 0x41DFFFFFFFC00000
  #_ REGISTER_IN f2 0xC1E0000000000000
  fsubs. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x41DFFFFFFFC00000
  #_ REGISTER_OUT f2 0xC1E0000000000000
  #_ REGISTER_OUT f3 0x41F0000000000000
  #_ REGISTER_OUT cr 0x08000000

test_fsubs_92_GEN:
  #_ REGISTER_IN f1 0x41DFFFFFFFC00000
  #_ REGISTER_IN f2 0x41DFFFFFFFC00000
  fsubs f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x41DFFFFFFFC00000
  #_ REGISTER_OUT f2 0x41DFFFFFFFC00000
  #_ REGISTER_OUT f3 0x0000000000000000

test_fsubs_92_cr_GEN:
  #_ REGISTER_IN f1 0x41DFFFFFFFC00000
  #_ REGISTER_IN f2 0x41DFFFFFFFC00000
  fsubs. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x41DFFFFFFFC00000
  #_ REGISTER_OUT f2 0x41DFFFFFFFC00000
  #_ REGISTER_OUT f3 0x0000000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fsubs_93_GEN:
  #_ REGISTER_IN f1 0x41DFFFFFFFC00000
  #_ REGISTER_IN f2 0x7FF0000000000000
  fsubs f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x41DFFFFFFFC00000
  #_ REGISTER_OUT f2 0x7FF0000000000000
  #_ REGISTER_OUT f3 0xFFF0000000000000

test_fsubs_93_cr_GEN:
  #_ REGISTER_IN f1 0x41DFFFFFFFC00000
  #_ REGISTER_IN f2 0x7FF0000000000000
  fsubs. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x41DFFFFFFFC00000
  #_ REGISTER_OUT f2 0x7FF0000000000000
  #_ REGISTER_OUT f3 0xFFF0000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fsubs_94_GEN:
  #_ REGISTER_IN f1 0x41DFFFFFFFC00000
  #_ REGISTER_IN f2 0xFFF0000000000000
  fsubs f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x41DFFFFFFFC00000
  #_ REGISTER_OUT f2 0xFFF0000000000000
  #_ REGISTER_OUT f3 0x7FF0000000000000

test_fsubs_94_cr_GEN:
  #_ REGISTER_IN f1 0x41DFFFFFFFC00000
  #_ REGISTER_IN f2 0xFFF0000000000000
  fsubs. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x41DFFFFFFFC00000
  #_ REGISTER_OUT f2 0xFFF0000000000000
  #_ REGISTER_OUT f3 0x7FF0000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fsubs_95_GEN:
  #_ REGISTER_IN f1 0x41DFFFFFFFC00000
  #_ REGISTER_IN f2 0xFFF8000000000000
  fsubs f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x41DFFFFFFFC00000
  #_ REGISTER_OUT f2 0xFFF8000000000000
  #_ REGISTER_OUT f3 0xFFF8000000000000

test_fsubs_95_cr_GEN:
  #_ REGISTER_IN f1 0x41DFFFFFFFC00000
  #_ REGISTER_IN f2 0xFFF8000000000000
  fsubs. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x41DFFFFFFFC00000
  #_ REGISTER_OUT f2 0xFFF8000000000000
  #_ REGISTER_OUT f3 0xFFF8000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fsubs_96_GEN:
  #_ REGISTER_IN f1 0x41DFFFFFFFC00000
  #_ REGISTER_IN f2 0xFFF4000000000000
  fsubs f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x41DFFFFFFFC00000
  #_ REGISTER_OUT f2 0xFFF4000000000000
  #_ REGISTER_OUT f3 0xFFFC000000000000

test_fsubs_96_cr_GEN:
  #_ REGISTER_IN f1 0x41DFFFFFFFC00000
  #_ REGISTER_IN f2 0xFFF4000000000000
  fsubs. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x41DFFFFFFFC00000
  #_ REGISTER_OUT f2 0xFFF4000000000000
  #_ REGISTER_OUT f3 0xFFFC000000000000
  #_ REGISTER_OUT cr 0x0A000000

test_fsubs_97_GEN:
  #_ REGISTER_IN f1 0x7FF0000000000000
  #_ REGISTER_IN f2 0x0000000000000000
  fsubs f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x7FF0000000000000
  #_ REGISTER_OUT f2 0x0000000000000000
  #_ REGISTER_OUT f3 0x7FF0000000000000

test_fsubs_97_cr_GEN:
  #_ REGISTER_IN f1 0x7FF0000000000000
  #_ REGISTER_IN f2 0x0000000000000000
  fsubs. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x7FF0000000000000
  #_ REGISTER_OUT f2 0x0000000000000000
  #_ REGISTER_OUT f3 0x7FF0000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fsubs_98_GEN:
  #_ REGISTER_IN f1 0x7FF0000000000000
  #_ REGISTER_IN f2 0x8000000000000000
  fsubs f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x7FF0000000000000
  #_ REGISTER_OUT f2 0x8000000000000000
  #_ REGISTER_OUT f3 0x7FF0000000000000

test_fsubs_98_cr_GEN:
  #_ REGISTER_IN f1 0x7FF0000000000000
  #_ REGISTER_IN f2 0x8000000000000000
  fsubs. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x7FF0000000000000
  #_ REGISTER_OUT f2 0x8000000000000000
  #_ REGISTER_OUT f3 0x7FF0000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fsubs_99_GEN:
  #_ REGISTER_IN f1 0x7FF0000000000000
  #_ REGISTER_IN f2 0x0000000000000001
  fsubs f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x7FF0000000000000
  #_ REGISTER_OUT f2 0x0000000000000001
  #_ REGISTER_OUT f3 0x7FF0000000000000

test_fsubs_99_cr_GEN:
  #_ REGISTER_IN f1 0x7FF0000000000000
  #_ REGISTER_IN f2 0x0000000000000001
  fsubs. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x7FF0000000000000
  #_ REGISTER_OUT f2 0x0000000000000001
  #_ REGISTER_OUT f3 0x7FF0000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fsubs_100_GEN:
  #_ REGISTER_IN f1 0x7FF0000000000000
  #_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
  fsubs f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x7FF0000000000000
  #_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
  #_ REGISTER_OUT f3 0x7FF0000000000000

test_fsubs_100_cr_GEN:
  #_ REGISTER_IN f1 0x7FF0000000000000
  #_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
  fsubs. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x7FF0000000000000
  #_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
  #_ REGISTER_OUT f3 0x7FF0000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fsubs_101_GEN:
  #_ REGISTER_IN f1 0x7FF0000000000000
  #_ REGISTER_IN f2 0x3FF0000000000000
  fsubs f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x7FF0000000000000
  #_ REGISTER_OUT f2 0x3FF0000000000000
  #_ REGISTER_OUT f3 0x7FF0000000000000

test_fsubs_101_cr_GEN:
  #_ REGISTER_IN f1 0x7FF0000000000000
  #_ REGISTER_IN f2 0x3FF0000000000000
  fsubs. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x7FF0000000000000
  #_ REGISTER_OUT f2 0x3FF0000000000000
  #_ REGISTER_OUT f3 0x7FF0000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fsubs_102_GEN:
  #_ REGISTER_IN f1 0x7FF0000000000000
  #_ REGISTER_IN f2 0xBFF0000000000000
  fsubs f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x7FF0000000000000
  #_ REGISTER_OUT f2 0xBFF0000000000000
  #_ REGISTER_OUT f3 0x7FF0000000000000

test_fsubs_102_cr_GEN:
  #_ REGISTER_IN f1 0x7FF0000000000000
  #_ REGISTER_IN f2 0xBFF0000000000000
  fsubs. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x7FF0000000000000
  #_ REGISTER_OUT f2 0xBFF0000000000000
  #_ REGISTER_OUT f3 0x7FF0000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fsubs_103_GEN:
  #_ REGISTER_IN f1 0x7FF0000000000000
  #_ REGISTER_IN f2 0xC1E0000000000000
  fsubs f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x7FF0000000000000
  #_ REGISTER_OUT f2 0xC1E0000000000000
  #_ REGISTER_OUT f3 0x7FF0000000000000

test_fsubs_103_cr_GEN:
  #_ REGISTER_IN f1 0x7FF0000000000000
  #_ REGISTER_IN f2 0xC1E0000000000000
  fsubs. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x7FF0000000000000
  #_ REGISTER_OUT f2 0xC1E0000000000000
  #_ REGISTER_OUT f3 0x7FF0000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fsubs_104_GEN:
  #_ REGISTER_IN f1 0x7FF0000000000000
  #_ REGISTER_IN f2 0x41DFFFFFFFC00000
  fsubs f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x7FF0000000000000
  #_ REGISTER_OUT f2 0x41DFFFFFFFC00000
  #_ REGISTER_OUT f3 0x7FF0000000000000

test_fsubs_104_cr_GEN:
  #_ REGISTER_IN f1 0x7FF0000000000000
  #_ REGISTER_IN f2 0x41DFFFFFFFC00000
  fsubs. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x7FF0000000000000
  #_ REGISTER_OUT f2 0x41DFFFFFFFC00000
  #_ REGISTER_OUT f3 0x7FF0000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fsubs_105_GEN:
  #_ REGISTER_IN f1 0x7FF0000000000000
  #_ REGISTER_IN f2 0x7FF0000000000000
  fsubs f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x7FF0000000000000
  #_ REGISTER_OUT f2 0x7FF0000000000000
  #_ REGISTER_OUT f3 0x7FF8000000000000

test_fsubs_105_cr_GEN:
  #_ REGISTER_IN f1 0x7FF0000000000000
  #_ REGISTER_IN f2 0x7FF0000000000000
  fsubs. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x7FF0000000000000
  #_ REGISTER_OUT f2 0x7FF0000000000000
  #_ REGISTER_OUT f3 0x7FF8000000000000
  #_ REGISTER_OUT cr 0x0A000000

test_fsubs_106_GEN:
  #_ REGISTER_IN f1 0x7FF0000000000000
  #_ REGISTER_IN f2 0xFFF0000000000000
  fsubs f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x7FF0000000000000
  #_ REGISTER_OUT f2 0xFFF0000000000000
  #_ REGISTER_OUT f3 0x7FF0000000000000

test_fsubs_106_cr_GEN:
  #_ REGISTER_IN f1 0x7FF0000000000000
  #_ REGISTER_IN f2 0xFFF0000000000000
  fsubs. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x7FF0000000000000
  #_ REGISTER_OUT f2 0xFFF0000000000000
  #_ REGISTER_OUT f3 0x7FF0000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fsubs_107_GEN:
  #_ REGISTER_IN f1 0x7FF0000000000000
  #_ REGISTER_IN f2 0xFFF8000000000000
  fsubs f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x7FF0000000000000
  #_ REGISTER_OUT f2 0xFFF8000000000000
  #_ REGISTER_OUT f3 0xFFF8000000000000

test_fsubs_107_cr_GEN:
  #_ REGISTER_IN f1 0x7FF0000000000000
  #_ REGISTER_IN f2 0xFFF8000000000000
  fsubs. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x7FF0000000000000
  #_ REGISTER_OUT f2 0xFFF8000000000000
  #_ REGISTER_OUT f3 0xFFF8000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fsubs_108_GEN:
  #_ REGISTER_IN f1 0x7FF0000000000000
  #_ REGISTER_IN f2 0xFFF4000000000000
  fsubs f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x7FF0000000000000
  #_ REGISTER_OUT f2 0xFFF4000000000000
  #_ REGISTER_OUT f3 0xFFFC000000000000

test_fsubs_108_cr_GEN:
  #_ REGISTER_IN f1 0x7FF0000000000000
  #_ REGISTER_IN f2 0xFFF4000000000000
  fsubs. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x7FF0000000000000
  #_ REGISTER_OUT f2 0xFFF4000000000000
  #_ REGISTER_OUT f3 0xFFFC000000000000
  #_ REGISTER_OUT cr 0x0A000000

test_fsubs_109_GEN:
  #_ REGISTER_IN f1 0xFFF0000000000000
  #_ REGISTER_IN f2 0x0000000000000000
  fsubs f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF0000000000000
  #_ REGISTER_OUT f2 0x0000000000000000
  #_ REGISTER_OUT f3 0xFFF0000000000000

test_fsubs_109_cr_GEN:
  #_ REGISTER_IN f1 0xFFF0000000000000
  #_ REGISTER_IN f2 0x0000000000000000
  fsubs. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF0000000000000
  #_ REGISTER_OUT f2 0x0000000000000000
  #_ REGISTER_OUT f3 0xFFF0000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fsubs_110_GEN:
  #_ REGISTER_IN f1 0xFFF0000000000000
  #_ REGISTER_IN f2 0x8000000000000000
  fsubs f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF0000000000000
  #_ REGISTER_OUT f2 0x8000000000000000
  #_ REGISTER_OUT f3 0xFFF0000000000000

test_fsubs_110_cr_GEN:
  #_ REGISTER_IN f1 0xFFF0000000000000
  #_ REGISTER_IN f2 0x8000000000000000
  fsubs. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF0000000000000
  #_ REGISTER_OUT f2 0x8000000000000000
  #_ REGISTER_OUT f3 0xFFF0000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fsubs_111_GEN:
  #_ REGISTER_IN f1 0xFFF0000000000000
  #_ REGISTER_IN f2 0x0000000000000001
  fsubs f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF0000000000000
  #_ REGISTER_OUT f2 0x0000000000000001
  #_ REGISTER_OUT f3 0xFFF0000000000000

test_fsubs_111_cr_GEN:
  #_ REGISTER_IN f1 0xFFF0000000000000
  #_ REGISTER_IN f2 0x0000000000000001
  fsubs. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF0000000000000
  #_ REGISTER_OUT f2 0x0000000000000001
  #_ REGISTER_OUT f3 0xFFF0000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fsubs_112_GEN:
  #_ REGISTER_IN f1 0xFFF0000000000000
  #_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
  fsubs f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF0000000000000
  #_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
  #_ REGISTER_OUT f3 0xFFF0000000000000

test_fsubs_112_cr_GEN:
  #_ REGISTER_IN f1 0xFFF0000000000000
  #_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
  fsubs. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF0000000000000
  #_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
  #_ REGISTER_OUT f3 0xFFF0000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fsubs_113_GEN:
  #_ REGISTER_IN f1 0xFFF0000000000000
  #_ REGISTER_IN f2 0x3FF0000000000000
  fsubs f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF0000000000000
  #_ REGISTER_OUT f2 0x3FF0000000000000
  #_ REGISTER_OUT f3 0xFFF0000000000000

test_fsubs_113_cr_GEN:
  #_ REGISTER_IN f1 0xFFF0000000000000
  #_ REGISTER_IN f2 0x3FF0000000000000
  fsubs. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF0000000000000
  #_ REGISTER_OUT f2 0x3FF0000000000000
  #_ REGISTER_OUT f3 0xFFF0000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fsubs_114_GEN:
  #_ REGISTER_IN f1 0xFFF0000000000000
  #_ REGISTER_IN f2 0xBFF0000000000000
  fsubs f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF0000000000000
  #_ REGISTER_OUT f2 0xBFF0000000000000
  #_ REGISTER_OUT f3 0xFFF0000000000000

test_fsubs_114_cr_GEN:
  #_ REGISTER_IN f1 0xFFF0000000000000
  #_ REGISTER_IN f2 0xBFF0000000000000
  fsubs. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF0000000000000
  #_ REGISTER_OUT f2 0xBFF0000000000000
  #_ REGISTER_OUT f3 0xFFF0000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fsubs_115_GEN:
  #_ REGISTER_IN f1 0xFFF0000000000000
  #_ REGISTER_IN f2 0xC1E0000000000000
  fsubs f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF0000000000000
  #_ REGISTER_OUT f2 0xC1E0000000000000
  #_ REGISTER_OUT f3 0xFFF0000000000000

test_fsubs_115_cr_GEN:
  #_ REGISTER_IN f1 0xFFF0000000000000
  #_ REGISTER_IN f2 0xC1E0000000000000
  fsubs. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF0000000000000
  #_ REGISTER_OUT f2 0xC1E0000000000000
  #_ REGISTER_OUT f3 0xFFF0000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fsubs_116_GEN:
  #_ REGISTER_IN f1 0xFFF0000000000000
  #_ REGISTER_IN f2 0x41DFFFFFFFC00000
  fsubs f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF0000000000000
  #_ REGISTER_OUT f2 0x41DFFFFFFFC00000
  #_ REGISTER_OUT f3 0xFFF0000000000000

test_fsubs_116_cr_GEN:
  #_ REGISTER_IN f1 0xFFF0000000000000
  #_ REGISTER_IN f2 0x41DFFFFFFFC00000
  fsubs. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF0000000000000
  #_ REGISTER_OUT f2 0x41DFFFFFFFC00000
  #_ REGISTER_OUT f3 0xFFF0000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fsubs_117_GEN:
  #_ REGISTER_IN f1 0xFFF0000000000000
  #_ REGISTER_IN f2 0x7FF0000000000000
  fsubs f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF0000000000000
  #_ REGISTER_OUT f2 0x7FF0000000000000
  #_ REGISTER_OUT f3 0xFFF0000000000000

test_fsubs_117_cr_GEN:
  #_ REGISTER_IN f1 0xFFF0000000000000
  #_ REGISTER_IN f2 0x7FF0000000000000
  fsubs. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF0000000000000
  #_ REGISTER_OUT f2 0x7FF0000000000000
  #_ REGISTER_OUT f3 0xFFF0000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fsubs_118_GEN:
  #_ REGISTER_IN f1 0xFFF0000000000000
  #_ REGISTER_IN f2 0xFFF0000000000000
  fsubs f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF0000000000000
  #_ REGISTER_OUT f2 0xFFF0000000000000
  #_ REGISTER_OUT f3 0x7FF8000000000000

test_fsubs_118_cr_GEN:
  #_ REGISTER_IN f1 0xFFF0000000000000
  #_ REGISTER_IN f2 0xFFF0000000000000
  fsubs. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF0000000000000
  #_ REGISTER_OUT f2 0xFFF0000000000000
  #_ REGISTER_OUT f3 0x7FF8000000000000
  #_ REGISTER_OUT cr 0x0A000000

test_fsubs_119_GEN:
  #_ REGISTER_IN f1 0xFFF0000000000000
  #_ REGISTER_IN f2 0xFFF8000000000000
  fsubs f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF0000000000000
  #_ REGISTER_OUT f2 0xFFF8000000000000
  #_ REGISTER_OUT f3 0xFFF8000000000000

test_fsubs_119_cr_GEN:
  #_ REGISTER_IN f1 0xFFF0000000000000
  #_ REGISTER_IN f2 0xFFF8000000000000
  fsubs. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF0000000000000
  #_ REGISTER_OUT f2 0xFFF8000000000000
  #_ REGISTER_OUT f3 0xFFF8000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fsubs_120_GEN:
  #_ REGISTER_IN f1 0xFFF0000000000000
  #_ REGISTER_IN f2 0xFFF4000000000000
  fsubs f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF0000000000000
  #_ REGISTER_OUT f2 0xFFF4000000000000
  #_ REGISTER_OUT f3 0xFFFC000000000000

test_fsubs_120_cr_GEN:
  #_ REGISTER_IN f1 0xFFF0000000000000
  #_ REGISTER_IN f2 0xFFF4000000000000
  fsubs. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF0000000000000
  #_ REGISTER_OUT f2 0xFFF4000000000000
  #_ REGISTER_OUT f3 0xFFFC000000000000
  #_ REGISTER_OUT cr 0x0A000000

test_fsubs_121_GEN:
  #_ REGISTER_IN f1 0xFFF8000000000000
  #_ REGISTER_IN f2 0x0000000000000000
  fsubs f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF8000000000000
  #_ REGISTER_OUT f2 0x0000000000000000
  #_ REGISTER_OUT f3 0xFFF8000000000000

test_fsubs_121_cr_GEN:
  #_ REGISTER_IN f1 0xFFF8000000000000
  #_ REGISTER_IN f2 0x0000000000000000
  fsubs. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF8000000000000
  #_ REGISTER_OUT f2 0x0000000000000000
  #_ REGISTER_OUT f3 0xFFF8000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fsubs_122_GEN:
  #_ REGISTER_IN f1 0xFFF8000000000000
  #_ REGISTER_IN f2 0x8000000000000000
  fsubs f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF8000000000000
  #_ REGISTER_OUT f2 0x8000000000000000
  #_ REGISTER_OUT f3 0xFFF8000000000000

test_fsubs_122_cr_GEN:
  #_ REGISTER_IN f1 0xFFF8000000000000
  #_ REGISTER_IN f2 0x8000000000000000
  fsubs. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF8000000000000
  #_ REGISTER_OUT f2 0x8000000000000000
  #_ REGISTER_OUT f3 0xFFF8000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fsubs_123_GEN:
  #_ REGISTER_IN f1 0xFFF8000000000000
  #_ REGISTER_IN f2 0x0000000000000001
  fsubs f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF8000000000000
  #_ REGISTER_OUT f2 0x0000000000000001
  #_ REGISTER_OUT f3 0xFFF8000000000000

test_fsubs_123_cr_GEN:
  #_ REGISTER_IN f1 0xFFF8000000000000
  #_ REGISTER_IN f2 0x0000000000000001
  fsubs. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF8000000000000
  #_ REGISTER_OUT f2 0x0000000000000001
  #_ REGISTER_OUT f3 0xFFF8000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fsubs_124_GEN:
  #_ REGISTER_IN f1 0xFFF8000000000000
  #_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
  fsubs f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF8000000000000
  #_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
  #_ REGISTER_OUT f3 0xFFF8000000000000

test_fsubs_124_cr_GEN:
  #_ REGISTER_IN f1 0xFFF8000000000000
  #_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
  fsubs. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF8000000000000
  #_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
  #_ REGISTER_OUT f3 0xFFF8000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fsubs_125_GEN:
  #_ REGISTER_IN f1 0xFFF8000000000000
  #_ REGISTER_IN f2 0x3FF0000000000000
  fsubs f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF8000000000000
  #_ REGISTER_OUT f2 0x3FF0000000000000
  #_ REGISTER_OUT f3 0xFFF8000000000000

test_fsubs_125_cr_GEN:
  #_ REGISTER_IN f1 0xFFF8000000000000
  #_ REGISTER_IN f2 0x3FF0000000000000
  fsubs. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF8000000000000
  #_ REGISTER_OUT f2 0x3FF0000000000000
  #_ REGISTER_OUT f3 0xFFF8000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fsubs_126_GEN:
  #_ REGISTER_IN f1 0xFFF8000000000000
  #_ REGISTER_IN f2 0xBFF0000000000000
  fsubs f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF8000000000000
  #_ REGISTER_OUT f2 0xBFF0000000000000
  #_ REGISTER_OUT f3 0xFFF8000000000000

test_fsubs_126_cr_GEN:
  #_ REGISTER_IN f1 0xFFF8000000000000
  #_ REGISTER_IN f2 0xBFF0000000000000
  fsubs. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF8000000000000
  #_ REGISTER_OUT f2 0xBFF0000000000000
  #_ REGISTER_OUT f3 0xFFF8000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fsubs_127_GEN:
  #_ REGISTER_IN f1 0xFFF8000000000000
  #_ REGISTER_IN f2 0xC1E0000000000000
  fsubs f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF8000000000000
  #_ REGISTER_OUT f2 0xC1E0000000000000
  #_ REGISTER_OUT f3 0xFFF8000000000000

test_fsubs_127_cr_GEN:
  #_ REGISTER_IN f1 0xFFF8000000000000
  #_ REGISTER_IN f2 0xC1E0000000000000
  fsubs. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF8000000000000
  #_ REGISTER_OUT f2 0xC1E0000000000000
  #_ REGISTER_OUT f3 0xFFF8000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fsubs_128_GEN:
  #_ REGISTER_IN f1 0xFFF8000000000000
  #_ REGISTER_IN f2 0x41DFFFFFFFC00000
  fsubs f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF8000000000000
  #_ REGISTER_OUT f2 0x41DFFFFFFFC00000
  #_ REGISTER_OUT f3 0xFFF8000000000000

test_fsubs_128_cr_GEN:
  #_ REGISTER_IN f1 0xFFF8000000000000
  #_ REGISTER_IN f2 0x41DFFFFFFFC00000
  fsubs. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF8000000000000
  #_ REGISTER_OUT f2 0x41DFFFFFFFC00000
  #_ REGISTER_OUT f3 0xFFF8000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fsubs_129_GEN:
  #_ REGISTER_IN f1 0xFFF8000000000000
  #_ REGISTER_IN f2 0x7FF0000000000000
  fsubs f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF8000000000000
  #_ REGISTER_OUT f2 0x7FF0000000000000
  #_ REGISTER_OUT f3 0xFFF8000000000000

test_fsubs_129_cr_GEN:
  #_ REGISTER_IN f1 0xFFF8000000000000
  #_ REGISTER_IN f2 0x7FF0000000000000
  fsubs. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF8000000000000
  #_ REGISTER_OUT f2 0x7FF0000000000000
  #_ REGISTER_OUT f3 0xFFF8000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fsubs_130_GEN:
  #_ REGISTER_IN f1 0xFFF8000000000000
  #_ REGISTER_IN f2 0xFFF0000000000000
  fsubs f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF8000000000000
  #_ REGISTER_OUT f2 0xFFF0000000000000
  #_ REGISTER_OUT f3 0xFFF8000000000000

test_fsubs_130_cr_GEN:
  #_ REGISTER_IN f1 0xFFF8000000000000
  #_ REGISTER_IN f2 0xFFF0000000000000
  fsubs. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF8000000000000
  #_ REGISTER_OUT f2 0xFFF0000000000000
  #_ REGISTER_OUT f3 0xFFF8000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fsubs_131_GEN:
  #_ REGISTER_IN f1 0xFFF8000000000000
  #_ REGISTER_IN f2 0xFFF8000000000000
  fsubs f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF8000000000000
  #_ REGISTER_OUT f2 0xFFF8000000000000
  #_ REGISTER_OUT f3 0xFFF8000000000000

test_fsubs_131_cr_GEN:
  #_ REGISTER_IN f1 0xFFF8000000000000
  #_ REGISTER_IN f2 0xFFF8000000000000
  fsubs. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF8000000000000
  #_ REGISTER_OUT f2 0xFFF8000000000000
  #_ REGISTER_OUT f3 0xFFF8000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fsubs_132_GEN:
  #_ REGISTER_IN f1 0xFFF8000000000000
  #_ REGISTER_IN f2 0xFFF4000000000000
  fsubs f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF8000000000000
  #_ REGISTER_OUT f2 0xFFF4000000000000
  #_ REGISTER_OUT f3 0xFFF8000000000000

test_fsubs_132_cr_GEN:
  #_ REGISTER_IN f1 0xFFF8000000000000
  #_ REGISTER_IN f2 0xFFF4000000000000
  fsubs. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF8000000000000
  #_ REGISTER_OUT f2 0xFFF4000000000000
  #_ REGISTER_OUT f3 0xFFF8000000000000
  #_ REGISTER_OUT cr 0x0A000000

test_fsubs_133_GEN:
  #_ REGISTER_IN f1 0xFFF4000000000000
  #_ REGISTER_IN f2 0x0000000000000000
  fsubs f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF4000000000000
  #_ REGISTER_OUT f2 0x0000000000000000
  #_ REGISTER_OUT f3 0xFFFC000000000000

test_fsubs_133_cr_GEN:
  #_ REGISTER_IN f1 0xFFF4000000000000
  #_ REGISTER_IN f2 0x0000000000000000
  fsubs. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF4000000000000
  #_ REGISTER_OUT f2 0x0000000000000000
  #_ REGISTER_OUT f3 0xFFFC000000000000
  #_ REGISTER_OUT cr 0x0A000000

test_fsubs_134_GEN:
  #_ REGISTER_IN f1 0xFFF4000000000000
  #_ REGISTER_IN f2 0x8000000000000000
  fsubs f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF4000000000000
  #_ REGISTER_OUT f2 0x8000000000000000
  #_ REGISTER_OUT f3 0xFFFC000000000000

test_fsubs_134_cr_GEN:
  #_ REGISTER_IN f1 0xFFF4000000000000
  #_ REGISTER_IN f2 0x8000000000000000
  fsubs. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF4000000000000
  #_ REGISTER_OUT f2 0x8000000000000000
  #_ REGISTER_OUT f3 0xFFFC000000000000
  #_ REGISTER_OUT cr 0x0A000000

test_fsubs_135_GEN:
  #_ REGISTER_IN f1 0xFFF4000000000000
  #_ REGISTER_IN f2 0x0000000000000001
  fsubs f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF4000000000000
  #_ REGISTER_OUT f2 0x0000000000000001
  #_ REGISTER_OUT f3 0xFFFC000000000000

test_fsubs_135_cr_GEN:
  #_ REGISTER_IN f1 0xFFF4000000000000
  #_ REGISTER_IN f2 0x0000000000000001
  fsubs. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF4000000000000
  #_ REGISTER_OUT f2 0x0000000000000001
  #_ REGISTER_OUT f3 0xFFFC000000000000
  #_ REGISTER_OUT cr 0x0A000000

test_fsubs_136_GEN:
  #_ REGISTER_IN f1 0xFFF4000000000000
  #_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
  fsubs f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF4000000000000
  #_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
  #_ REGISTER_OUT f3 0xFFFC000000000000

test_fsubs_136_cr_GEN:
  #_ REGISTER_IN f1 0xFFF4000000000000
  #_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
  fsubs. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF4000000000000
  #_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
  #_ REGISTER_OUT f3 0xFFFC000000000000
  #_ REGISTER_OUT cr 0x0A000000

test_fsubs_137_GEN:
  #_ REGISTER_IN f1 0xFFF4000000000000
  #_ REGISTER_IN f2 0x3FF0000000000000
  fsubs f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF4000000000000
  #_ REGISTER_OUT f2 0x3FF0000000000000
  #_ REGISTER_OUT f3 0xFFFC000000000000

test_fsubs_137_cr_GEN:
  #_ REGISTER_IN f1 0xFFF4000000000000
  #_ REGISTER_IN f2 0x3FF0000000000000
  fsubs. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF4000000000000
  #_ REGISTER_OUT f2 0x3FF0000000000000
  #_ REGISTER_OUT f3 0xFFFC000000000000
  #_ REGISTER_OUT cr 0x0A000000

test_fsubs_138_GEN:
  #_ REGISTER_IN f1 0xFFF4000000000000
  #_ REGISTER_IN f2 0xBFF0000000000000
  fsubs f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF4000000000000
  #_ REGISTER_OUT f2 0xBFF0000000000000
  #_ REGISTER_OUT f3 0xFFFC000000000000

test_fsubs_138_cr_GEN:
  #_ REGISTER_IN f1 0xFFF4000000000000
  #_ REGISTER_IN f2 0xBFF0000000000000
  fsubs. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF4000000000000
  #_ REGISTER_OUT f2 0xBFF0000000000000
  #_ REGISTER_OUT f3 0xFFFC000000000000
  #_ REGISTER_OUT cr 0x0A000000

test_fsubs_139_GEN:
  #_ REGISTER_IN f1 0xFFF4000000000000
  #_ REGISTER_IN f2 0xC1E0000000000000
  fsubs f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF4000000000000
  #_ REGISTER_OUT f2 0xC1E0000000000000
  #_ REGISTER_OUT f3 0xFFFC000000000000

test_fsubs_139_cr_GEN:
  #_ REGISTER_IN f1 0xFFF4000000000000
  #_ REGISTER_IN f2 0xC1E0000000000000
  fsubs. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF4000000000000
  #_ REGISTER_OUT f2 0xC1E0000000000000
  #_ REGISTER_OUT f3 0xFFFC000000000000
  #_ REGISTER_OUT cr 0x0A000000

test_fsubs_140_GEN:
  #_ REGISTER_IN f1 0xFFF4000000000000
  #_ REGISTER_IN f2 0x41DFFFFFFFC00000
  fsubs f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF4000000000000
  #_ REGISTER_OUT f2 0x41DFFFFFFFC00000
  #_ REGISTER_OUT f3 0xFFFC000000000000

test_fsubs_140_cr_GEN:
  #_ REGISTER_IN f1 0xFFF4000000000000
  #_ REGISTER_IN f2 0x41DFFFFFFFC00000
  fsubs. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF4000000000000
  #_ REGISTER_OUT f2 0x41DFFFFFFFC00000
  #_ REGISTER_OUT f3 0xFFFC000000000000
  #_ REGISTER_OUT cr 0x0A000000

test_fsubs_141_GEN:
  #_ REGISTER_IN f1 0xFFF4000000000000
  #_ REGISTER_IN f2 0x7FF0000000000000
  fsubs f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF4000000000000
  #_ REGISTER_OUT f2 0x7FF0000000000000
  #_ REGISTER_OUT f3 0xFFFC000000000000

test_fsubs_141_cr_GEN:
  #_ REGISTER_IN f1 0xFFF4000000000000
  #_ REGISTER_IN f2 0x7FF0000000000000
  fsubs. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF4000000000000
  #_ REGISTER_OUT f2 0x7FF0000000000000
  #_ REGISTER_OUT f3 0xFFFC000000000000
  #_ REGISTER_OUT cr 0x0A000000

test_fsubs_142_GEN:
  #_ REGISTER_IN f1 0xFFF4000000000000
  #_ REGISTER_IN f2 0xFFF0000000000000
  fsubs f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF4000000000000
  #_ REGISTER_OUT f2 0xFFF0000000000000
  #_ REGISTER_OUT f3 0xFFFC000000000000

test_fsubs_142_cr_GEN:
  #_ REGISTER_IN f1 0xFFF4000000000000
  #_ REGISTER_IN f2 0xFFF0000000000000
  fsubs. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF4000000000000
  #_ REGISTER_OUT f2 0xFFF0000000000000
  #_ REGISTER_OUT f3 0xFFFC000000000000
  #_ REGISTER_OUT cr 0x0A000000

test_fsubs_143_GEN:
  #_ REGISTER_IN f1 0xFFF4000000000000
  #_ REGISTER_IN f2 0xFFF8000000000000
  fsubs f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF4000000000000
  #_ REGISTER_OUT f2 0xFFF8000000000000
  #_ REGISTER_OUT f3 0xFFFC000000000000

test_fsubs_143_cr_GEN:
  #_ REGISTER_IN f1 0xFFF4000000000000
  #_ REGISTER_IN f2 0xFFF8000000000000
  fsubs. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF4000000000000
  #_ REGISTER_OUT f2 0xFFF8000000000000
  #_ REGISTER_OUT f3 0xFFFC000000000000
  #_ REGISTER_OUT cr 0x0A000000

test_fsubs_144_GEN:
  #_ REGISTER_IN f1 0xFFF4000000000000
  #_ REGISTER_IN f2 0xFFF4000000000000
  fsubs f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF4000000000000
  #_ REGISTER_OUT f2 0xFFF4000000000000
  #_ REGISTER_OUT f3 0xFFFC000000000000

test_fsubs_144_cr_GEN:
  #_ REGISTER_IN f1 0xFFF4000000000000
  #_ REGISTER_IN f2 0xFFF4000000000000
  fsubs. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF4000000000000
  #_ REGISTER_OUT f2 0xFFF4000000000000
  #_ REGISTER_OUT f3 0xFFFC000000000000
  #_ REGISTER_OUT cr 0x0A000000

