test_vslh_1:
  #_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
  #_ REGISTER_IN v4 [00000000, 00000000, 00000000, 00000000]
  vslh v3, v3, v4
  blr
  #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
  #_ REGISTER_OUT v4 [00000000, 00000000, 00000000, 00000000]

test_vslh_2:
  #_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
  #_ REGISTER_IN v4 [00010001, 00010001, 00010001, 00010001]
  vslh v3, v3, v4
  blr
  #_ REGISTER_OUT v3 [FFFEFFFE, FFFEFFFE, FFFEFFFE, FFFEFFFE]
  #_ REGISTER_OUT v4 [00010001, 00010001, 00010001, 00010001]

test_vslh_3:
  #_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
  #_ REGISTER_IN v4 [000F000F, 000F000F, 000F000F, 000F000F]
  vslh v3, v3, v4
  blr
  #_ REGISTER_OUT v3 [80008000, 80008000, 80008000, 80008000]
  #_ REGISTER_OUT v4 [000F000F, 000F000F, 000F000F, 000F000F]

test_vslh_4:
  #_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
  #_ REGISTER_IN v4 [00100010, 00100010, 00100010, 00100010]
  vslh v3, v3, v4
  blr
  #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
  #_ REGISTER_OUT v4 [00100010, 00100010, 00100010, 00100010]

test_vslh_5:
  #_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
  #_ REGISTER_IN v4 [00090009, 00090009, 00090009, 00090009]
  vslh v3, v3, v4
  blr
  #_ REGISTER_OUT v3 [FE00FE00, FE00FE00, FE00FE00, FE00FE00]
  #_ REGISTER_OUT v4 [00090009, 00090009, 00090009, 00090009]

test_vslh_6:
  #_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
  #_ REGISTER_IN v4 [00110011, 00110011, 00110011, 00110011]
  vslh v3, v3, v4
  blr
  #_ REGISTER_OUT v3 [FFFEFFFE, FFFEFFFE, FFFEFFFE, FFFEFFFE]
  #_ REGISTER_OUT v4 [00110011, 00110011, 00110011, 00110011]
