test_mulldx_1:
  #_ REGISTER_IN r4 0x0000000000001000
  #_ REGISTER_IN r5 0x0000000000000010
  mulld. r3, r4, r5
  mfcr r12
  blr
  #_ REGISTER_OUT r3 0x0000000000010000
  #_ REGISTER_OUT r12 0x0000000040000000

test_mulldx_1_constant:
  li r4, 0x1000
  li r5, 0x10
  mulld. r3, r4, r5
  mfcr r12
  blr
  #_ REGISTER_OUT r3 0x0000000000010000
  #_ REGISTER_OUT r12 0x0000000040000000

test_mulldx_negative:
  #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
  #_ REGISTER_IN r5 0x0000000000000002
  mulld. r3, r4, r5
  mfcr r12
  blr
  #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFE
  #_ REGISTER_OUT r12 0x0000000080000000

test_mulldx_overflow:
  #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
  #_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF
  mulld. r3, r4, r5
  mfcr r12
  blr
  #_ REGISTER_OUT r3 0x0000000000000001
  #_ REGISTER_OUT r12 0x0000000040000000

test_mullwx_1:
  #_ REGISTER_IN r4 0x0000000000001000
  #_ REGISTER_IN r5 0x0000000000000010
  mullw. r3, r4, r5
  mfcr r12
  blr
  #_ REGISTER_OUT r3 0x0000000000010000
  #_ REGISTER_OUT r12 0x0000000040000000

test_mullwx_negative:
  #_ REGISTER_IN r4 0x00000000FFFFFFFF
  #_ REGISTER_IN r5 0x0000000000000002
  mullw. r3, r4, r5
  mfcr r12
  blr
  #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFE
  #_ REGISTER_OUT r12 0x0000000080000000
