test_fmul_1_GEN:
  #_ REGISTER_IN f1 0x0000000000000000
  #_ REGISTER_IN f2 0x0000000000000000
  fmul f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x0000000000000000
  #_ REGISTER_OUT f2 0x0000000000000000
  #_ REGISTER_OUT f3 0x0000000000000000

test_fmul_1_cr_GEN:
  #_ REGISTER_IN f1 0x0000000000000000
  #_ REGISTER_IN f2 0x0000000000000000
  fmul. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x0000000000000000
  #_ REGISTER_OUT f2 0x0000000000000000
  #_ REGISTER_OUT f3 0x0000000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fmul_2_GEN:
  #_ REGISTER_IN f1 0x0000000000000000
  #_ REGISTER_IN f2 0x8000000000000000
  fmul f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x0000000000000000
  #_ REGISTER_OUT f2 0x8000000000000000
  #_ REGISTER_OUT f3 0x8000000000000000

test_fmul_2_cr_GEN:
  #_ REGISTER_IN f1 0x0000000000000000
  #_ REGISTER_IN f2 0x8000000000000000
  fmul. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x0000000000000000
  #_ REGISTER_OUT f2 0x8000000000000000
  #_ REGISTER_OUT f3 0x8000000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fmul_3_GEN:
  #_ REGISTER_IN f1 0x0000000000000000
  #_ REGISTER_IN f2 0x0000000000000001
  fmul f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x0000000000000000
  #_ REGISTER_OUT f2 0x0000000000000001
  #_ REGISTER_OUT f3 0x0000000000000000

test_fmul_3_cr_GEN:
  #_ REGISTER_IN f1 0x0000000000000000
  #_ REGISTER_IN f2 0x0000000000000001
  fmul. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x0000000000000000
  #_ REGISTER_OUT f2 0x0000000000000001
  #_ REGISTER_OUT f3 0x0000000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fmul_4_GEN:
  #_ REGISTER_IN f1 0x0000000000000000
  #_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
  fmul f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x0000000000000000
  #_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
  #_ REGISTER_OUT f3 0x0000000000000000

test_fmul_4_cr_GEN:
  #_ REGISTER_IN f1 0x0000000000000000
  #_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
  fmul. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x0000000000000000
  #_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
  #_ REGISTER_OUT f3 0x0000000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fmul_5_GEN:
  #_ REGISTER_IN f1 0x0000000000000000
  #_ REGISTER_IN f2 0x3FF0000000000000
  fmul f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x0000000000000000
  #_ REGISTER_OUT f2 0x3FF0000000000000
  #_ REGISTER_OUT f3 0x0000000000000000

test_fmul_5_cr_GEN:
  #_ REGISTER_IN f1 0x0000000000000000
  #_ REGISTER_IN f2 0x3FF0000000000000
  fmul. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x0000000000000000
  #_ REGISTER_OUT f2 0x3FF0000000000000
  #_ REGISTER_OUT f3 0x0000000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fmul_6_GEN:
  #_ REGISTER_IN f1 0x0000000000000000
  #_ REGISTER_IN f2 0xBFF0000000000000
  fmul f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x0000000000000000
  #_ REGISTER_OUT f2 0xBFF0000000000000
  #_ REGISTER_OUT f3 0x8000000000000000

test_fmul_6_cr_GEN:
  #_ REGISTER_IN f1 0x0000000000000000
  #_ REGISTER_IN f2 0xBFF0000000000000
  fmul. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x0000000000000000
  #_ REGISTER_OUT f2 0xBFF0000000000000
  #_ REGISTER_OUT f3 0x8000000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fmul_7_GEN:
  #_ REGISTER_IN f1 0x0000000000000000
  #_ REGISTER_IN f2 0xC1E0000000000000
  fmul f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x0000000000000000
  #_ REGISTER_OUT f2 0xC1E0000000000000
  #_ REGISTER_OUT f3 0x8000000000000000

test_fmul_7_cr_GEN:
  #_ REGISTER_IN f1 0x0000000000000000
  #_ REGISTER_IN f2 0xC1E0000000000000
  fmul. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x0000000000000000
  #_ REGISTER_OUT f2 0xC1E0000000000000
  #_ REGISTER_OUT f3 0x8000000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fmul_8_GEN:
  #_ REGISTER_IN f1 0x0000000000000000
  #_ REGISTER_IN f2 0x41DFFFFFFFC00000
  fmul f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x0000000000000000
  #_ REGISTER_OUT f2 0x41DFFFFFFFC00000
  #_ REGISTER_OUT f3 0x0000000000000000

test_fmul_8_cr_GEN:
  #_ REGISTER_IN f1 0x0000000000000000
  #_ REGISTER_IN f2 0x41DFFFFFFFC00000
  fmul. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x0000000000000000
  #_ REGISTER_OUT f2 0x41DFFFFFFFC00000
  #_ REGISTER_OUT f3 0x0000000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fmul_9_GEN:
  #_ REGISTER_IN f1 0x0000000000000000
  #_ REGISTER_IN f2 0x7FF0000000000000
  fmul f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x0000000000000000
  #_ REGISTER_OUT f2 0x7FF0000000000000
  #_ REGISTER_OUT f3 0x7FF8000000000000

test_fmul_9_cr_GEN:
  #_ REGISTER_IN f1 0x0000000000000000
  #_ REGISTER_IN f2 0x7FF0000000000000
  fmul. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x0000000000000000
  #_ REGISTER_OUT f2 0x7FF0000000000000
  #_ REGISTER_OUT f3 0x7FF8000000000000
  #_ REGISTER_OUT cr 0x0A000000

test_fmul_10_GEN:
  #_ REGISTER_IN f1 0x0000000000000000
  #_ REGISTER_IN f2 0xFFF0000000000000
  fmul f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x0000000000000000
  #_ REGISTER_OUT f2 0xFFF0000000000000
  #_ REGISTER_OUT f3 0x7FF8000000000000

test_fmul_10_cr_GEN:
  #_ REGISTER_IN f1 0x0000000000000000
  #_ REGISTER_IN f2 0xFFF0000000000000
  fmul. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x0000000000000000
  #_ REGISTER_OUT f2 0xFFF0000000000000
  #_ REGISTER_OUT f3 0x7FF8000000000000
  #_ REGISTER_OUT cr 0x0A000000

test_fmul_11_GEN:
  #_ REGISTER_IN f1 0x0000000000000000
  #_ REGISTER_IN f2 0xFFF8000000000000
  fmul f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x0000000000000000
  #_ REGISTER_OUT f2 0xFFF8000000000000
  #_ REGISTER_OUT f3 0xFFF8000000000000

test_fmul_11_cr_GEN:
  #_ REGISTER_IN f1 0x0000000000000000
  #_ REGISTER_IN f2 0xFFF8000000000000
  fmul. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x0000000000000000
  #_ REGISTER_OUT f2 0xFFF8000000000000
  #_ REGISTER_OUT f3 0xFFF8000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fmul_12_GEN:
  #_ REGISTER_IN f1 0x0000000000000000
  #_ REGISTER_IN f2 0xFFF4000000000000
  fmul f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x0000000000000000
  #_ REGISTER_OUT f2 0xFFF4000000000000
  #_ REGISTER_OUT f3 0xFFFC000000000000

test_fmul_12_cr_GEN:
  #_ REGISTER_IN f1 0x0000000000000000
  #_ REGISTER_IN f2 0xFFF4000000000000
  fmul. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x0000000000000000
  #_ REGISTER_OUT f2 0xFFF4000000000000
  #_ REGISTER_OUT f3 0xFFFC000000000000
  #_ REGISTER_OUT cr 0x0A000000

test_fmul_13_GEN:
  #_ REGISTER_IN f1 0x8000000000000000
  #_ REGISTER_IN f2 0x0000000000000000
  fmul f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x8000000000000000
  #_ REGISTER_OUT f2 0x0000000000000000
  #_ REGISTER_OUT f3 0x8000000000000000

test_fmul_13_cr_GEN:
  #_ REGISTER_IN f1 0x8000000000000000
  #_ REGISTER_IN f2 0x0000000000000000
  fmul. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x8000000000000000
  #_ REGISTER_OUT f2 0x0000000000000000
  #_ REGISTER_OUT f3 0x8000000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fmul_14_GEN:
  #_ REGISTER_IN f1 0x8000000000000000
  #_ REGISTER_IN f2 0x8000000000000000
  fmul f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x8000000000000000
  #_ REGISTER_OUT f2 0x8000000000000000
  #_ REGISTER_OUT f3 0x0000000000000000

test_fmul_14_cr_GEN:
  #_ REGISTER_IN f1 0x8000000000000000
  #_ REGISTER_IN f2 0x8000000000000000
  fmul. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x8000000000000000
  #_ REGISTER_OUT f2 0x8000000000000000
  #_ REGISTER_OUT f3 0x0000000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fmul_15_GEN:
  #_ REGISTER_IN f1 0x8000000000000000
  #_ REGISTER_IN f2 0x0000000000000001
  fmul f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x8000000000000000
  #_ REGISTER_OUT f2 0x0000000000000001
  #_ REGISTER_OUT f3 0x8000000000000000

test_fmul_15_cr_GEN:
  #_ REGISTER_IN f1 0x8000000000000000
  #_ REGISTER_IN f2 0x0000000000000001
  fmul. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x8000000000000000
  #_ REGISTER_OUT f2 0x0000000000000001
  #_ REGISTER_OUT f3 0x8000000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fmul_16_GEN:
  #_ REGISTER_IN f1 0x8000000000000000
  #_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
  fmul f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x8000000000000000
  #_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
  #_ REGISTER_OUT f3 0x8000000000000000

test_fmul_16_cr_GEN:
  #_ REGISTER_IN f1 0x8000000000000000
  #_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
  fmul. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x8000000000000000
  #_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
  #_ REGISTER_OUT f3 0x8000000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fmul_17_GEN:
  #_ REGISTER_IN f1 0x8000000000000000
  #_ REGISTER_IN f2 0x3FF0000000000000
  fmul f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x8000000000000000
  #_ REGISTER_OUT f2 0x3FF0000000000000
  #_ REGISTER_OUT f3 0x8000000000000000

test_fmul_17_cr_GEN:
  #_ REGISTER_IN f1 0x8000000000000000
  #_ REGISTER_IN f2 0x3FF0000000000000
  fmul. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x8000000000000000
  #_ REGISTER_OUT f2 0x3FF0000000000000
  #_ REGISTER_OUT f3 0x8000000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fmul_18_GEN:
  #_ REGISTER_IN f1 0x8000000000000000
  #_ REGISTER_IN f2 0xBFF0000000000000
  fmul f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x8000000000000000
  #_ REGISTER_OUT f2 0xBFF0000000000000
  #_ REGISTER_OUT f3 0x0000000000000000

test_fmul_18_cr_GEN:
  #_ REGISTER_IN f1 0x8000000000000000
  #_ REGISTER_IN f2 0xBFF0000000000000
  fmul. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x8000000000000000
  #_ REGISTER_OUT f2 0xBFF0000000000000
  #_ REGISTER_OUT f3 0x0000000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fmul_19_GEN:
  #_ REGISTER_IN f1 0x8000000000000000
  #_ REGISTER_IN f2 0xC1E0000000000000
  fmul f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x8000000000000000
  #_ REGISTER_OUT f2 0xC1E0000000000000
  #_ REGISTER_OUT f3 0x0000000000000000

test_fmul_19_cr_GEN:
  #_ REGISTER_IN f1 0x8000000000000000
  #_ REGISTER_IN f2 0xC1E0000000000000
  fmul. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x8000000000000000
  #_ REGISTER_OUT f2 0xC1E0000000000000
  #_ REGISTER_OUT f3 0x0000000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fmul_20_GEN:
  #_ REGISTER_IN f1 0x8000000000000000
  #_ REGISTER_IN f2 0x41DFFFFFFFC00000
  fmul f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x8000000000000000
  #_ REGISTER_OUT f2 0x41DFFFFFFFC00000
  #_ REGISTER_OUT f3 0x8000000000000000

test_fmul_20_cr_GEN:
  #_ REGISTER_IN f1 0x8000000000000000
  #_ REGISTER_IN f2 0x41DFFFFFFFC00000
  fmul. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x8000000000000000
  #_ REGISTER_OUT f2 0x41DFFFFFFFC00000
  #_ REGISTER_OUT f3 0x8000000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fmul_21_GEN:
  #_ REGISTER_IN f1 0x8000000000000000
  #_ REGISTER_IN f2 0x7FF0000000000000
  fmul f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x8000000000000000
  #_ REGISTER_OUT f2 0x7FF0000000000000
  #_ REGISTER_OUT f3 0x7FF8000000000000

test_fmul_21_cr_GEN:
  #_ REGISTER_IN f1 0x8000000000000000
  #_ REGISTER_IN f2 0x7FF0000000000000
  fmul. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x8000000000000000
  #_ REGISTER_OUT f2 0x7FF0000000000000
  #_ REGISTER_OUT f3 0x7FF8000000000000
  #_ REGISTER_OUT cr 0x0A000000

test_fmul_22_GEN:
  #_ REGISTER_IN f1 0x8000000000000000
  #_ REGISTER_IN f2 0xFFF0000000000000
  fmul f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x8000000000000000
  #_ REGISTER_OUT f2 0xFFF0000000000000
  #_ REGISTER_OUT f3 0x7FF8000000000000

test_fmul_22_cr_GEN:
  #_ REGISTER_IN f1 0x8000000000000000
  #_ REGISTER_IN f2 0xFFF0000000000000
  fmul. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x8000000000000000
  #_ REGISTER_OUT f2 0xFFF0000000000000
  #_ REGISTER_OUT f3 0x7FF8000000000000
  #_ REGISTER_OUT cr 0x0A000000

test_fmul_23_GEN:
  #_ REGISTER_IN f1 0x8000000000000000
  #_ REGISTER_IN f2 0xFFF8000000000000
  fmul f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x8000000000000000
  #_ REGISTER_OUT f2 0xFFF8000000000000
  #_ REGISTER_OUT f3 0xFFF8000000000000

test_fmul_23_cr_GEN:
  #_ REGISTER_IN f1 0x8000000000000000
  #_ REGISTER_IN f2 0xFFF8000000000000
  fmul. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x8000000000000000
  #_ REGISTER_OUT f2 0xFFF8000000000000
  #_ REGISTER_OUT f3 0xFFF8000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fmul_24_GEN:
  #_ REGISTER_IN f1 0x8000000000000000
  #_ REGISTER_IN f2 0xFFF4000000000000
  fmul f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x8000000000000000
  #_ REGISTER_OUT f2 0xFFF4000000000000
  #_ REGISTER_OUT f3 0xFFFC000000000000

test_fmul_24_cr_GEN:
  #_ REGISTER_IN f1 0x8000000000000000
  #_ REGISTER_IN f2 0xFFF4000000000000
  fmul. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x8000000000000000
  #_ REGISTER_OUT f2 0xFFF4000000000000
  #_ REGISTER_OUT f3 0xFFFC000000000000
  #_ REGISTER_OUT cr 0x0A000000

test_fmul_25_GEN:
  #_ REGISTER_IN f1 0x0000000000000001
  #_ REGISTER_IN f2 0x0000000000000000
  fmul f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x0000000000000001
  #_ REGISTER_OUT f2 0x0000000000000000
  #_ REGISTER_OUT f3 0x0000000000000000

test_fmul_25_cr_GEN:
  #_ REGISTER_IN f1 0x0000000000000001
  #_ REGISTER_IN f2 0x0000000000000000
  fmul. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x0000000000000001
  #_ REGISTER_OUT f2 0x0000000000000000
  #_ REGISTER_OUT f3 0x0000000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fmul_26_GEN:
  #_ REGISTER_IN f1 0x0000000000000001
  #_ REGISTER_IN f2 0x8000000000000000
  fmul f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x0000000000000001
  #_ REGISTER_OUT f2 0x8000000000000000
  #_ REGISTER_OUT f3 0x8000000000000000

test_fmul_26_cr_GEN:
  #_ REGISTER_IN f1 0x0000000000000001
  #_ REGISTER_IN f2 0x8000000000000000
  fmul. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x0000000000000001
  #_ REGISTER_OUT f2 0x8000000000000000
  #_ REGISTER_OUT f3 0x8000000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fmul_27_GEN:
  #_ REGISTER_IN f1 0x0000000000000001
  #_ REGISTER_IN f2 0x0000000000000001
  fmul f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x0000000000000001
  #_ REGISTER_OUT f2 0x0000000000000001
  #_ REGISTER_OUT f3 0x0000000000000000

test_fmul_27_cr_GEN:
  #_ REGISTER_IN f1 0x0000000000000001
  #_ REGISTER_IN f2 0x0000000000000001
  fmul. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x0000000000000001
  #_ REGISTER_OUT f2 0x0000000000000001
  #_ REGISTER_OUT f3 0x0000000000000000
  #_ REGISTER_OUT cr 0x08000000

test_fmul_28_GEN:
  #_ REGISTER_IN f1 0x0000000000000001
  #_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
  fmul f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x0000000000000001
  #_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
  #_ REGISTER_OUT f3 0x0000000000000000

test_fmul_28_cr_GEN:
  #_ REGISTER_IN f1 0x0000000000000001
  #_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
  fmul. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x0000000000000001
  #_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
  #_ REGISTER_OUT f3 0x0000000000000000
  #_ REGISTER_OUT cr 0x08000000

test_fmul_29_GEN:
  #_ REGISTER_IN f1 0x0000000000000001
  #_ REGISTER_IN f2 0x3FF0000000000000
  fmul f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x0000000000000001
  #_ REGISTER_OUT f2 0x3FF0000000000000
  #_ REGISTER_OUT f3 0x0000000000000001

test_fmul_29_cr_GEN:
  #_ REGISTER_IN f1 0x0000000000000001
  #_ REGISTER_IN f2 0x3FF0000000000000
  fmul. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x0000000000000001
  #_ REGISTER_OUT f2 0x3FF0000000000000
  #_ REGISTER_OUT f3 0x0000000000000001
  #_ REGISTER_OUT cr 0x00000000

test_fmul_30_GEN:
  #_ REGISTER_IN f1 0x0000000000000001
  #_ REGISTER_IN f2 0xBFF0000000000000
  fmul f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x0000000000000001
  #_ REGISTER_OUT f2 0xBFF0000000000000
  #_ REGISTER_OUT f3 0x8000000000000001

test_fmul_30_cr_GEN:
  #_ REGISTER_IN f1 0x0000000000000001
  #_ REGISTER_IN f2 0xBFF0000000000000
  fmul. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x0000000000000001
  #_ REGISTER_OUT f2 0xBFF0000000000000
  #_ REGISTER_OUT f3 0x8000000000000001
  #_ REGISTER_OUT cr 0x00000000

test_fmul_31_GEN:
  #_ REGISTER_IN f1 0x0000000000000001
  #_ REGISTER_IN f2 0xC1E0000000000000
  fmul f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x0000000000000001
  #_ REGISTER_OUT f2 0xC1E0000000000000
  #_ REGISTER_OUT f3 0x8000000080000000

test_fmul_31_cr_GEN:
  #_ REGISTER_IN f1 0x0000000000000001
  #_ REGISTER_IN f2 0xC1E0000000000000
  fmul. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x0000000000000001
  #_ REGISTER_OUT f2 0xC1E0000000000000
  #_ REGISTER_OUT f3 0x8000000080000000
  #_ REGISTER_OUT cr 0x00000000

test_fmul_32_GEN:
  #_ REGISTER_IN f1 0x0000000000000001
  #_ REGISTER_IN f2 0x41DFFFFFFFC00000
  fmul f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x0000000000000001
  #_ REGISTER_OUT f2 0x41DFFFFFFFC00000
  #_ REGISTER_OUT f3 0x000000007FFFFFFF

test_fmul_32_cr_GEN:
  #_ REGISTER_IN f1 0x0000000000000001
  #_ REGISTER_IN f2 0x41DFFFFFFFC00000
  fmul. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x0000000000000001
  #_ REGISTER_OUT f2 0x41DFFFFFFFC00000
  #_ REGISTER_OUT f3 0x000000007FFFFFFF
  #_ REGISTER_OUT cr 0x00000000

test_fmul_33_GEN:
  #_ REGISTER_IN f1 0x0000000000000001
  #_ REGISTER_IN f2 0x7FF0000000000000
  fmul f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x0000000000000001
  #_ REGISTER_OUT f2 0x7FF0000000000000
  #_ REGISTER_OUT f3 0x7FF0000000000000

test_fmul_33_cr_GEN:
  #_ REGISTER_IN f1 0x0000000000000001
  #_ REGISTER_IN f2 0x7FF0000000000000
  fmul. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x0000000000000001
  #_ REGISTER_OUT f2 0x7FF0000000000000
  #_ REGISTER_OUT f3 0x7FF0000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fmul_34_GEN:
  #_ REGISTER_IN f1 0x0000000000000001
  #_ REGISTER_IN f2 0xFFF0000000000000
  fmul f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x0000000000000001
  #_ REGISTER_OUT f2 0xFFF0000000000000
  #_ REGISTER_OUT f3 0xFFF0000000000000

test_fmul_34_cr_GEN:
  #_ REGISTER_IN f1 0x0000000000000001
  #_ REGISTER_IN f2 0xFFF0000000000000
  fmul. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x0000000000000001
  #_ REGISTER_OUT f2 0xFFF0000000000000
  #_ REGISTER_OUT f3 0xFFF0000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fmul_35_GEN:
  #_ REGISTER_IN f1 0x0000000000000001
  #_ REGISTER_IN f2 0xFFF8000000000000
  fmul f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x0000000000000001
  #_ REGISTER_OUT f2 0xFFF8000000000000
  #_ REGISTER_OUT f3 0xFFF8000000000000

test_fmul_35_cr_GEN:
  #_ REGISTER_IN f1 0x0000000000000001
  #_ REGISTER_IN f2 0xFFF8000000000000
  fmul. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x0000000000000001
  #_ REGISTER_OUT f2 0xFFF8000000000000
  #_ REGISTER_OUT f3 0xFFF8000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fmul_36_GEN:
  #_ REGISTER_IN f1 0x0000000000000001
  #_ REGISTER_IN f2 0xFFF4000000000000
  fmul f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x0000000000000001
  #_ REGISTER_OUT f2 0xFFF4000000000000
  #_ REGISTER_OUT f3 0xFFFC000000000000

test_fmul_36_cr_GEN:
  #_ REGISTER_IN f1 0x0000000000000001
  #_ REGISTER_IN f2 0xFFF4000000000000
  fmul. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x0000000000000001
  #_ REGISTER_OUT f2 0xFFF4000000000000
  #_ REGISTER_OUT f3 0xFFFC000000000000
  #_ REGISTER_OUT cr 0x0A000000

test_fmul_37_GEN:
  #_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
  #_ REGISTER_IN f2 0x0000000000000000
  fmul f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
  #_ REGISTER_OUT f2 0x0000000000000000
  #_ REGISTER_OUT f3 0x0000000000000000

test_fmul_37_cr_GEN:
  #_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
  #_ REGISTER_IN f2 0x0000000000000000
  fmul. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
  #_ REGISTER_OUT f2 0x0000000000000000
  #_ REGISTER_OUT f3 0x0000000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fmul_38_GEN:
  #_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
  #_ REGISTER_IN f2 0x8000000000000000
  fmul f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
  #_ REGISTER_OUT f2 0x8000000000000000
  #_ REGISTER_OUT f3 0x8000000000000000

test_fmul_38_cr_GEN:
  #_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
  #_ REGISTER_IN f2 0x8000000000000000
  fmul. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
  #_ REGISTER_OUT f2 0x8000000000000000
  #_ REGISTER_OUT f3 0x8000000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fmul_39_GEN:
  #_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
  #_ REGISTER_IN f2 0x0000000000000001
  fmul f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
  #_ REGISTER_OUT f2 0x0000000000000001
  #_ REGISTER_OUT f3 0x0000000000000000

test_fmul_39_cr_GEN:
  #_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
  #_ REGISTER_IN f2 0x0000000000000001
  fmul. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
  #_ REGISTER_OUT f2 0x0000000000000001
  #_ REGISTER_OUT f3 0x0000000000000000
  #_ REGISTER_OUT cr 0x08000000

test_fmul_40_GEN:
  #_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
  #_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
  fmul f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
  #_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
  #_ REGISTER_OUT f3 0x0000000000000000

test_fmul_40_cr_GEN:
  #_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
  #_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
  fmul. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
  #_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
  #_ REGISTER_OUT f3 0x0000000000000000
  #_ REGISTER_OUT cr 0x08000000

test_fmul_41_GEN:
  #_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
  #_ REGISTER_IN f2 0x3FF0000000000000
  fmul f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
  #_ REGISTER_OUT f2 0x3FF0000000000000
  #_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF

test_fmul_41_cr_GEN:
  #_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
  #_ REGISTER_IN f2 0x3FF0000000000000
  fmul. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
  #_ REGISTER_OUT f2 0x3FF0000000000000
  #_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
  #_ REGISTER_OUT cr 0x00000000

test_fmul_42_GEN:
  #_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
  #_ REGISTER_IN f2 0xBFF0000000000000
  fmul f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
  #_ REGISTER_OUT f2 0xBFF0000000000000
  #_ REGISTER_OUT f3 0x800FFFFFFFFFFFFF

test_fmul_42_cr_GEN:
  #_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
  #_ REGISTER_IN f2 0xBFF0000000000000
  fmul. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
  #_ REGISTER_OUT f2 0xBFF0000000000000
  #_ REGISTER_OUT f3 0x800FFFFFFFFFFFFF
  #_ REGISTER_OUT cr 0x00000000

test_fmul_43_GEN:
  #_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
  #_ REGISTER_IN f2 0xC1E0000000000000
  fmul f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
  #_ REGISTER_OUT f2 0xC1E0000000000000
  #_ REGISTER_OUT f3 0x81FFFFFFFFFFFFFE

test_fmul_43_cr_GEN:
  #_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
  #_ REGISTER_IN f2 0xC1E0000000000000
  fmul. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
  #_ REGISTER_OUT f2 0xC1E0000000000000
  #_ REGISTER_OUT f3 0x81FFFFFFFFFFFFFE
  #_ REGISTER_OUT cr 0x00000000

test_fmul_44_GEN:
  #_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
  #_ REGISTER_IN f2 0x41DFFFFFFFC00000
  fmul f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
  #_ REGISTER_OUT f2 0x41DFFFFFFFC00000
  #_ REGISTER_OUT f3 0x01FFFFFFFFBFFFFE

test_fmul_44_cr_GEN:
  #_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
  #_ REGISTER_IN f2 0x41DFFFFFFFC00000
  fmul. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
  #_ REGISTER_OUT f2 0x41DFFFFFFFC00000
  #_ REGISTER_OUT f3 0x01FFFFFFFFBFFFFE
  #_ REGISTER_OUT cr 0x08000000

test_fmul_45_GEN:
  #_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
  #_ REGISTER_IN f2 0x7FF0000000000000
  fmul f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
  #_ REGISTER_OUT f2 0x7FF0000000000000
  #_ REGISTER_OUT f3 0x7FF0000000000000

test_fmul_45_cr_GEN:
  #_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
  #_ REGISTER_IN f2 0x7FF0000000000000
  fmul. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
  #_ REGISTER_OUT f2 0x7FF0000000000000
  #_ REGISTER_OUT f3 0x7FF0000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fmul_46_GEN:
  #_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
  #_ REGISTER_IN f2 0xFFF0000000000000
  fmul f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
  #_ REGISTER_OUT f2 0xFFF0000000000000
  #_ REGISTER_OUT f3 0xFFF0000000000000

test_fmul_46_cr_GEN:
  #_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
  #_ REGISTER_IN f2 0xFFF0000000000000
  fmul. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
  #_ REGISTER_OUT f2 0xFFF0000000000000
  #_ REGISTER_OUT f3 0xFFF0000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fmul_47_GEN:
  #_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
  #_ REGISTER_IN f2 0xFFF8000000000000
  fmul f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
  #_ REGISTER_OUT f2 0xFFF8000000000000
  #_ REGISTER_OUT f3 0xFFF8000000000000

test_fmul_47_cr_GEN:
  #_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
  #_ REGISTER_IN f2 0xFFF8000000000000
  fmul. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
  #_ REGISTER_OUT f2 0xFFF8000000000000
  #_ REGISTER_OUT f3 0xFFF8000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fmul_48_GEN:
  #_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
  #_ REGISTER_IN f2 0xFFF4000000000000
  fmul f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
  #_ REGISTER_OUT f2 0xFFF4000000000000
  #_ REGISTER_OUT f3 0xFFFC000000000000

test_fmul_48_cr_GEN:
  #_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
  #_ REGISTER_IN f2 0xFFF4000000000000
  fmul. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
  #_ REGISTER_OUT f2 0xFFF4000000000000
  #_ REGISTER_OUT f3 0xFFFC000000000000
  #_ REGISTER_OUT cr 0x0A000000

test_fmul_49_GEN:
  #_ REGISTER_IN f1 0x3FF0000000000000
  #_ REGISTER_IN f2 0x0000000000000000
  fmul f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x3FF0000000000000
  #_ REGISTER_OUT f2 0x0000000000000000
  #_ REGISTER_OUT f3 0x0000000000000000

test_fmul_49_cr_GEN:
  #_ REGISTER_IN f1 0x3FF0000000000000
  #_ REGISTER_IN f2 0x0000000000000000
  fmul. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x3FF0000000000000
  #_ REGISTER_OUT f2 0x0000000000000000
  #_ REGISTER_OUT f3 0x0000000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fmul_50_GEN:
  #_ REGISTER_IN f1 0x3FF0000000000000
  #_ REGISTER_IN f2 0x8000000000000000
  fmul f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x3FF0000000000000
  #_ REGISTER_OUT f2 0x8000000000000000
  #_ REGISTER_OUT f3 0x8000000000000000

test_fmul_50_cr_GEN:
  #_ REGISTER_IN f1 0x3FF0000000000000
  #_ REGISTER_IN f2 0x8000000000000000
  fmul. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x3FF0000000000000
  #_ REGISTER_OUT f2 0x8000000000000000
  #_ REGISTER_OUT f3 0x8000000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fmul_51_GEN:
  #_ REGISTER_IN f1 0x3FF0000000000000
  #_ REGISTER_IN f2 0x0000000000000001
  fmul f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x3FF0000000000000
  #_ REGISTER_OUT f2 0x0000000000000001
  #_ REGISTER_OUT f3 0x0000000000000001

test_fmul_51_cr_GEN:
  #_ REGISTER_IN f1 0x3FF0000000000000
  #_ REGISTER_IN f2 0x0000000000000001
  fmul. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x3FF0000000000000
  #_ REGISTER_OUT f2 0x0000000000000001
  #_ REGISTER_OUT f3 0x0000000000000001
  #_ REGISTER_OUT cr 0x00000000

test_fmul_52_GEN:
  #_ REGISTER_IN f1 0x3FF0000000000000
  #_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
  fmul f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x3FF0000000000000
  #_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
  #_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF

test_fmul_52_cr_GEN:
  #_ REGISTER_IN f1 0x3FF0000000000000
  #_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
  fmul. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x3FF0000000000000
  #_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
  #_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
  #_ REGISTER_OUT cr 0x00000000

test_fmul_53_GEN:
  #_ REGISTER_IN f1 0x3FF0000000000000
  #_ REGISTER_IN f2 0x3FF0000000000000
  fmul f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x3FF0000000000000
  #_ REGISTER_OUT f2 0x3FF0000000000000
  #_ REGISTER_OUT f3 0x3FF0000000000000

test_fmul_53_cr_GEN:
  #_ REGISTER_IN f1 0x3FF0000000000000
  #_ REGISTER_IN f2 0x3FF0000000000000
  fmul. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x3FF0000000000000
  #_ REGISTER_OUT f2 0x3FF0000000000000
  #_ REGISTER_OUT f3 0x3FF0000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fmul_54_GEN:
  #_ REGISTER_IN f1 0x3FF0000000000000
  #_ REGISTER_IN f2 0xBFF0000000000000
  fmul f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x3FF0000000000000
  #_ REGISTER_OUT f2 0xBFF0000000000000
  #_ REGISTER_OUT f3 0xBFF0000000000000

test_fmul_54_cr_GEN:
  #_ REGISTER_IN f1 0x3FF0000000000000
  #_ REGISTER_IN f2 0xBFF0000000000000
  fmul. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x3FF0000000000000
  #_ REGISTER_OUT f2 0xBFF0000000000000
  #_ REGISTER_OUT f3 0xBFF0000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fmul_55_GEN:
  #_ REGISTER_IN f1 0x3FF0000000000000
  #_ REGISTER_IN f2 0xC1E0000000000000
  fmul f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x3FF0000000000000
  #_ REGISTER_OUT f2 0xC1E0000000000000
  #_ REGISTER_OUT f3 0xC1E0000000000000

test_fmul_55_cr_GEN:
  #_ REGISTER_IN f1 0x3FF0000000000000
  #_ REGISTER_IN f2 0xC1E0000000000000
  fmul. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x3FF0000000000000
  #_ REGISTER_OUT f2 0xC1E0000000000000
  #_ REGISTER_OUT f3 0xC1E0000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fmul_56_GEN:
  #_ REGISTER_IN f1 0x3FF0000000000000
  #_ REGISTER_IN f2 0x41DFFFFFFFC00000
  fmul f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x3FF0000000000000
  #_ REGISTER_OUT f2 0x41DFFFFFFFC00000
  #_ REGISTER_OUT f3 0x41DFFFFFFFC00000

test_fmul_56_cr_GEN:
  #_ REGISTER_IN f1 0x3FF0000000000000
  #_ REGISTER_IN f2 0x41DFFFFFFFC00000
  fmul. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x3FF0000000000000
  #_ REGISTER_OUT f2 0x41DFFFFFFFC00000
  #_ REGISTER_OUT f3 0x41DFFFFFFFC00000
  #_ REGISTER_OUT cr 0x00000000

test_fmul_57_GEN:
  #_ REGISTER_IN f1 0x3FF0000000000000
  #_ REGISTER_IN f2 0x7FF0000000000000
  fmul f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x3FF0000000000000
  #_ REGISTER_OUT f2 0x7FF0000000000000
  #_ REGISTER_OUT f3 0x7FF0000000000000

test_fmul_57_cr_GEN:
  #_ REGISTER_IN f1 0x3FF0000000000000
  #_ REGISTER_IN f2 0x7FF0000000000000
  fmul. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x3FF0000000000000
  #_ REGISTER_OUT f2 0x7FF0000000000000
  #_ REGISTER_OUT f3 0x7FF0000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fmul_58_GEN:
  #_ REGISTER_IN f1 0x3FF0000000000000
  #_ REGISTER_IN f2 0xFFF0000000000000
  fmul f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x3FF0000000000000
  #_ REGISTER_OUT f2 0xFFF0000000000000
  #_ REGISTER_OUT f3 0xFFF0000000000000

test_fmul_58_cr_GEN:
  #_ REGISTER_IN f1 0x3FF0000000000000
  #_ REGISTER_IN f2 0xFFF0000000000000
  fmul. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x3FF0000000000000
  #_ REGISTER_OUT f2 0xFFF0000000000000
  #_ REGISTER_OUT f3 0xFFF0000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fmul_59_GEN:
  #_ REGISTER_IN f1 0x3FF0000000000000
  #_ REGISTER_IN f2 0xFFF8000000000000
  fmul f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x3FF0000000000000
  #_ REGISTER_OUT f2 0xFFF8000000000000
  #_ REGISTER_OUT f3 0xFFF8000000000000

test_fmul_59_cr_GEN:
  #_ REGISTER_IN f1 0x3FF0000000000000
  #_ REGISTER_IN f2 0xFFF8000000000000
  fmul. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x3FF0000000000000
  #_ REGISTER_OUT f2 0xFFF8000000000000
  #_ REGISTER_OUT f3 0xFFF8000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fmul_60_GEN:
  #_ REGISTER_IN f1 0x3FF0000000000000
  #_ REGISTER_IN f2 0xFFF4000000000000
  fmul f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x3FF0000000000000
  #_ REGISTER_OUT f2 0xFFF4000000000000
  #_ REGISTER_OUT f3 0xFFFC000000000000

test_fmul_60_cr_GEN:
  #_ REGISTER_IN f1 0x3FF0000000000000
  #_ REGISTER_IN f2 0xFFF4000000000000
  fmul. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x3FF0000000000000
  #_ REGISTER_OUT f2 0xFFF4000000000000
  #_ REGISTER_OUT f3 0xFFFC000000000000
  #_ REGISTER_OUT cr 0x0A000000

test_fmul_61_GEN:
  #_ REGISTER_IN f1 0xBFF0000000000000
  #_ REGISTER_IN f2 0x0000000000000000
  fmul f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xBFF0000000000000
  #_ REGISTER_OUT f2 0x0000000000000000
  #_ REGISTER_OUT f3 0x8000000000000000

test_fmul_61_cr_GEN:
  #_ REGISTER_IN f1 0xBFF0000000000000
  #_ REGISTER_IN f2 0x0000000000000000
  fmul. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xBFF0000000000000
  #_ REGISTER_OUT f2 0x0000000000000000
  #_ REGISTER_OUT f3 0x8000000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fmul_62_GEN:
  #_ REGISTER_IN f1 0xBFF0000000000000
  #_ REGISTER_IN f2 0x8000000000000000
  fmul f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xBFF0000000000000
  #_ REGISTER_OUT f2 0x8000000000000000
  #_ REGISTER_OUT f3 0x0000000000000000

test_fmul_62_cr_GEN:
  #_ REGISTER_IN f1 0xBFF0000000000000
  #_ REGISTER_IN f2 0x8000000000000000
  fmul. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xBFF0000000000000
  #_ REGISTER_OUT f2 0x8000000000000000
  #_ REGISTER_OUT f3 0x0000000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fmul_63_GEN:
  #_ REGISTER_IN f1 0xBFF0000000000000
  #_ REGISTER_IN f2 0x0000000000000001
  fmul f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xBFF0000000000000
  #_ REGISTER_OUT f2 0x0000000000000001
  #_ REGISTER_OUT f3 0x8000000000000001

test_fmul_63_cr_GEN:
  #_ REGISTER_IN f1 0xBFF0000000000000
  #_ REGISTER_IN f2 0x0000000000000001
  fmul. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xBFF0000000000000
  #_ REGISTER_OUT f2 0x0000000000000001
  #_ REGISTER_OUT f3 0x8000000000000001
  #_ REGISTER_OUT cr 0x00000000

test_fmul_64_GEN:
  #_ REGISTER_IN f1 0xBFF0000000000000
  #_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
  fmul f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xBFF0000000000000
  #_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
  #_ REGISTER_OUT f3 0x800FFFFFFFFFFFFF

test_fmul_64_cr_GEN:
  #_ REGISTER_IN f1 0xBFF0000000000000
  #_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
  fmul. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xBFF0000000000000
  #_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
  #_ REGISTER_OUT f3 0x800FFFFFFFFFFFFF
  #_ REGISTER_OUT cr 0x00000000

test_fmul_65_GEN:
  #_ REGISTER_IN f1 0xBFF0000000000000
  #_ REGISTER_IN f2 0x3FF0000000000000
  fmul f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xBFF0000000000000
  #_ REGISTER_OUT f2 0x3FF0000000000000
  #_ REGISTER_OUT f3 0xBFF0000000000000

test_fmul_65_cr_GEN:
  #_ REGISTER_IN f1 0xBFF0000000000000
  #_ REGISTER_IN f2 0x3FF0000000000000
  fmul. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xBFF0000000000000
  #_ REGISTER_OUT f2 0x3FF0000000000000
  #_ REGISTER_OUT f3 0xBFF0000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fmul_66_GEN:
  #_ REGISTER_IN f1 0xBFF0000000000000
  #_ REGISTER_IN f2 0xBFF0000000000000
  fmul f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xBFF0000000000000
  #_ REGISTER_OUT f2 0xBFF0000000000000
  #_ REGISTER_OUT f3 0x3FF0000000000000

test_fmul_66_cr_GEN:
  #_ REGISTER_IN f1 0xBFF0000000000000
  #_ REGISTER_IN f2 0xBFF0000000000000
  fmul. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xBFF0000000000000
  #_ REGISTER_OUT f2 0xBFF0000000000000
  #_ REGISTER_OUT f3 0x3FF0000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fmul_67_GEN:
  #_ REGISTER_IN f1 0xBFF0000000000000
  #_ REGISTER_IN f2 0xC1E0000000000000
  fmul f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xBFF0000000000000
  #_ REGISTER_OUT f2 0xC1E0000000000000
  #_ REGISTER_OUT f3 0x41E0000000000000

test_fmul_67_cr_GEN:
  #_ REGISTER_IN f1 0xBFF0000000000000
  #_ REGISTER_IN f2 0xC1E0000000000000
  fmul. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xBFF0000000000000
  #_ REGISTER_OUT f2 0xC1E0000000000000
  #_ REGISTER_OUT f3 0x41E0000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fmul_68_GEN:
  #_ REGISTER_IN f1 0xBFF0000000000000
  #_ REGISTER_IN f2 0x41DFFFFFFFC00000
  fmul f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xBFF0000000000000
  #_ REGISTER_OUT f2 0x41DFFFFFFFC00000
  #_ REGISTER_OUT f3 0xC1DFFFFFFFC00000

test_fmul_68_cr_GEN:
  #_ REGISTER_IN f1 0xBFF0000000000000
  #_ REGISTER_IN f2 0x41DFFFFFFFC00000
  fmul. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xBFF0000000000000
  #_ REGISTER_OUT f2 0x41DFFFFFFFC00000
  #_ REGISTER_OUT f3 0xC1DFFFFFFFC00000
  #_ REGISTER_OUT cr 0x00000000

test_fmul_69_GEN:
  #_ REGISTER_IN f1 0xBFF0000000000000
  #_ REGISTER_IN f2 0x7FF0000000000000
  fmul f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xBFF0000000000000
  #_ REGISTER_OUT f2 0x7FF0000000000000
  #_ REGISTER_OUT f3 0xFFF0000000000000

test_fmul_69_cr_GEN:
  #_ REGISTER_IN f1 0xBFF0000000000000
  #_ REGISTER_IN f2 0x7FF0000000000000
  fmul. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xBFF0000000000000
  #_ REGISTER_OUT f2 0x7FF0000000000000
  #_ REGISTER_OUT f3 0xFFF0000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fmul_70_GEN:
  #_ REGISTER_IN f1 0xBFF0000000000000
  #_ REGISTER_IN f2 0xFFF0000000000000
  fmul f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xBFF0000000000000
  #_ REGISTER_OUT f2 0xFFF0000000000000
  #_ REGISTER_OUT f3 0x7FF0000000000000

test_fmul_70_cr_GEN:
  #_ REGISTER_IN f1 0xBFF0000000000000
  #_ REGISTER_IN f2 0xFFF0000000000000
  fmul. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xBFF0000000000000
  #_ REGISTER_OUT f2 0xFFF0000000000000
  #_ REGISTER_OUT f3 0x7FF0000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fmul_71_GEN:
  #_ REGISTER_IN f1 0xBFF0000000000000
  #_ REGISTER_IN f2 0xFFF8000000000000
  fmul f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xBFF0000000000000
  #_ REGISTER_OUT f2 0xFFF8000000000000
  #_ REGISTER_OUT f3 0xFFF8000000000000

test_fmul_71_cr_GEN:
  #_ REGISTER_IN f1 0xBFF0000000000000
  #_ REGISTER_IN f2 0xFFF8000000000000
  fmul. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xBFF0000000000000
  #_ REGISTER_OUT f2 0xFFF8000000000000
  #_ REGISTER_OUT f3 0xFFF8000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fmul_72_GEN:
  #_ REGISTER_IN f1 0xBFF0000000000000
  #_ REGISTER_IN f2 0xFFF4000000000000
  fmul f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xBFF0000000000000
  #_ REGISTER_OUT f2 0xFFF4000000000000
  #_ REGISTER_OUT f3 0xFFFC000000000000

test_fmul_72_cr_GEN:
  #_ REGISTER_IN f1 0xBFF0000000000000
  #_ REGISTER_IN f2 0xFFF4000000000000
  fmul. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xBFF0000000000000
  #_ REGISTER_OUT f2 0xFFF4000000000000
  #_ REGISTER_OUT f3 0xFFFC000000000000
  #_ REGISTER_OUT cr 0x0A000000

test_fmul_73_GEN:
  #_ REGISTER_IN f1 0xC1E0000000000000
  #_ REGISTER_IN f2 0x0000000000000000
  fmul f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xC1E0000000000000
  #_ REGISTER_OUT f2 0x0000000000000000
  #_ REGISTER_OUT f3 0x8000000000000000

test_fmul_73_cr_GEN:
  #_ REGISTER_IN f1 0xC1E0000000000000
  #_ REGISTER_IN f2 0x0000000000000000
  fmul. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xC1E0000000000000
  #_ REGISTER_OUT f2 0x0000000000000000
  #_ REGISTER_OUT f3 0x8000000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fmul_74_GEN:
  #_ REGISTER_IN f1 0xC1E0000000000000
  #_ REGISTER_IN f2 0x8000000000000000
  fmul f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xC1E0000000000000
  #_ REGISTER_OUT f2 0x8000000000000000
  #_ REGISTER_OUT f3 0x0000000000000000

test_fmul_74_cr_GEN:
  #_ REGISTER_IN f1 0xC1E0000000000000
  #_ REGISTER_IN f2 0x8000000000000000
  fmul. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xC1E0000000000000
  #_ REGISTER_OUT f2 0x8000000000000000
  #_ REGISTER_OUT f3 0x0000000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fmul_75_GEN:
  #_ REGISTER_IN f1 0xC1E0000000000000
  #_ REGISTER_IN f2 0x0000000000000001
  fmul f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xC1E0000000000000
  #_ REGISTER_OUT f2 0x0000000000000001
  #_ REGISTER_OUT f3 0x8000000080000000

test_fmul_75_cr_GEN:
  #_ REGISTER_IN f1 0xC1E0000000000000
  #_ REGISTER_IN f2 0x0000000000000001
  fmul. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xC1E0000000000000
  #_ REGISTER_OUT f2 0x0000000000000001
  #_ REGISTER_OUT f3 0x8000000080000000
  #_ REGISTER_OUT cr 0x00000000

test_fmul_76_GEN:
  #_ REGISTER_IN f1 0xC1E0000000000000
  #_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
  fmul f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xC1E0000000000000
  #_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
  #_ REGISTER_OUT f3 0x81FFFFFFFFFFFFFE

test_fmul_76_cr_GEN:
  #_ REGISTER_IN f1 0xC1E0000000000000
  #_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
  fmul. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xC1E0000000000000
  #_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
  #_ REGISTER_OUT f3 0x81FFFFFFFFFFFFFE
  #_ REGISTER_OUT cr 0x00000000

test_fmul_77_GEN:
  #_ REGISTER_IN f1 0xC1E0000000000000
  #_ REGISTER_IN f2 0x3FF0000000000000
  fmul f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xC1E0000000000000
  #_ REGISTER_OUT f2 0x3FF0000000000000
  #_ REGISTER_OUT f3 0xC1E0000000000000

test_fmul_77_cr_GEN:
  #_ REGISTER_IN f1 0xC1E0000000000000
  #_ REGISTER_IN f2 0x3FF0000000000000
  fmul. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xC1E0000000000000
  #_ REGISTER_OUT f2 0x3FF0000000000000
  #_ REGISTER_OUT f3 0xC1E0000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fmul_78_GEN:
  #_ REGISTER_IN f1 0xC1E0000000000000
  #_ REGISTER_IN f2 0xBFF0000000000000
  fmul f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xC1E0000000000000
  #_ REGISTER_OUT f2 0xBFF0000000000000
  #_ REGISTER_OUT f3 0x41E0000000000000

test_fmul_78_cr_GEN:
  #_ REGISTER_IN f1 0xC1E0000000000000
  #_ REGISTER_IN f2 0xBFF0000000000000
  fmul. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xC1E0000000000000
  #_ REGISTER_OUT f2 0xBFF0000000000000
  #_ REGISTER_OUT f3 0x41E0000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fmul_79_GEN:
  #_ REGISTER_IN f1 0xC1E0000000000000
  #_ REGISTER_IN f2 0xC1E0000000000000
  fmul f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xC1E0000000000000
  #_ REGISTER_OUT f2 0xC1E0000000000000
  #_ REGISTER_OUT f3 0x43D0000000000000

test_fmul_79_cr_GEN:
  #_ REGISTER_IN f1 0xC1E0000000000000
  #_ REGISTER_IN f2 0xC1E0000000000000
  fmul. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xC1E0000000000000
  #_ REGISTER_OUT f2 0xC1E0000000000000
  #_ REGISTER_OUT f3 0x43D0000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fmul_80_GEN:
  #_ REGISTER_IN f1 0xC1E0000000000000
  #_ REGISTER_IN f2 0x41DFFFFFFFC00000
  fmul f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xC1E0000000000000
  #_ REGISTER_OUT f2 0x41DFFFFFFFC00000
  #_ REGISTER_OUT f3 0xC3CFFFFFFFC00000

test_fmul_80_cr_GEN:
  #_ REGISTER_IN f1 0xC1E0000000000000
  #_ REGISTER_IN f2 0x41DFFFFFFFC00000
  fmul. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xC1E0000000000000
  #_ REGISTER_OUT f2 0x41DFFFFFFFC00000
  #_ REGISTER_OUT f3 0xC3CFFFFFFFC00000
  #_ REGISTER_OUT cr 0x00000000

test_fmul_81_GEN:
  #_ REGISTER_IN f1 0xC1E0000000000000
  #_ REGISTER_IN f2 0x7FF0000000000000
  fmul f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xC1E0000000000000
  #_ REGISTER_OUT f2 0x7FF0000000000000
  #_ REGISTER_OUT f3 0xFFF0000000000000

test_fmul_81_cr_GEN:
  #_ REGISTER_IN f1 0xC1E0000000000000
  #_ REGISTER_IN f2 0x7FF0000000000000
  fmul. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xC1E0000000000000
  #_ REGISTER_OUT f2 0x7FF0000000000000
  #_ REGISTER_OUT f3 0xFFF0000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fmul_82_GEN:
  #_ REGISTER_IN f1 0xC1E0000000000000
  #_ REGISTER_IN f2 0xFFF0000000000000
  fmul f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xC1E0000000000000
  #_ REGISTER_OUT f2 0xFFF0000000000000
  #_ REGISTER_OUT f3 0x7FF0000000000000

test_fmul_82_cr_GEN:
  #_ REGISTER_IN f1 0xC1E0000000000000
  #_ REGISTER_IN f2 0xFFF0000000000000
  fmul. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xC1E0000000000000
  #_ REGISTER_OUT f2 0xFFF0000000000000
  #_ REGISTER_OUT f3 0x7FF0000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fmul_83_GEN:
  #_ REGISTER_IN f1 0xC1E0000000000000
  #_ REGISTER_IN f2 0xFFF8000000000000
  fmul f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xC1E0000000000000
  #_ REGISTER_OUT f2 0xFFF8000000000000
  #_ REGISTER_OUT f3 0xFFF8000000000000

test_fmul_83_cr_GEN:
  #_ REGISTER_IN f1 0xC1E0000000000000
  #_ REGISTER_IN f2 0xFFF8000000000000
  fmul. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xC1E0000000000000
  #_ REGISTER_OUT f2 0xFFF8000000000000
  #_ REGISTER_OUT f3 0xFFF8000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fmul_84_GEN:
  #_ REGISTER_IN f1 0xC1E0000000000000
  #_ REGISTER_IN f2 0xFFF4000000000000
  fmul f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xC1E0000000000000
  #_ REGISTER_OUT f2 0xFFF4000000000000
  #_ REGISTER_OUT f3 0xFFFC000000000000

test_fmul_84_cr_GEN:
  #_ REGISTER_IN f1 0xC1E0000000000000
  #_ REGISTER_IN f2 0xFFF4000000000000
  fmul. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xC1E0000000000000
  #_ REGISTER_OUT f2 0xFFF4000000000000
  #_ REGISTER_OUT f3 0xFFFC000000000000
  #_ REGISTER_OUT cr 0x0A000000

test_fmul_85_GEN:
  #_ REGISTER_IN f1 0x41DFFFFFFFC00000
  #_ REGISTER_IN f2 0x0000000000000000
  fmul f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x41DFFFFFFFC00000
  #_ REGISTER_OUT f2 0x0000000000000000
  #_ REGISTER_OUT f3 0x0000000000000000

test_fmul_85_cr_GEN:
  #_ REGISTER_IN f1 0x41DFFFFFFFC00000
  #_ REGISTER_IN f2 0x0000000000000000
  fmul. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x41DFFFFFFFC00000
  #_ REGISTER_OUT f2 0x0000000000000000
  #_ REGISTER_OUT f3 0x0000000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fmul_86_GEN:
  #_ REGISTER_IN f1 0x41DFFFFFFFC00000
  #_ REGISTER_IN f2 0x8000000000000000
  fmul f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x41DFFFFFFFC00000
  #_ REGISTER_OUT f2 0x8000000000000000
  #_ REGISTER_OUT f3 0x8000000000000000

test_fmul_86_cr_GEN:
  #_ REGISTER_IN f1 0x41DFFFFFFFC00000
  #_ REGISTER_IN f2 0x8000000000000000
  fmul. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x41DFFFFFFFC00000
  #_ REGISTER_OUT f2 0x8000000000000000
  #_ REGISTER_OUT f3 0x8000000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fmul_87_GEN:
  #_ REGISTER_IN f1 0x41DFFFFFFFC00000
  #_ REGISTER_IN f2 0x0000000000000001
  fmul f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x41DFFFFFFFC00000
  #_ REGISTER_OUT f2 0x0000000000000001
  #_ REGISTER_OUT f3 0x000000007FFFFFFF

test_fmul_87_cr_GEN:
  #_ REGISTER_IN f1 0x41DFFFFFFFC00000
  #_ REGISTER_IN f2 0x0000000000000001
  fmul. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x41DFFFFFFFC00000
  #_ REGISTER_OUT f2 0x0000000000000001
  #_ REGISTER_OUT f3 0x000000007FFFFFFF
  #_ REGISTER_OUT cr 0x00000000

test_fmul_88_GEN:
  #_ REGISTER_IN f1 0x41DFFFFFFFC00000
  #_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
  fmul f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x41DFFFFFFFC00000
  #_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
  #_ REGISTER_OUT f3 0x01FFFFFFFFBFFFFE

test_fmul_88_cr_GEN:
  #_ REGISTER_IN f1 0x41DFFFFFFFC00000
  #_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
  fmul. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x41DFFFFFFFC00000
  #_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
  #_ REGISTER_OUT f3 0x01FFFFFFFFBFFFFE
  #_ REGISTER_OUT cr 0x08000000

test_fmul_89_GEN:
  #_ REGISTER_IN f1 0x41DFFFFFFFC00000
  #_ REGISTER_IN f2 0x3FF0000000000000
  fmul f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x41DFFFFFFFC00000
  #_ REGISTER_OUT f2 0x3FF0000000000000
  #_ REGISTER_OUT f3 0x41DFFFFFFFC00000

test_fmul_89_cr_GEN:
  #_ REGISTER_IN f1 0x41DFFFFFFFC00000
  #_ REGISTER_IN f2 0x3FF0000000000000
  fmul. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x41DFFFFFFFC00000
  #_ REGISTER_OUT f2 0x3FF0000000000000
  #_ REGISTER_OUT f3 0x41DFFFFFFFC00000
  #_ REGISTER_OUT cr 0x00000000

test_fmul_90_GEN:
  #_ REGISTER_IN f1 0x41DFFFFFFFC00000
  #_ REGISTER_IN f2 0xBFF0000000000000
  fmul f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x41DFFFFFFFC00000
  #_ REGISTER_OUT f2 0xBFF0000000000000
  #_ REGISTER_OUT f3 0xC1DFFFFFFFC00000

test_fmul_90_cr_GEN:
  #_ REGISTER_IN f1 0x41DFFFFFFFC00000
  #_ REGISTER_IN f2 0xBFF0000000000000
  fmul. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x41DFFFFFFFC00000
  #_ REGISTER_OUT f2 0xBFF0000000000000
  #_ REGISTER_OUT f3 0xC1DFFFFFFFC00000
  #_ REGISTER_OUT cr 0x00000000

test_fmul_91_GEN:
  #_ REGISTER_IN f1 0x41DFFFFFFFC00000
  #_ REGISTER_IN f2 0xC1E0000000000000
  fmul f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x41DFFFFFFFC00000
  #_ REGISTER_OUT f2 0xC1E0000000000000
  #_ REGISTER_OUT f3 0xC3CFFFFFFFC00000

test_fmul_91_cr_GEN:
  #_ REGISTER_IN f1 0x41DFFFFFFFC00000
  #_ REGISTER_IN f2 0xC1E0000000000000
  fmul. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x41DFFFFFFFC00000
  #_ REGISTER_OUT f2 0xC1E0000000000000
  #_ REGISTER_OUT f3 0xC3CFFFFFFFC00000
  #_ REGISTER_OUT cr 0x00000000

test_fmul_92_GEN:
  #_ REGISTER_IN f1 0x41DFFFFFFFC00000
  #_ REGISTER_IN f2 0x41DFFFFFFFC00000
  fmul f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x41DFFFFFFFC00000
  #_ REGISTER_OUT f2 0x41DFFFFFFFC00000
  #_ REGISTER_OUT f3 0x43CFFFFFFF800000

test_fmul_92_cr_GEN:
  #_ REGISTER_IN f1 0x41DFFFFFFFC00000
  #_ REGISTER_IN f2 0x41DFFFFFFFC00000
  fmul. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x41DFFFFFFFC00000
  #_ REGISTER_OUT f2 0x41DFFFFFFFC00000
  #_ REGISTER_OUT f3 0x43CFFFFFFF800000
  #_ REGISTER_OUT cr 0x08000000

test_fmul_93_GEN:
  #_ REGISTER_IN f1 0x41DFFFFFFFC00000
  #_ REGISTER_IN f2 0x7FF0000000000000
  fmul f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x41DFFFFFFFC00000
  #_ REGISTER_OUT f2 0x7FF0000000000000
  #_ REGISTER_OUT f3 0x7FF0000000000000

test_fmul_93_cr_GEN:
  #_ REGISTER_IN f1 0x41DFFFFFFFC00000
  #_ REGISTER_IN f2 0x7FF0000000000000
  fmul. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x41DFFFFFFFC00000
  #_ REGISTER_OUT f2 0x7FF0000000000000
  #_ REGISTER_OUT f3 0x7FF0000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fmul_94_GEN:
  #_ REGISTER_IN f1 0x41DFFFFFFFC00000
  #_ REGISTER_IN f2 0xFFF0000000000000
  fmul f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x41DFFFFFFFC00000
  #_ REGISTER_OUT f2 0xFFF0000000000000
  #_ REGISTER_OUT f3 0xFFF0000000000000

test_fmul_94_cr_GEN:
  #_ REGISTER_IN f1 0x41DFFFFFFFC00000
  #_ REGISTER_IN f2 0xFFF0000000000000
  fmul. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x41DFFFFFFFC00000
  #_ REGISTER_OUT f2 0xFFF0000000000000
  #_ REGISTER_OUT f3 0xFFF0000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fmul_95_GEN:
  #_ REGISTER_IN f1 0x41DFFFFFFFC00000
  #_ REGISTER_IN f2 0xFFF8000000000000
  fmul f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x41DFFFFFFFC00000
  #_ REGISTER_OUT f2 0xFFF8000000000000
  #_ REGISTER_OUT f3 0xFFF8000000000000

test_fmul_95_cr_GEN:
  #_ REGISTER_IN f1 0x41DFFFFFFFC00000
  #_ REGISTER_IN f2 0xFFF8000000000000
  fmul. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x41DFFFFFFFC00000
  #_ REGISTER_OUT f2 0xFFF8000000000000
  #_ REGISTER_OUT f3 0xFFF8000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fmul_96_GEN:
  #_ REGISTER_IN f1 0x41DFFFFFFFC00000
  #_ REGISTER_IN f2 0xFFF4000000000000
  fmul f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x41DFFFFFFFC00000
  #_ REGISTER_OUT f2 0xFFF4000000000000
  #_ REGISTER_OUT f3 0xFFFC000000000000

test_fmul_96_cr_GEN:
  #_ REGISTER_IN f1 0x41DFFFFFFFC00000
  #_ REGISTER_IN f2 0xFFF4000000000000
  fmul. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x41DFFFFFFFC00000
  #_ REGISTER_OUT f2 0xFFF4000000000000
  #_ REGISTER_OUT f3 0xFFFC000000000000
  #_ REGISTER_OUT cr 0x0A000000

test_fmul_97_GEN:
  #_ REGISTER_IN f1 0x7FF0000000000000
  #_ REGISTER_IN f2 0x0000000000000000
  fmul f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x7FF0000000000000
  #_ REGISTER_OUT f2 0x0000000000000000
  #_ REGISTER_OUT f3 0x7FF8000000000000

test_fmul_97_cr_GEN:
  #_ REGISTER_IN f1 0x7FF0000000000000
  #_ REGISTER_IN f2 0x0000000000000000
  fmul. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x7FF0000000000000
  #_ REGISTER_OUT f2 0x0000000000000000
  #_ REGISTER_OUT f3 0x7FF8000000000000
  #_ REGISTER_OUT cr 0x0A000000

test_fmul_98_GEN:
  #_ REGISTER_IN f1 0x7FF0000000000000
  #_ REGISTER_IN f2 0x8000000000000000
  fmul f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x7FF0000000000000
  #_ REGISTER_OUT f2 0x8000000000000000
  #_ REGISTER_OUT f3 0x7FF8000000000000

test_fmul_98_cr_GEN:
  #_ REGISTER_IN f1 0x7FF0000000000000
  #_ REGISTER_IN f2 0x8000000000000000
  fmul. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x7FF0000000000000
  #_ REGISTER_OUT f2 0x8000000000000000
  #_ REGISTER_OUT f3 0x7FF8000000000000
  #_ REGISTER_OUT cr 0x0A000000

test_fmul_99_GEN:
  #_ REGISTER_IN f1 0x7FF0000000000000
  #_ REGISTER_IN f2 0x0000000000000001
  fmul f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x7FF0000000000000
  #_ REGISTER_OUT f2 0x0000000000000001
  #_ REGISTER_OUT f3 0x7FF0000000000000

test_fmul_99_cr_GEN:
  #_ REGISTER_IN f1 0x7FF0000000000000
  #_ REGISTER_IN f2 0x0000000000000001
  fmul. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x7FF0000000000000
  #_ REGISTER_OUT f2 0x0000000000000001
  #_ REGISTER_OUT f3 0x7FF0000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fmul_100_GEN:
  #_ REGISTER_IN f1 0x7FF0000000000000
  #_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
  fmul f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x7FF0000000000000
  #_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
  #_ REGISTER_OUT f3 0x7FF0000000000000

test_fmul_100_cr_GEN:
  #_ REGISTER_IN f1 0x7FF0000000000000
  #_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
  fmul. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x7FF0000000000000
  #_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
  #_ REGISTER_OUT f3 0x7FF0000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fmul_101_GEN:
  #_ REGISTER_IN f1 0x7FF0000000000000
  #_ REGISTER_IN f2 0x3FF0000000000000
  fmul f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x7FF0000000000000
  #_ REGISTER_OUT f2 0x3FF0000000000000
  #_ REGISTER_OUT f3 0x7FF0000000000000

test_fmul_101_cr_GEN:
  #_ REGISTER_IN f1 0x7FF0000000000000
  #_ REGISTER_IN f2 0x3FF0000000000000
  fmul. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x7FF0000000000000
  #_ REGISTER_OUT f2 0x3FF0000000000000
  #_ REGISTER_OUT f3 0x7FF0000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fmul_102_GEN:
  #_ REGISTER_IN f1 0x7FF0000000000000
  #_ REGISTER_IN f2 0xBFF0000000000000
  fmul f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x7FF0000000000000
  #_ REGISTER_OUT f2 0xBFF0000000000000
  #_ REGISTER_OUT f3 0xFFF0000000000000

test_fmul_102_cr_GEN:
  #_ REGISTER_IN f1 0x7FF0000000000000
  #_ REGISTER_IN f2 0xBFF0000000000000
  fmul. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x7FF0000000000000
  #_ REGISTER_OUT f2 0xBFF0000000000000
  #_ REGISTER_OUT f3 0xFFF0000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fmul_103_GEN:
  #_ REGISTER_IN f1 0x7FF0000000000000
  #_ REGISTER_IN f2 0xC1E0000000000000
  fmul f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x7FF0000000000000
  #_ REGISTER_OUT f2 0xC1E0000000000000
  #_ REGISTER_OUT f3 0xFFF0000000000000

test_fmul_103_cr_GEN:
  #_ REGISTER_IN f1 0x7FF0000000000000
  #_ REGISTER_IN f2 0xC1E0000000000000
  fmul. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x7FF0000000000000
  #_ REGISTER_OUT f2 0xC1E0000000000000
  #_ REGISTER_OUT f3 0xFFF0000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fmul_104_GEN:
  #_ REGISTER_IN f1 0x7FF0000000000000
  #_ REGISTER_IN f2 0x41DFFFFFFFC00000
  fmul f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x7FF0000000000000
  #_ REGISTER_OUT f2 0x41DFFFFFFFC00000
  #_ REGISTER_OUT f3 0x7FF0000000000000

test_fmul_104_cr_GEN:
  #_ REGISTER_IN f1 0x7FF0000000000000
  #_ REGISTER_IN f2 0x41DFFFFFFFC00000
  fmul. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x7FF0000000000000
  #_ REGISTER_OUT f2 0x41DFFFFFFFC00000
  #_ REGISTER_OUT f3 0x7FF0000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fmul_105_GEN:
  #_ REGISTER_IN f1 0x7FF0000000000000
  #_ REGISTER_IN f2 0x7FF0000000000000
  fmul f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x7FF0000000000000
  #_ REGISTER_OUT f2 0x7FF0000000000000
  #_ REGISTER_OUT f3 0x7FF0000000000000

test_fmul_105_cr_GEN:
  #_ REGISTER_IN f1 0x7FF0000000000000
  #_ REGISTER_IN f2 0x7FF0000000000000
  fmul. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x7FF0000000000000
  #_ REGISTER_OUT f2 0x7FF0000000000000
  #_ REGISTER_OUT f3 0x7FF0000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fmul_106_GEN:
  #_ REGISTER_IN f1 0x7FF0000000000000
  #_ REGISTER_IN f2 0xFFF0000000000000
  fmul f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x7FF0000000000000
  #_ REGISTER_OUT f2 0xFFF0000000000000
  #_ REGISTER_OUT f3 0xFFF0000000000000

test_fmul_106_cr_GEN:
  #_ REGISTER_IN f1 0x7FF0000000000000
  #_ REGISTER_IN f2 0xFFF0000000000000
  fmul. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x7FF0000000000000
  #_ REGISTER_OUT f2 0xFFF0000000000000
  #_ REGISTER_OUT f3 0xFFF0000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fmul_107_GEN:
  #_ REGISTER_IN f1 0x7FF0000000000000
  #_ REGISTER_IN f2 0xFFF8000000000000
  fmul f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x7FF0000000000000
  #_ REGISTER_OUT f2 0xFFF8000000000000
  #_ REGISTER_OUT f3 0xFFF8000000000000

test_fmul_107_cr_GEN:
  #_ REGISTER_IN f1 0x7FF0000000000000
  #_ REGISTER_IN f2 0xFFF8000000000000
  fmul. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x7FF0000000000000
  #_ REGISTER_OUT f2 0xFFF8000000000000
  #_ REGISTER_OUT f3 0xFFF8000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fmul_108_GEN:
  #_ REGISTER_IN f1 0x7FF0000000000000
  #_ REGISTER_IN f2 0xFFF4000000000000
  fmul f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x7FF0000000000000
  #_ REGISTER_OUT f2 0xFFF4000000000000
  #_ REGISTER_OUT f3 0xFFFC000000000000

test_fmul_108_cr_GEN:
  #_ REGISTER_IN f1 0x7FF0000000000000
  #_ REGISTER_IN f2 0xFFF4000000000000
  fmul. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0x7FF0000000000000
  #_ REGISTER_OUT f2 0xFFF4000000000000
  #_ REGISTER_OUT f3 0xFFFC000000000000
  #_ REGISTER_OUT cr 0x0A000000

test_fmul_109_GEN:
  #_ REGISTER_IN f1 0xFFF0000000000000
  #_ REGISTER_IN f2 0x0000000000000000
  fmul f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF0000000000000
  #_ REGISTER_OUT f2 0x0000000000000000
  #_ REGISTER_OUT f3 0x7FF8000000000000

test_fmul_109_cr_GEN:
  #_ REGISTER_IN f1 0xFFF0000000000000
  #_ REGISTER_IN f2 0x0000000000000000
  fmul. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF0000000000000
  #_ REGISTER_OUT f2 0x0000000000000000
  #_ REGISTER_OUT f3 0x7FF8000000000000
  #_ REGISTER_OUT cr 0x0A000000

test_fmul_110_GEN:
  #_ REGISTER_IN f1 0xFFF0000000000000
  #_ REGISTER_IN f2 0x8000000000000000
  fmul f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF0000000000000
  #_ REGISTER_OUT f2 0x8000000000000000
  #_ REGISTER_OUT f3 0x7FF8000000000000

test_fmul_110_cr_GEN:
  #_ REGISTER_IN f1 0xFFF0000000000000
  #_ REGISTER_IN f2 0x8000000000000000
  fmul. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF0000000000000
  #_ REGISTER_OUT f2 0x8000000000000000
  #_ REGISTER_OUT f3 0x7FF8000000000000
  #_ REGISTER_OUT cr 0x0A000000

test_fmul_111_GEN:
  #_ REGISTER_IN f1 0xFFF0000000000000
  #_ REGISTER_IN f2 0x0000000000000001
  fmul f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF0000000000000
  #_ REGISTER_OUT f2 0x0000000000000001
  #_ REGISTER_OUT f3 0xFFF0000000000000

test_fmul_111_cr_GEN:
  #_ REGISTER_IN f1 0xFFF0000000000000
  #_ REGISTER_IN f2 0x0000000000000001
  fmul. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF0000000000000
  #_ REGISTER_OUT f2 0x0000000000000001
  #_ REGISTER_OUT f3 0xFFF0000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fmul_112_GEN:
  #_ REGISTER_IN f1 0xFFF0000000000000
  #_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
  fmul f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF0000000000000
  #_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
  #_ REGISTER_OUT f3 0xFFF0000000000000

test_fmul_112_cr_GEN:
  #_ REGISTER_IN f1 0xFFF0000000000000
  #_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
  fmul. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF0000000000000
  #_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
  #_ REGISTER_OUT f3 0xFFF0000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fmul_113_GEN:
  #_ REGISTER_IN f1 0xFFF0000000000000
  #_ REGISTER_IN f2 0x3FF0000000000000
  fmul f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF0000000000000
  #_ REGISTER_OUT f2 0x3FF0000000000000
  #_ REGISTER_OUT f3 0xFFF0000000000000

test_fmul_113_cr_GEN:
  #_ REGISTER_IN f1 0xFFF0000000000000
  #_ REGISTER_IN f2 0x3FF0000000000000
  fmul. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF0000000000000
  #_ REGISTER_OUT f2 0x3FF0000000000000
  #_ REGISTER_OUT f3 0xFFF0000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fmul_114_GEN:
  #_ REGISTER_IN f1 0xFFF0000000000000
  #_ REGISTER_IN f2 0xBFF0000000000000
  fmul f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF0000000000000
  #_ REGISTER_OUT f2 0xBFF0000000000000
  #_ REGISTER_OUT f3 0x7FF0000000000000

test_fmul_114_cr_GEN:
  #_ REGISTER_IN f1 0xFFF0000000000000
  #_ REGISTER_IN f2 0xBFF0000000000000
  fmul. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF0000000000000
  #_ REGISTER_OUT f2 0xBFF0000000000000
  #_ REGISTER_OUT f3 0x7FF0000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fmul_115_GEN:
  #_ REGISTER_IN f1 0xFFF0000000000000
  #_ REGISTER_IN f2 0xC1E0000000000000
  fmul f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF0000000000000
  #_ REGISTER_OUT f2 0xC1E0000000000000
  #_ REGISTER_OUT f3 0x7FF0000000000000

test_fmul_115_cr_GEN:
  #_ REGISTER_IN f1 0xFFF0000000000000
  #_ REGISTER_IN f2 0xC1E0000000000000
  fmul. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF0000000000000
  #_ REGISTER_OUT f2 0xC1E0000000000000
  #_ REGISTER_OUT f3 0x7FF0000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fmul_116_GEN:
  #_ REGISTER_IN f1 0xFFF0000000000000
  #_ REGISTER_IN f2 0x41DFFFFFFFC00000
  fmul f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF0000000000000
  #_ REGISTER_OUT f2 0x41DFFFFFFFC00000
  #_ REGISTER_OUT f3 0xFFF0000000000000

test_fmul_116_cr_GEN:
  #_ REGISTER_IN f1 0xFFF0000000000000
  #_ REGISTER_IN f2 0x41DFFFFFFFC00000
  fmul. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF0000000000000
  #_ REGISTER_OUT f2 0x41DFFFFFFFC00000
  #_ REGISTER_OUT f3 0xFFF0000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fmul_117_GEN:
  #_ REGISTER_IN f1 0xFFF0000000000000
  #_ REGISTER_IN f2 0x7FF0000000000000
  fmul f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF0000000000000
  #_ REGISTER_OUT f2 0x7FF0000000000000
  #_ REGISTER_OUT f3 0xFFF0000000000000

test_fmul_117_cr_GEN:
  #_ REGISTER_IN f1 0xFFF0000000000000
  #_ REGISTER_IN f2 0x7FF0000000000000
  fmul. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF0000000000000
  #_ REGISTER_OUT f2 0x7FF0000000000000
  #_ REGISTER_OUT f3 0xFFF0000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fmul_118_GEN:
  #_ REGISTER_IN f1 0xFFF0000000000000
  #_ REGISTER_IN f2 0xFFF0000000000000
  fmul f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF0000000000000
  #_ REGISTER_OUT f2 0xFFF0000000000000
  #_ REGISTER_OUT f3 0x7FF0000000000000

test_fmul_118_cr_GEN:
  #_ REGISTER_IN f1 0xFFF0000000000000
  #_ REGISTER_IN f2 0xFFF0000000000000
  fmul. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF0000000000000
  #_ REGISTER_OUT f2 0xFFF0000000000000
  #_ REGISTER_OUT f3 0x7FF0000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fmul_119_GEN:
  #_ REGISTER_IN f1 0xFFF0000000000000
  #_ REGISTER_IN f2 0xFFF8000000000000
  fmul f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF0000000000000
  #_ REGISTER_OUT f2 0xFFF8000000000000
  #_ REGISTER_OUT f3 0xFFF8000000000000

test_fmul_119_cr_GEN:
  #_ REGISTER_IN f1 0xFFF0000000000000
  #_ REGISTER_IN f2 0xFFF8000000000000
  fmul. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF0000000000000
  #_ REGISTER_OUT f2 0xFFF8000000000000
  #_ REGISTER_OUT f3 0xFFF8000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fmul_120_GEN:
  #_ REGISTER_IN f1 0xFFF0000000000000
  #_ REGISTER_IN f2 0xFFF4000000000000
  fmul f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF0000000000000
  #_ REGISTER_OUT f2 0xFFF4000000000000
  #_ REGISTER_OUT f3 0xFFFC000000000000

test_fmul_120_cr_GEN:
  #_ REGISTER_IN f1 0xFFF0000000000000
  #_ REGISTER_IN f2 0xFFF4000000000000
  fmul. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF0000000000000
  #_ REGISTER_OUT f2 0xFFF4000000000000
  #_ REGISTER_OUT f3 0xFFFC000000000000
  #_ REGISTER_OUT cr 0x0A000000

test_fmul_121_GEN:
  #_ REGISTER_IN f1 0xFFF8000000000000
  #_ REGISTER_IN f2 0x0000000000000000
  fmul f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF8000000000000
  #_ REGISTER_OUT f2 0x0000000000000000
  #_ REGISTER_OUT f3 0xFFF8000000000000

test_fmul_121_cr_GEN:
  #_ REGISTER_IN f1 0xFFF8000000000000
  #_ REGISTER_IN f2 0x0000000000000000
  fmul. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF8000000000000
  #_ REGISTER_OUT f2 0x0000000000000000
  #_ REGISTER_OUT f3 0xFFF8000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fmul_122_GEN:
  #_ REGISTER_IN f1 0xFFF8000000000000
  #_ REGISTER_IN f2 0x8000000000000000
  fmul f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF8000000000000
  #_ REGISTER_OUT f2 0x8000000000000000
  #_ REGISTER_OUT f3 0xFFF8000000000000

test_fmul_122_cr_GEN:
  #_ REGISTER_IN f1 0xFFF8000000000000
  #_ REGISTER_IN f2 0x8000000000000000
  fmul. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF8000000000000
  #_ REGISTER_OUT f2 0x8000000000000000
  #_ REGISTER_OUT f3 0xFFF8000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fmul_123_GEN:
  #_ REGISTER_IN f1 0xFFF8000000000000
  #_ REGISTER_IN f2 0x0000000000000001
  fmul f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF8000000000000
  #_ REGISTER_OUT f2 0x0000000000000001
  #_ REGISTER_OUT f3 0xFFF8000000000000

test_fmul_123_cr_GEN:
  #_ REGISTER_IN f1 0xFFF8000000000000
  #_ REGISTER_IN f2 0x0000000000000001
  fmul. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF8000000000000
  #_ REGISTER_OUT f2 0x0000000000000001
  #_ REGISTER_OUT f3 0xFFF8000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fmul_124_GEN:
  #_ REGISTER_IN f1 0xFFF8000000000000
  #_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
  fmul f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF8000000000000
  #_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
  #_ REGISTER_OUT f3 0xFFF8000000000000

test_fmul_124_cr_GEN:
  #_ REGISTER_IN f1 0xFFF8000000000000
  #_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
  fmul. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF8000000000000
  #_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
  #_ REGISTER_OUT f3 0xFFF8000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fmul_125_GEN:
  #_ REGISTER_IN f1 0xFFF8000000000000
  #_ REGISTER_IN f2 0x3FF0000000000000
  fmul f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF8000000000000
  #_ REGISTER_OUT f2 0x3FF0000000000000
  #_ REGISTER_OUT f3 0xFFF8000000000000

test_fmul_125_cr_GEN:
  #_ REGISTER_IN f1 0xFFF8000000000000
  #_ REGISTER_IN f2 0x3FF0000000000000
  fmul. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF8000000000000
  #_ REGISTER_OUT f2 0x3FF0000000000000
  #_ REGISTER_OUT f3 0xFFF8000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fmul_126_GEN:
  #_ REGISTER_IN f1 0xFFF8000000000000
  #_ REGISTER_IN f2 0xBFF0000000000000
  fmul f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF8000000000000
  #_ REGISTER_OUT f2 0xBFF0000000000000
  #_ REGISTER_OUT f3 0xFFF8000000000000

test_fmul_126_cr_GEN:
  #_ REGISTER_IN f1 0xFFF8000000000000
  #_ REGISTER_IN f2 0xBFF0000000000000
  fmul. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF8000000000000
  #_ REGISTER_OUT f2 0xBFF0000000000000
  #_ REGISTER_OUT f3 0xFFF8000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fmul_127_GEN:
  #_ REGISTER_IN f1 0xFFF8000000000000
  #_ REGISTER_IN f2 0xC1E0000000000000
  fmul f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF8000000000000
  #_ REGISTER_OUT f2 0xC1E0000000000000
  #_ REGISTER_OUT f3 0xFFF8000000000000

test_fmul_127_cr_GEN:
  #_ REGISTER_IN f1 0xFFF8000000000000
  #_ REGISTER_IN f2 0xC1E0000000000000
  fmul. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF8000000000000
  #_ REGISTER_OUT f2 0xC1E0000000000000
  #_ REGISTER_OUT f3 0xFFF8000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fmul_128_GEN:
  #_ REGISTER_IN f1 0xFFF8000000000000
  #_ REGISTER_IN f2 0x41DFFFFFFFC00000
  fmul f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF8000000000000
  #_ REGISTER_OUT f2 0x41DFFFFFFFC00000
  #_ REGISTER_OUT f3 0xFFF8000000000000

test_fmul_128_cr_GEN:
  #_ REGISTER_IN f1 0xFFF8000000000000
  #_ REGISTER_IN f2 0x41DFFFFFFFC00000
  fmul. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF8000000000000
  #_ REGISTER_OUT f2 0x41DFFFFFFFC00000
  #_ REGISTER_OUT f3 0xFFF8000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fmul_129_GEN:
  #_ REGISTER_IN f1 0xFFF8000000000000
  #_ REGISTER_IN f2 0x7FF0000000000000
  fmul f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF8000000000000
  #_ REGISTER_OUT f2 0x7FF0000000000000
  #_ REGISTER_OUT f3 0xFFF8000000000000

test_fmul_129_cr_GEN:
  #_ REGISTER_IN f1 0xFFF8000000000000
  #_ REGISTER_IN f2 0x7FF0000000000000
  fmul. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF8000000000000
  #_ REGISTER_OUT f2 0x7FF0000000000000
  #_ REGISTER_OUT f3 0xFFF8000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fmul_130_GEN:
  #_ REGISTER_IN f1 0xFFF8000000000000
  #_ REGISTER_IN f2 0xFFF0000000000000
  fmul f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF8000000000000
  #_ REGISTER_OUT f2 0xFFF0000000000000
  #_ REGISTER_OUT f3 0xFFF8000000000000

test_fmul_130_cr_GEN:
  #_ REGISTER_IN f1 0xFFF8000000000000
  #_ REGISTER_IN f2 0xFFF0000000000000
  fmul. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF8000000000000
  #_ REGISTER_OUT f2 0xFFF0000000000000
  #_ REGISTER_OUT f3 0xFFF8000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fmul_131_GEN:
  #_ REGISTER_IN f1 0xFFF8000000000000
  #_ REGISTER_IN f2 0xFFF8000000000000
  fmul f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF8000000000000
  #_ REGISTER_OUT f2 0xFFF8000000000000
  #_ REGISTER_OUT f3 0xFFF8000000000000

test_fmul_131_cr_GEN:
  #_ REGISTER_IN f1 0xFFF8000000000000
  #_ REGISTER_IN f2 0xFFF8000000000000
  fmul. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF8000000000000
  #_ REGISTER_OUT f2 0xFFF8000000000000
  #_ REGISTER_OUT f3 0xFFF8000000000000
  #_ REGISTER_OUT cr 0x00000000

test_fmul_132_GEN:
  #_ REGISTER_IN f1 0xFFF8000000000000
  #_ REGISTER_IN f2 0xFFF4000000000000
  fmul f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF8000000000000
  #_ REGISTER_OUT f2 0xFFF4000000000000
  #_ REGISTER_OUT f3 0xFFF8000000000000

test_fmul_132_cr_GEN:
  #_ REGISTER_IN f1 0xFFF8000000000000
  #_ REGISTER_IN f2 0xFFF4000000000000
  fmul. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF8000000000000
  #_ REGISTER_OUT f2 0xFFF4000000000000
  #_ REGISTER_OUT f3 0xFFF8000000000000
  #_ REGISTER_OUT cr 0x0A000000

test_fmul_133_GEN:
  #_ REGISTER_IN f1 0xFFF4000000000000
  #_ REGISTER_IN f2 0x0000000000000000
  fmul f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF4000000000000
  #_ REGISTER_OUT f2 0x0000000000000000
  #_ REGISTER_OUT f3 0xFFFC000000000000

test_fmul_133_cr_GEN:
  #_ REGISTER_IN f1 0xFFF4000000000000
  #_ REGISTER_IN f2 0x0000000000000000
  fmul. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF4000000000000
  #_ REGISTER_OUT f2 0x0000000000000000
  #_ REGISTER_OUT f3 0xFFFC000000000000
  #_ REGISTER_OUT cr 0x0A000000

test_fmul_134_GEN:
  #_ REGISTER_IN f1 0xFFF4000000000000
  #_ REGISTER_IN f2 0x8000000000000000
  fmul f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF4000000000000
  #_ REGISTER_OUT f2 0x8000000000000000
  #_ REGISTER_OUT f3 0xFFFC000000000000

test_fmul_134_cr_GEN:
  #_ REGISTER_IN f1 0xFFF4000000000000
  #_ REGISTER_IN f2 0x8000000000000000
  fmul. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF4000000000000
  #_ REGISTER_OUT f2 0x8000000000000000
  #_ REGISTER_OUT f3 0xFFFC000000000000
  #_ REGISTER_OUT cr 0x0A000000

test_fmul_135_GEN:
  #_ REGISTER_IN f1 0xFFF4000000000000
  #_ REGISTER_IN f2 0x0000000000000001
  fmul f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF4000000000000
  #_ REGISTER_OUT f2 0x0000000000000001
  #_ REGISTER_OUT f3 0xFFFC000000000000

test_fmul_135_cr_GEN:
  #_ REGISTER_IN f1 0xFFF4000000000000
  #_ REGISTER_IN f2 0x0000000000000001
  fmul. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF4000000000000
  #_ REGISTER_OUT f2 0x0000000000000001
  #_ REGISTER_OUT f3 0xFFFC000000000000
  #_ REGISTER_OUT cr 0x0A000000

test_fmul_136_GEN:
  #_ REGISTER_IN f1 0xFFF4000000000000
  #_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
  fmul f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF4000000000000
  #_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
  #_ REGISTER_OUT f3 0xFFFC000000000000

test_fmul_136_cr_GEN:
  #_ REGISTER_IN f1 0xFFF4000000000000
  #_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
  fmul. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF4000000000000
  #_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
  #_ REGISTER_OUT f3 0xFFFC000000000000
  #_ REGISTER_OUT cr 0x0A000000

test_fmul_137_GEN:
  #_ REGISTER_IN f1 0xFFF4000000000000
  #_ REGISTER_IN f2 0x3FF0000000000000
  fmul f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF4000000000000
  #_ REGISTER_OUT f2 0x3FF0000000000000
  #_ REGISTER_OUT f3 0xFFFC000000000000

test_fmul_137_cr_GEN:
  #_ REGISTER_IN f1 0xFFF4000000000000
  #_ REGISTER_IN f2 0x3FF0000000000000
  fmul. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF4000000000000
  #_ REGISTER_OUT f2 0x3FF0000000000000
  #_ REGISTER_OUT f3 0xFFFC000000000000
  #_ REGISTER_OUT cr 0x0A000000

test_fmul_138_GEN:
  #_ REGISTER_IN f1 0xFFF4000000000000
  #_ REGISTER_IN f2 0xBFF0000000000000
  fmul f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF4000000000000
  #_ REGISTER_OUT f2 0xBFF0000000000000
  #_ REGISTER_OUT f3 0xFFFC000000000000

test_fmul_138_cr_GEN:
  #_ REGISTER_IN f1 0xFFF4000000000000
  #_ REGISTER_IN f2 0xBFF0000000000000
  fmul. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF4000000000000
  #_ REGISTER_OUT f2 0xBFF0000000000000
  #_ REGISTER_OUT f3 0xFFFC000000000000
  #_ REGISTER_OUT cr 0x0A000000

test_fmul_139_GEN:
  #_ REGISTER_IN f1 0xFFF4000000000000
  #_ REGISTER_IN f2 0xC1E0000000000000
  fmul f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF4000000000000
  #_ REGISTER_OUT f2 0xC1E0000000000000
  #_ REGISTER_OUT f3 0xFFFC000000000000

test_fmul_139_cr_GEN:
  #_ REGISTER_IN f1 0xFFF4000000000000
  #_ REGISTER_IN f2 0xC1E0000000000000
  fmul. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF4000000000000
  #_ REGISTER_OUT f2 0xC1E0000000000000
  #_ REGISTER_OUT f3 0xFFFC000000000000
  #_ REGISTER_OUT cr 0x0A000000

test_fmul_140_GEN:
  #_ REGISTER_IN f1 0xFFF4000000000000
  #_ REGISTER_IN f2 0x41DFFFFFFFC00000
  fmul f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF4000000000000
  #_ REGISTER_OUT f2 0x41DFFFFFFFC00000
  #_ REGISTER_OUT f3 0xFFFC000000000000

test_fmul_140_cr_GEN:
  #_ REGISTER_IN f1 0xFFF4000000000000
  #_ REGISTER_IN f2 0x41DFFFFFFFC00000
  fmul. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF4000000000000
  #_ REGISTER_OUT f2 0x41DFFFFFFFC00000
  #_ REGISTER_OUT f3 0xFFFC000000000000
  #_ REGISTER_OUT cr 0x0A000000

test_fmul_141_GEN:
  #_ REGISTER_IN f1 0xFFF4000000000000
  #_ REGISTER_IN f2 0x7FF0000000000000
  fmul f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF4000000000000
  #_ REGISTER_OUT f2 0x7FF0000000000000
  #_ REGISTER_OUT f3 0xFFFC000000000000

test_fmul_141_cr_GEN:
  #_ REGISTER_IN f1 0xFFF4000000000000
  #_ REGISTER_IN f2 0x7FF0000000000000
  fmul. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF4000000000000
  #_ REGISTER_OUT f2 0x7FF0000000000000
  #_ REGISTER_OUT f3 0xFFFC000000000000
  #_ REGISTER_OUT cr 0x0A000000

test_fmul_142_GEN:
  #_ REGISTER_IN f1 0xFFF4000000000000
  #_ REGISTER_IN f2 0xFFF0000000000000
  fmul f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF4000000000000
  #_ REGISTER_OUT f2 0xFFF0000000000000
  #_ REGISTER_OUT f3 0xFFFC000000000000

test_fmul_142_cr_GEN:
  #_ REGISTER_IN f1 0xFFF4000000000000
  #_ REGISTER_IN f2 0xFFF0000000000000
  fmul. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF4000000000000
  #_ REGISTER_OUT f2 0xFFF0000000000000
  #_ REGISTER_OUT f3 0xFFFC000000000000
  #_ REGISTER_OUT cr 0x0A000000

test_fmul_143_GEN:
  #_ REGISTER_IN f1 0xFFF4000000000000
  #_ REGISTER_IN f2 0xFFF8000000000000
  fmul f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF4000000000000
  #_ REGISTER_OUT f2 0xFFF8000000000000
  #_ REGISTER_OUT f3 0xFFFC000000000000

test_fmul_143_cr_GEN:
  #_ REGISTER_IN f1 0xFFF4000000000000
  #_ REGISTER_IN f2 0xFFF8000000000000
  fmul. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF4000000000000
  #_ REGISTER_OUT f2 0xFFF8000000000000
  #_ REGISTER_OUT f3 0xFFFC000000000000
  #_ REGISTER_OUT cr 0x0A000000

test_fmul_144_GEN:
  #_ REGISTER_IN f1 0xFFF4000000000000
  #_ REGISTER_IN f2 0xFFF4000000000000
  fmul f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF4000000000000
  #_ REGISTER_OUT f2 0xFFF4000000000000
  #_ REGISTER_OUT f3 0xFFFC000000000000

test_fmul_144_cr_GEN:
  #_ REGISTER_IN f1 0xFFF4000000000000
  #_ REGISTER_IN f2 0xFFF4000000000000
  fmul. f3, f1, f2
  blr
  #_ REGISTER_OUT f1 0xFFF4000000000000
  #_ REGISTER_OUT f2 0xFFF4000000000000
  #_ REGISTER_OUT f3 0xFFFC000000000000
  #_ REGISTER_OUT cr 0x0A000000

