//
// Generated by Microsoft (R) HLSL Shader Compiler 10.1
//
//
// Buffer Definitions: 
//
// cbuffer xe_system_cbuffer
// {
//
//   uint xe_flags;                     // Offset:    0 Size:     4 [unused]
//   uint xe_vertex_index_endian_and_edge_factors;// Offset:    4 Size:     4 [unused]
//   int xe_vertex_base_index;          // Offset:    8 Size:     4 [unused]
//   uint xe_pixel_pos_reg;             // Offset:   12 Size:     4 [unused]
//   float3 xe_ndc_scale;               // Offset:   16 Size:    12 [unused]
//   float xe_pixel_half_pixel_offset;  // Offset:   28 Size:     4 [unused]
//   float3 xe_ndc_offset;              // Offset:   32 Size:    12 [unused]
//   int xe_alpha_test;                 // Offset:   44 Size:     4 [unused]
//   float2 xe_point_size;              // Offset:   48 Size:     8 [unused]
//   float2 xe_point_size_min_max;      // Offset:   56 Size:     8 [unused]
//   float2 xe_point_screen_to_ndc;     // Offset:   64 Size:     8 [unused]
//   uint2 xe_sample_count_log2;        // Offset:   72 Size:     8 [unused]
//   float2 xe_alpha_test_range;        // Offset:   80 Size:     8 [unused]
//   uint xe_edram_pitch_tiles;         // Offset:   88 Size:     4 [unused]
//   uint xe_edram_depth_base_dwords;   // Offset:   92 Size:     4 [unused]
//   float4 xe_color_exp_bias;          // Offset:   96 Size:    16 [unused]
//   uint4 xe_color_output_map;         // Offset:  112 Size:    16 [unused]
//   float2 xe_tessellation_factor_range;// Offset:  128 Size:     8
//   float2 xe_edram_depth_range;       // Offset:  136 Size:     8 [unused]
//   float2 xe_edram_poly_offset_front; // Offset:  144 Size:     8 [unused]
//   float2 xe_edram_poly_offset_back;  // Offset:  152 Size:     8 [unused]
//   uint xe_edram_resolution_scale_log2;// Offset:  160 Size:     4 [unused]
//   uint xe_edram_stencil_reference;   // Offset:  164 Size:     4 [unused]
//   uint xe_edram_stencil_read_mask;   // Offset:  168 Size:     4 [unused]
//   uint xe_edram_stencil_write_mask;  // Offset:  172 Size:     4 [unused]
//   uint4 xe_edram_stencil_front;      // Offset:  176 Size:    16 [unused]
//   uint4 xe_edram_stencil_back;       // Offset:  192 Size:    16 [unused]
//   uint4 xe_edram_base_dwords;        // Offset:  208 Size:    16 [unused]
//   uint4 xe_edram_rt_flags;           // Offset:  224 Size:    16 [unused]
//   uint4 xe_edram_rt_pack_width_low;  // Offset:  240 Size:    16 [unused]
//   uint4 xe_edram_rt_pack_offset_low; // Offset:  256 Size:    16 [unused]
//   uint4 xe_edram_rt_pack_width_high; // Offset:  272 Size:    16 [unused]
//   uint4 xe_edram_rt_pack_offset_high;// Offset:  288 Size:    16 [unused]
//   uint4 xe_edram_load_mask_rt01;     // Offset:  304 Size:    16 [unused]
//   uint4 xe_edram_load_mask_rt23;     // Offset:  320 Size:    16 [unused]
//   float4 xe_edram_load_scale_rt01;   // Offset:  336 Size:    16 [unused]
//   float4 xe_edram_load_scale_rt23;   // Offset:  352 Size:    16 [unused]
//   uint4 xe_edram_blend_rt01;         // Offset:  368 Size:    16 [unused]
//   uint4 xe_edram_blend_rt23;         // Offset:  384 Size:    16 [unused]
//   float4 xe_edram_blend_constant;    // Offset:  400 Size:    16 [unused]
//   float4 xe_edram_store_min_rt01;    // Offset:  416 Size:    16 [unused]
//   float4 xe_edram_store_min_rt23;    // Offset:  432 Size:    16 [unused]
//   float4 xe_edram_store_max_rt01;    // Offset:  448 Size:    16 [unused]
//   float4 xe_edram_store_max_rt23;    // Offset:  464 Size:    16 [unused]
//   float4 xe_edram_store_scale_rt01;  // Offset:  480 Size:    16 [unused]
//   float4 xe_edram_store_scale_rt23;  // Offset:  496 Size:    16 [unused]
//
// }
//
//
// Resource Bindings:
//
// Name                                 Type  Format         Dim      ID      HLSL Bind  Count
// ------------------------------ ---------- ------- ----------- ------- -------------- ------
// xe_system_cbuffer                 cbuffer      NA          NA     CB0            cb0      1 
//
//
//
// Patch Constant signature:
//
// Name                 Index   Mask Register SysValue  Format   Used
// -------------------- ----- ------ -------- -------- ------- ------
// SV_TessFactor            0   x           0  TRIEDGE   float   x   
// SV_TessFactor            1   x           1  TRIEDGE   float   x   
// SV_TessFactor            2   x           2  TRIEDGE   float   x   
// SV_InsideTessFactor      0   x           3   TRIINT   float   x   
//
//
// Input signature:
//
// Name                 Index   Mask Register SysValue  Format   Used
// -------------------- ----- ------ -------- -------- ------- ------
// no Input
//
// Output signature:
//
// Name                 Index   Mask Register SysValue  Format   Used
// -------------------- ----- ------ -------- -------- ------- ------
// no Output
// Tessellation Domain   # of control points
// -------------------- --------------------
// Triangle                                3
//
// Tessellation Output Primitive  Partitioning Type 
// ------------------------------ ------------------
// Clockwise Triangles            Integer           
//
hs_5_1
hs_decls 
dcl_input_control_point_count 3
dcl_output_control_point_count 3
dcl_tessellator_domain domain_tri
dcl_tessellator_partitioning partitioning_integer
dcl_tessellator_output_primitive output_triangle_cw
dcl_globalFlags refactoringAllowed
dcl_constantbuffer CB0[0:0][9], immediateIndexed, space=0
hs_fork_phase 
dcl_hs_fork_phase_instance_count 3
dcl_input vForkInstanceID
dcl_output_siv o0.x, finalTriUeq0EdgeTessFactor
dcl_output_siv o1.x, finalTriVeq0EdgeTessFactor
dcl_output_siv o2.x, finalTriWeq0EdgeTessFactor
dcl_temps 1
dcl_indexrange o0.x 3
mov r0.x, vForkInstanceID.x
mov o[r0.x + 0].x, CB0[0][8].y
ret 
hs_fork_phase 
dcl_output_siv o3.x, finalTriInsideTessFactor
mov o3.x, CB0[0][8].y
ret 
// Approximately 5 instruction slots used
