//
// Generated by Microsoft (R) HLSL Shader Compiler 10.1
//
//
// Buffer Definitions: 
//
// cbuffer XeTextureTileConstants
// {
//
//   uint xe_texture_tile_guest_base;   // Offset:    0 Size:     4
//   uint xe_texture_tile_info;         // Offset:    4 Size:     4
//   uint xe_texture_tile_offset;       // Offset:    8 Size:     4
//   uint xe_texture_tile_size;         // Offset:   12 Size:     4
//   uint xe_texture_tile_host_base;    // Offset:   16 Size:     4
//   uint xe_texture_tile_host_pitch;   // Offset:   20 Size:     4
//
// }
//
//
// Resource Bindings:
//
// Name                                 Type  Format         Dim      ID      HLSL Bind  Count
// ------------------------------ ---------- ------- ----------- ------- -------------- ------
// xe_texture_tile_source            texture    byte         r/o      T0             t0      1 
// xe_texture_tile_dest                  UAV    byte         r/w      U0             u0      1 
// XeTextureTileConstants            cbuffer      NA          NA     CB0            cb0      1 
//
//
//
// Input signature:
//
// Name                 Index   Mask Register SysValue  Format   Used
// -------------------- ----- ------ -------- -------- ------- ------
// no Input
//
// Output signature:
//
// Name                 Index   Mask Register SysValue  Format   Used
// -------------------- ----- ------ -------- -------- ------- ------
// no Output
cs_5_1
dcl_globalFlags refactoringAllowed
dcl_constantbuffer CB0[0:0][2], immediateIndexed, space=0
dcl_resource_raw T0[0:0], space=0
dcl_uav_raw U0[0:0], space=0
dcl_input vThreadID.xy
dcl_temps 4
dcl_thread_group 32, 32, 1
ushr r0.y, CB0[0][0].w, l(16)
mov r0.x, CB0[0][0].w
and r0.xy, r0.xyxx, l(0x0000ffff, 0x0000ffff, 0, 0)
ubfe r0.z, l(1), l(9), CB0[0][0].y
ishl r0.xy, r0.xyxx, r0.zzzz
uge r0.xy, vThreadID.xyxx, r0.xyxx
or r0.x, r0.y, r0.x
if_nz r0.x
  ret 
endif 
ushr r1.xyzw, CB0[0][0].zzyy, l(5, 10, 10, 19)
mov r2.xz, CB0[0][0].zzzz
mov r2.yw, r1.xxxx
and r2.xyzw, r2.xyzw, l(31, 31, 31, 31)
ushr r3.xyzw, vThreadID.xyxy, r0.zzzz
iadd r2.xyzw, r2.xyzw, r3.xyzw
bfi r0.xy, l(9, 9, 0, 0), l(5, 5, 0, 0), r1.wzww, l(0, 0, 0, 0)
if_nz r0.x
  ushr r3.xyzw, r2.wzwz, l(4, 5, 3, 3)
  ubfe r0.w, l(1), l(12), CB0[0][0].z
  ushr r1.xz, r0.xxyx, l(4, 0, 5, 0)
  imad r0.x, r0.w, r1.x, r3.x
  imad r0.x, r0.x, r1.z, r3.y
  ishl r1.x, r2.w, l(12)
  and r1.x, r1.x, l(0x00006000)
  bfi r1.x, l(3), l(10), r2.z, r1.x
  ushr r1.x, r1.x, l(6)
  iadd r0.w, r0.w, r3.z
  bfi r1.z, l(1), l(1), r0.w, l(0)
  iadd r1.z, r1.z, r3.w
  bfi r1.z, l(2), l(1), r1.z, l(0)
  bfi r0.w, l(1), l(0), r0.w, r1.z
  bfi r1.zw, l(0, 0, 18, 18), l(0, 0, 12, 15), r0.xxxx, l(0, 0, 0, 0)
  imad r1.xz, r1.xxxx, l(2, 0, 16, 0), r1.zzwz
  bfi r1.xy, l(2, 2, 0, 0), l(10, 13, 0, 0), r1.yyyy, r1.xzxx
  bfi r0.x, l(1), l(4), r2.w, l(0)
  ubfe r1.z, l(3), l(6), r1.x
  and r1.w, r0.w, l(6)
  bfi r0.w, l(1), l(8), r0.w, l(0)
  imad r0.w, r1.z, l(32), r0.w
  imad r0.w, r1.w, l(4), r0.w
  bfi r1.xy, l(5, 5, 0, 0), l(0, 3, 0, 0), r0.xxxx, r1.xyxx
  bfi r0.x, l(9), l(3), r0.w, r1.y
  bfi r0.x, l(6), l(0), r1.x, r0.x
else 
  ushr r1.xyzw, r2.xyzw, l(5, 5, 3, 2)
  ushr r0.y, r0.y, l(5)
  imad r0.y, r1.y, r0.y, r1.x
  ishl r0.w, r2.w, l(7)
  and r1.xy, r0.wwww, l(1792, 2048, 0, 0)
  bfi r0.w, l(3), l(5), r2.z, r1.x
  bfi r0.w, l(21), l(11), r0.y, r0.w
  bfi r2.x, l(1), l(4), r2.w, l(0)
  iadd r0.w, r0.w, r2.x
  ishl r2.yw, r1.xxxx, l(0, 3, 0, 2)
  bfi r2.yz, l(0, 3, 3, 0), l(0, 8, 7, 0), r2.zzzz, r2.yywy
  bfi r2.yz, l(0, 21, 21, 0), l(0, 14, 13, 0), r0.yyyy, r2.yyzy
  imad r2.xy, r2.xxxx, l(8, 4, 0, 0), r2.yzyy
  bfi r0.y, l(12), l(0), r1.y, r2.x
  and r1.x, r2.y, l(1792)
  iadd r0.y, r0.y, r1.x
  and r1.x, r1.w, l(2)
  iadd r1.x, r1.x, r1.z
  bfi r1.x, l(2), l(6), r1.x, l(0)
  iadd r0.y, r0.y, r1.x
  bfi r0.x, l(6), l(0), r0.w, r0.y
endif 
iadd r0.x, r0.x, CB0[0][0].x
ishl r0.y, r0.z, l(1)
ishl r0.x, r0.x, r0.y
and r0.y, r0.z, vThreadID.y
ishl r0.y, r0.y, l(5)
iadd r0.x, r0.y, r0.x
if_nz r0.z
  bfi r0.y, l(1), l(4), vThreadID.x, l(0)
  xor r0.y, r0.y, l(0)
  iadd r0.x, r0.y, r0.x
endif 
imad r0.y, vThreadID.y, CB0[0][1].y, CB0[0][1].x
ishl r0.z, vThreadID.x, l(4)
iadd r0.y, r0.z, r0.y
ld_raw r1.xyzw, r0.y, T0[0].xyzw
and r0.yz, CB0[0][0].yyyy, l(0, 7, 4, 0)
if_nz r0.z
  and r0.z, CB0[0][0].y, l(1)
  movc r1.xyzw, r0.zzzz, r1.wzyx, r1.yxwz
  mov r0.y, l(2)
endif 
ushr r0.z, r0.y, l(1)
xor r0.z, r0.z, r0.y
and r0.yz, r0.yyzy, l(0, 2, 1, 0)
if_nz r0.z
  ishl r2.xyzw, r1.xyzw, l(8, 8, 8, 8)
  and r2.xyzw, r2.xyzw, l(0xff00ff00, 0xff00ff00, 0xff00ff00, 0xff00ff00)
  ushr r3.xyzw, r1.xyzw, l(8, 8, 8, 8)
  and r3.xyzw, r3.xyzw, l(0x00ff00ff, 0x00ff00ff, 0x00ff00ff, 0x00ff00ff)
  iadd r1.xyzw, r2.xyzw, r3.xyzw
endif 
if_nz r0.y
  ushr r2.xyzw, r1.xyzw, l(16, 16, 16, 16)
  bfi r1.xyzw, l(16, 16, 16, 16), l(16, 16, 16, 16), r1.xyzw, r2.xyzw
endif 
store_raw U0[0].xyzw, r0.x, r1.xyzw
ret 
// Approximately 104 instruction slots used
