//
// Generated by Microsoft (R) HLSL Shader Compiler 10.1
//
//
// Buffer Definitions: 
//
// cbuffer XeTextureLoadConstants
// {
//
//   uint xe_texture_load_guest_base;   // Offset:    0 Size:     4
//   uint xe_texture_load_guest_pitch;  // Offset:    4 Size:     4
//   uint xe_texture_load_host_base;    // Offset:    8 Size:     4
//   uint xe_texture_load_host_pitch;   // Offset:   12 Size:     4
//   uint3 xe_texture_load_size_texels; // Offset:   16 Size:    12 [unused]
//   bool xe_texture_load_is_3d;        // Offset:   28 Size:     4
//   uint3 xe_texture_load_size_blocks; // Offset:   32 Size:    12
//   uint xe_texture_load_endianness;   // Offset:   44 Size:     4
//   uint2 xe_texture_guest_storage_width_height;// Offset:   48 Size:     8
//   uint xe_texture_load_guest_format; // Offset:   56 Size:     4 [unused]
//   uint3 xe_texture_load_guest_mip_offset;// Offset:   64 Size:    12
//
// }
//
//
// Resource Bindings:
//
// Name                                 Type  Format         Dim      ID      HLSL Bind  Count
// ------------------------------ ---------- ------- ----------- ------- -------------- ------
// xe_texture_load_source            texture    byte         r/o      T0             t0      1 
// xe_texture_load_dest                  UAV    byte         r/w      U0             u0      1 
// XeTextureLoadConstants            cbuffer      NA          NA     CB0            cb0      1 
//
//
//
// Input signature:
//
// Name                 Index   Mask Register SysValue  Format   Used
// -------------------- ----- ------ -------- -------- ------- ------
// no Input
//
// Output signature:
//
// Name                 Index   Mask Register SysValue  Format   Used
// -------------------- ----- ------ -------- -------- ------- ------
// no Output
cs_5_1
dcl_globalFlags refactoringAllowed
dcl_constantbuffer CB0[0:0][5], immediateIndexed, space=0
dcl_resource_raw T0[0:0], space=0
dcl_uav_raw U0[0:0], space=0
dcl_input vThreadID.xyz
dcl_temps 6
dcl_thread_group 16, 16, 1
ishl r0.x, vThreadID.x, l(2)
mov r0.yz, vThreadID.yyzy
uge r0.xyz, r0.xyzx, CB0[0][2].xyzx
or r0.x, r0.y, r0.x
or r0.x, r0.z, r0.x
if_nz r0.x
  ret 
endif 
iadd r0.xyzw, vThreadID.yzxy, CB0[0][4].yzxy
ieq r1.x, CB0[0][0].y, l(-1)
if_nz r1.x
  if_nz CB0[0][1].w
    iadd r1.xy, CB0[0][3].yxyy, l(31, 31, 0, 0)
    ushr r2.xyzw, r0.xyzw, l(4, 2, 5, 3)
    ushr r1.xy, r1.xyxx, l(4, 5, 0, 0)
    and r0.x, r1.x, l(0x0ffffffe)
    imad r0.x, r2.y, r0.x, r2.x
    imad r0.x, r0.x, r1.y, r2.z
    ishl r1.x, r0.w, l(10)
    and r1.x, r1.x, l(6144)
    bfi r1.x, l(3), l(8), r0.z, r1.x
    ushr r1.x, r1.x, l(6)
    iadd r1.y, r2.y, r2.w
    ushr r1.z, r0.z, l(3)
    bfi r1.w, l(1), l(1), r1.y, l(0)
    iadd r1.z, r1.w, r1.z
    bfi r1.z, l(2), l(1), r1.z, l(0)
    bfi r1.y, l(1), l(0), r1.y, r1.z
    and r1.z, r1.x, l(112)
    bfi r2.xy, l(20, 20, 0, 0), l(10, 13, 0, 0), r0.xxxx, l(0, 0, 0, 0)
    imad r1.zw, r1.zzzz, l(0, 0, 2, 16), r2.xxxy
    bfi r1.xz, l(4, 0, 4, 0), l(0, 0, 3, 0), r1.xxxx, r1.zzwz
    bfi r1.xz, l(2, 0, 2, 0), l(8, 0, 11, 0), r0.yyyy, r1.xxzx
    ubfe r0.x, l(3), l(6), r1.x
    and r1.w, r1.y, l(6)
    bfi r1.y, l(1), l(8), r1.y, l(0)
    imad r0.x, r0.x, l(32), r1.y
    imad r0.x, r1.w, l(4), r0.x
    bfi r1.xy, l(1, 1, 0, 0), l(4, 7, 0, 0), r0.wwww, r1.xzxx
    bfi r0.x, l(9), l(3), r0.x, r1.y
    bfi r0.x, l(6), l(0), r1.x, r0.x
  else 
    ushr r1.xyzw, r0.zwzw, l(5, 5, 3, 2)
    iadd r2.x, CB0[0][3].x, l(31)
    ushr r2.x, r2.x, l(5)
    imad r1.x, r1.y, r2.x, r1.x
    ishl r2.xy, r0.wwww, l(4, 7, 0, 0)
    and r2.xy, r2.xyxx, l(224, 2048, 0, 0)
    bfi r1.y, l(3), l(2), r0.z, r2.x
    ishl r2.x, r2.x, l(1)
    bfi r2.x, l(3), l(3), r0.z, r2.x
    and r2.x, r2.x, l(480)
    bfi r2.z, l(23), l(9), r1.x, r2.x
    bfi r2.z, l(4), l(0), r1.y, r2.z
    bfi r2.z, l(1), l(4), r0.w, r2.z
    ishl r2.xw, r2.xxxx, l(3, 0, 0, 2)
    bfi r2.xw, l(23, 0, 0, 23), l(12, 0, 0, 11), r1.xxxx, r2.xxxw
    bfi r1.xy, l(4, 4, 0, 0), l(3, 2, 0, 0), r1.yyyy, r2.xwxx
    bfi r1.xy, l(1, 1, 0, 0), l(7, 6, 0, 0), r0.wwww, r1.xyxx
    bfi r1.x, l(12), l(0), r2.y, r1.x
    and r1.y, r1.y, l(1792)
    iadd r1.x, r1.x, r1.y
    and r1.y, r1.w, l(2)
    iadd r1.y, r1.y, r1.z
    bfi r1.y, l(2), l(6), r1.y, l(0)
    iadd r1.x, r1.x, r1.y
    bfi r0.x, l(6), l(0), r2.z, r1.x
  endif 
else 
  ishl r0.z, r0.z, l(2)
  iadd r1.x, CB0[0][2].y, l(31)
  and r1.x, r1.x, l(-32)
  imad r0.y, r0.y, r1.x, r0.w
  imad r0.x, r0.y, CB0[0][0].y, r0.z
endif 
iadd r0.x, r0.x, CB0[0][0].x
ishl r0.x, r0.x, l(2)
ld_raw r0.xyzw, r0.x, T0[0].xyzw
ushr r1.x, CB0[0][2].w, l(1)
xor r1.x, r1.x, CB0[0][2].w
and r1.x, r1.x, l(1)
if_nz r1.x
  ishl r1.xyzw, r0.xyzw, l(8, 8, 8, 8)
  and r1.xyzw, r1.xyzw, l(0xff00ff00, 0xff00ff00, 0xff00ff00, 0xff00ff00)
  ushr r2.xyzw, r0.xyzw, l(8, 8, 8, 8)
  and r2.xyzw, r2.xyzw, l(0x00ff00ff, 0x00ff00ff, 0x00ff00ff, 0x00ff00ff)
  iadd r0.xyzw, r1.xyzw, r2.xyzw
endif 
and r1.x, CB0[0][2].w, l(2)
if_nz r1.x
  ushr r1.xyzw, r0.xyzw, l(16, 16, 16, 16)
  bfi r0.xyzw, l(16, 16, 16, 16), l(16, 16, 16, 16), r0.xyzw, r1.xyzw
endif 
ishl r1.xy, vThreadID.xyxx, l(1, 1, 0, 0)
ishl r1.z, CB0[0][2].y, l(1)
ishl r1.x, r1.x, l(3)
imad r1.y, vThreadID.z, r1.z, r1.y
imad r1.x, r1.y, CB0[0][0].w, r1.x
iadd r1.x, r1.x, CB0[0][0].z
and r2.xyzw, r0.xyzw, l(2047, 2047, 2047, 2047)
ubfe r3.xyzw, l(1, 1, 1, 1), l(10, 10, 10, 10), r0.xyzw
ieq r4.xyzw, r2.xyzw, l(1024, 1024, 1024, 1024)
movc r2.xyzw, r4.xyzw, l(1025,1025,1025,1025), r2.xyzw
movc r4.xyzw, r3.xyzw, l(2047,2047,2047,2047), l(0,0,0,0)
xor r2.xyzw, r2.xyzw, r4.xyzw
iadd r2.xyzw, r3.xyzw, r2.xyzw
ishl r4.xyzw, r2.xyzw, l(5, 5, 5, 5)
ushr r2.xyzw, r2.xyzw, l(5, 5, 5, 5)
or r2.xyzw, r2.xyzw, r4.xyzw
movc r4.xyzw, r3.xyzw, l(0x0000ffff,0x0000ffff,0x0000ffff,0x0000ffff), l(0,0,0,0)
xor r2.xyzw, r2.xyzw, r4.xyzw
iadd r2.xyzw, r3.xyzw, r2.xyzw
ubfe r3.xyzw, l(11, 11, 11, 11), l(11, 11, 11, 11), r0.xyzw
ubfe r4.xyzw, l(1, 1, 1, 1), l(21, 21, 21, 21), r0.xyzw
ieq r5.xyzw, r3.xyzw, l(1024, 1024, 1024, 1024)
movc r3.xyzw, r5.xyzw, l(1025,1025,1025,1025), r3.xyzw
movc r5.xyzw, r4.xyzw, l(2047,2047,2047,2047), l(0,0,0,0)
xor r3.xyzw, r3.xyzw, r5.xyzw
iadd r3.xyzw, r4.xyzw, r3.xyzw
ishl r5.xyzw, r3.xyzw, l(5, 5, 5, 5)
ushr r3.xyzw, r3.xyzw, l(5, 5, 5, 5)
or r3.xyzw, r3.xyzw, r5.xyzw
movc r5.xyzw, r4.xyzw, l(0x0000ffff,0x0000ffff,0x0000ffff,0x0000ffff), l(0,0,0,0)
xor r3.xyzw, r3.xyzw, r5.xyzw
iadd r3.xyzw, r4.xyzw, r3.xyzw
or r2.xyzw, r2.xyzw, r3.xyzw
ushr r0.xyzw, r0.xyzw, l(22, 22, 22, 22)
ushr r3.xyzw, r0.xyzw, l(9, 9, 9, 9)
ieq r4.xyzw, r0.xyzw, l(512, 512, 512, 512)
movc r0.xyzw, r4.xyzw, l(513,513,513,513), r0.xyzw
movc r4.xyzw, r3.xyzw, l(1023,1023,1023,1023), l(0,0,0,0)
xor r0.xyzw, r0.xyzw, r4.xyzw
iadd r0.xyzw, r3.xyzw, r0.xyzw
ishl r4.xyzw, r0.xyzw, l(6, 6, 6, 6)
ushr r0.xyzw, r0.xyzw, l(3, 3, 3, 3)
or r0.xyzw, r0.xyzw, r4.xyzw
movc r4.xyzw, r3.xyzw, l(0x0000ffff,0x0000ffff,0x0000ffff,0x0000ffff), l(0,0,0,0)
xor r0.xyzw, r0.xyzw, r4.xyzw
iadd r0.xyzw, r3.xyzw, r0.xyzw
or r0.xyzw, r0.xzyw, l(0x7fff0000, 0x7fff0000, 0x7fff0000, 0x7fff0000)
mov r3.xz, r2.xxyx
mov r3.yw, r0.xxxz
store_raw U0[0].xyzw, r1.x, r3.xyzw
iadd r1.x, r1.x, CB0[0][0].w
mov r0.xz, r2.zzwz
store_raw U0[0].xyzw, r1.x, r0.xyzw
ret 
// Approximately 147 instruction slots used
