//
// Generated by Microsoft (R) HLSL Shader Compiler 10.1
//
//
// Buffer Definitions: 
//
// cbuffer XeEDRAMLoadStoreConstants
// {
//
//   uint4 xe_edram_load_store_constants;// Offset:    0 Size:    16
//   uint xe_edram_base_depth_pitch;    // Offset:   16 Size:     4
//
// }
//
//
// Resource Bindings:
//
// Name                                 Type  Format         Dim      ID      HLSL Bind  Count
// ------------------------------ ---------- ------- ----------- ------- -------------- ------
// xe_edram_load_store_source        texture    byte         r/o      T0             t0      1 
// xe_edram_load_store_dest              UAV    byte         r/w      U0             u0      1 
// XeEDRAMLoadStoreConstants         cbuffer      NA          NA     CB0            cb0      1 
//
//
//
// Input signature:
//
// Name                 Index   Mask Register SysValue  Format   Used
// -------------------- ----- ------ -------- -------- ------- ------
// no Input
//
// Output signature:
//
// Name                 Index   Mask Register SysValue  Format   Used
// -------------------- ----- ------ -------- -------- ------- ------
// no Output
cs_5_1
dcl_globalFlags refactoringAllowed
dcl_constantbuffer CB0[0:0][2], immediateIndexed, space=0
dcl_resource_raw T0[0:0], space=0
dcl_uav_raw U0[0:0], space=0
dcl_input vThreadGroupID.xy
dcl_input vThreadIDInGroup.xy
dcl_input vThreadID.xy
dcl_temps 2
dcl_thread_group 20, 16, 1
ishl r0.xy, vThreadID.xxxx, l(4, 2, 0, 0)
imad r0.xy, vThreadID.yyyy, CB0[0][0].ywyy, r0.xyxx
iadd r0.xy, r0.xyxx, CB0[0][0].xzxx
ld_raw r1.xyzw, r0.x, T0[0].xyzw
ld_raw r0.x, r0.y, T0[0].xxxx
ushr r0.yzw, r0.xxxx, l(0, 8, 16, 24)
bfi r0.xyzw, l(24, 24, 24, 24), l(8, 8, 8, 8), r1.xyzw, r0.xyzw
ishl r1.x, vThreadIDInGroup.x, l(2)
and r1.yz, CB0[0][1].xxxx, l(0, 2048, 2047, 0)
if_nz r1.y
  ult r1.y, vThreadIDInGroup.x, l(10)
  uge r1.w, vThreadIDInGroup.x, l(10)
  and r1.yw, r1.yyyw, l(0, 40, 0, -40)
  iadd r1.y, r1.w, r1.y
  iadd r1.x, r1.y, r1.x
endif 
ushr r1.y, CB0[0][1].x, l(12)
imad r1.y, vThreadGroupID.y, r1.y, r1.z
iadd r1.y, r1.y, vThreadGroupID.x
imul null, r1.z, vThreadIDInGroup.y, l(320)
imad r1.y, r1.y, l(5120), r1.z
ishl r1.x, r1.x, l(2)
iadd r1.x, r1.x, r1.y
store_raw U0[0].xyzw, r1.x, r0.xyzw
ret 
// Approximately 25 instruction slots used
