//
// Generated by Microsoft (R) HLSL Shader Compiler 10.1
//
//
// Buffer Definitions: 
//
// cbuffer XeEDRAMLoadStoreConstants
// {
//
//   uint4 xe_edram_load_store_constants;// Offset:    0 Size:    16
//   uint xe_edram_base_depth_pitch;    // Offset:   16 Size:     4
//
// }
//
//
// Resource Bindings:
//
// Name                                 Type  Format         Dim      ID      HLSL Bind  Count
// ------------------------------ ---------- ------- ----------- ------- -------------- ------
// xe_edram_load_store_source        texture    byte         r/o      T0             t0      1 
// xe_edram_load_store_dest              UAV    byte         r/w      U0             u0      1 
// XeEDRAMLoadStoreConstants         cbuffer      NA          NA     CB0            cb0      1 
//
//
//
// Input signature:
//
// Name                 Index   Mask Register SysValue  Format   Used
// -------------------- ----- ------ -------- -------- ------- ------
// no Input
//
// Output signature:
//
// Name                 Index   Mask Register SysValue  Format   Used
// -------------------- ----- ------ -------- -------- ------- ------
// no Output
cs_5_1
dcl_globalFlags refactoringAllowed
dcl_constantbuffer CB0[0:0][2], immediateIndexed, space=0
dcl_resource_raw T0[0:0], space=0
dcl_uav_raw U0[0:0], space=0
dcl_input vThreadGroupID.xy
dcl_input vThreadIDInGroup.xy
dcl_input vThreadID.xy
dcl_temps 9
dcl_thread_group 20, 16, 1
ushr r0.xy, CB0[0][0].xyxx, l(17, 17, 0, 0)
ishl r0.zw, vThreadID.xxxy, l(0, 0, 2, 0)
ult r0.zw, r0.zzzw, r0.xxxy
or r0.z, r0.w, r0.z
if_nz r0.z
  ret 
endif 
iadd r0.yz, -r0.xxyx, vThreadID.xxyx
ishl r0.x, r0.y, l(2)
and r1.xy, CB0[0][0].xyxx, l(4095, 4095, 0, 0)
uge r1.yz, r0.xxzx, r1.xxyx
or r0.w, r1.z, r1.y
if_nz r0.w
  ret 
endif 
ubfe r2.xyzw, l(1, 1, 1, 1), l(15, 14, 17, 16), CB0[0][0].wwww
uge r1.yz, vThreadIDInGroup.xxyx, l(0, 10, 8, 0)
and r1.yz, r1.yyzy, l(0, 1, 1, 0)
imul null, r3.xy, r2.xyxx, r1.yzyy
ishl r3.zw, vThreadGroupID.xxxy, r2.xxxy
imad r1.yz, r1.yyzy, r2.xxyx, r3.zzwz
imad r3.xy, -r3.xyxx, l(10, 8, 0, 0), vThreadIDInGroup.xyxx
iadd r3.zw, r2.xxxy, l(0, 0, 2, 0)
ishl r3.xy, r3.xyxx, r3.zwzz
iadd r2.yz, r2.zzwz, r3.xxyx
and r3.xy, CB0[0][1].xxxx, l(2048, 2047, 0, 0)
if_nz r3.x
  ult r0.w, r2.y, l(40)
  and r0.w, r0.w, l(40)
  uge r1.w, r2.y, l(40)
  and r1.w, r1.w, l(-40)
  iadd r0.w, r0.w, r1.w
  iadd r2.y, r0.w, r2.y
endif 
ushr r0.w, CB0[0][1].x, l(12)
imad r0.w, r1.z, r0.w, r3.y
iadd r0.w, r1.y, r0.w
imul null, r1.y, r2.z, l(320)
imad r0.w, r0.w, l(5120), r1.y
ishl r1.y, r2.y, l(2)
iadd r0.w, r0.w, r1.y
ld_raw r3.xyzw, r0.w, T0[0].xyzw
if_nz r2.x
  iadd r0.w, r0.w, l(16)
  ld_raw r2.y, r0.w, T0[0].xxxx
  iadd r0.w, r0.w, l(8)
  ld_raw r2.z, r0.w, T0[0].xxxx
  mov r2.x, r3.z
  mov r3.yzw, r2.xxyz
endif 
ushr r1.yz, CB0[0][0].wwww, l(0, 21, 18, 0)
if_nz r1.y
  ishl r0.w, l(1), r1.y
  iadd r0.w, r0.w, l(-1)
  ushr r1.w, r1.y, l(5)
  ishl r0.w, r0.w, r1.w
  bfi r0.w, r1.y, l(0), l(-1), r0.w
  not r0.w, r0.w
  and r2.xyzw, r0.wwww, r3.xyzw
  bfi r4.xyzw, r1.yyyy, r1.wwww, r3.xyzw, l(0, 0, 0, 0)
  or r2.xyzw, r2.xyzw, r4.xyzw
  ubfe r4.xyzw, r1.yyyy, r1.wwww, r3.xyzw
  or r3.xyzw, r2.xyzw, r4.xyzw
endif 
ushr r0.w, r1.z, l(1)
xor r0.w, r0.w, r1.z
and r0.w, r0.w, l(1)
if_nz r0.w
  ishl r2.xyzw, r3.xyzw, l(8, 8, 8, 8)
  and r2.xyzw, r2.xyzw, l(0xff00ff00, 0xff00ff00, 0xff00ff00, 0xff00ff00)
  ushr r4.xyzw, r3.xyzw, l(8, 8, 8, 8)
  and r4.xyzw, r4.xyzw, l(0x00ff00ff, 0x00ff00ff, 0x00ff00ff, 0x00ff00ff)
  iadd r3.xyzw, r2.xyzw, r4.xyzw
endif 
and r0.w, r1.z, l(2)
if_nz r0.w
  ushr r2.xyzw, r3.xyzw, l(16, 16, 16, 16)
  bfi r3.xyzw, l(16, 16, 16, 16), l(16, 16, 16, 16), r3.xyzw, r2.xyzw
endif 
ubfe r1.yz, l(0, 5, 5, 0), l(0, 12, 12, 0), CB0[0][0].xxyx
iadd r0.xz, r0.xxzx, r1.yyzy
and r0.w, CB0[0][0].w, l(0x00003fff)
iadd r2.xyzw, r0.xxxx, l(0, 1, 2, 3)
ushr r4.xyzw, r2.xyzw, l(5, 5, 5, 5)
ushr r1.yz, r0.zzzz, l(0, 5, 2, 0)
iadd r0.x, r0.w, l(31)
ushr r0.x, r0.x, l(5)
imad r4.xyzw, r1.yyyy, r0.xxxx, r4.xyzw
ishl r0.xw, r0.zzzz, l(4, 0, 0, 7)
and r0.xw, r0.xxxw, l(224, 0, 0, 2048)
bfi r5.xyzw, l(3, 3, 3, 3), l(2, 2, 2, 2), r2.xyzw, r0.xxxx
ishl r0.x, r0.x, l(1)
bfi r6.xyzw, l(3, 3, 3, 3), l(3, 3, 3, 3), r2.xyzw, r0.xxxx
and r6.xyzw, r6.xyzw, l(480, 480, 480, 480)
bfi r7.xyzw, l(23, 23, 23, 23), l(9, 9, 9, 9), r4.xyzw, r6.xyzw
bfi r7.xyzw, l(4, 4, 4, 4), l(0, 0, 0, 0), r5.xyzw, r7.xyzw
bfi r7.xyzw, l(1, 1, 1, 1), l(4, 4, 4, 4), r0.zzzz, r7.xyzw
ishl r8.xyzw, r6.xyzw, l(3, 3, 3, 3)
bfi r8.xyzw, l(23, 23, 23, 23), l(12, 12, 12, 12), r4.xyzw, r8.xyzw
bfi r8.xyzw, l(4, 4, 4, 4), l(3, 3, 3, 3), r5.xyzw, r8.xyzw
bfi r8.xyzw, l(1, 1, 1, 1), l(7, 7, 7, 7), r0.zzzz, r8.xyzw
bfi r8.xyzw, l(12, 12, 12, 12), l(0, 0, 0, 0), r0.wwww, r8.xyzw
ishl r6.xyzw, r6.xyzw, l(2, 2, 2, 2)
bfi r4.xyzw, l(23, 23, 23, 23), l(11, 11, 11, 11), r4.xyzw, r6.xyzw
bfi r4.xyzw, l(4, 4, 4, 4), l(2, 2, 2, 2), r5.xyzw, r4.xyzw
bfi r4.xyzw, l(1, 1, 1, 1), l(6, 6, 6, 6), r0.zzzz, r4.xyzw
and r4.xyzw, r4.xyzw, l(1792, 1792, 1792, 1792)
iadd r4.xyzw, r8.xyzw, r4.xyzw
ushr r2.xyzw, r2.xyzw, l(3, 3, 3, 3)
and r0.x, r1.z, l(2)
iadd r2.xyzw, r0.xxxx, r2.xyzw
bfi r2.xyzw, l(2, 2, 2, 2), l(6, 6, 6, 6), r2.xyzw, l(0, 0, 0, 0)
iadd r2.xyzw, r4.xyzw, r2.xyzw
bfi r2.xyzw, l(6, 6, 6, 6), l(0, 0, 0, 0), r7.xyzw, r2.xyzw
iadd r2.xyzw, r2.xyzw, CB0[0][0].zzzz
store_raw U0[0].x, r2.x, r3.x
bfi r0.xyz, l(30, 30, 30, 0), l(2, 2, 2, 0), r0.yyyy, l(1, 2, 3, 0)
ult r0.xyz, r0.xyzx, r1.xxxx
if_nz r0.x
  store_raw U0[0].x, r2.y, r3.y
  if_nz r0.y
    store_raw U0[0].x, r2.z, r3.z
    if_nz r0.z
      store_raw U0[0].x, r2.w, r3.w
    endif 
  endif 
endif 
ret 
// Approximately 128 instruction slots used
