//
// Generated by Microsoft (R) HLSL Shader Compiler 10.1
//
//
// Buffer Definitions: 
//
// cbuffer XeTextureTileConstants
// {
//
//   uint xe_texture_tile_guest_base;   // Offset:    0 Size:     4
//   uint xe_texture_tile_endian_format_guest_pitch;// Offset:    4 Size:     4
//   uint xe_texture_tile_offset;       // Offset:    8 Size:     4
//   uint xe_texture_tile_size;         // Offset:   12 Size:     4
//   uint xe_texture_tile_host_base;    // Offset:   16 Size:     4
//   uint xe_texture_tile_host_pitch;   // Offset:   20 Size:     4
//
// }
//
//
// Resource Bindings:
//
// Name                                 Type  Format         Dim      ID      HLSL Bind  Count
// ------------------------------ ---------- ------- ----------- ------- -------------- ------
// xe_texture_tile_source            texture    byte         r/o      T0             t0      1 
// xe_texture_tile_dest                  UAV    byte         r/w      U0             u0      1 
// XeTextureTileConstants            cbuffer      NA          NA     CB0            cb0      1 
//
//
//
// Input signature:
//
// Name                 Index   Mask Register SysValue  Format   Used
// -------------------- ----- ------ -------- -------- ------- ------
// no Input
//
// Output signature:
//
// Name                 Index   Mask Register SysValue  Format   Used
// -------------------- ----- ------ -------- -------- ------- ------
// no Output
cs_5_1
dcl_globalFlags refactoringAllowed
dcl_constantbuffer CB0[0:0][2], immediateIndexed, space=0
dcl_resource_raw T0[0:0], space=0
dcl_uav_raw U0[0:0], space=0
dcl_input vThreadID.xy
dcl_temps 4
dcl_thread_group 32, 32, 1
ushr r0.y, CB0[0][0].w, l(16)
mov r0.x, CB0[0][0].w
and r0.xy, r0.xyxx, l(0x0000ffff, 0x0000ffff, 0, 0)
uge r0.xy, vThreadID.xyxx, r0.xyxx
or r0.x, r0.y, r0.x
if_nz r0.x
  ret 
endif 
ushr r0.xy, CB0[0][0].zyzz, l(16, 9, 0, 0)
mov r0.z, CB0[0][0].z
and r1.xyzw, r0.zxzx, l(0x0000ffff, 0x0000ffff, 0x0000ffff, 0x0000ffff)
iadd r1.xyzw, r1.xyzw, vThreadID.xyxy
ushr r2.xyzw, r1.xyzw, l(5, 5, 3, 2)
iadd r0.x, r0.y, l(31)
ushr r0.x, r0.x, l(5)
imad r0.x, r2.y, r0.x, r2.x
ishl r0.y, r1.w, l(7)
and r0.yz, r0.yyyy, l(0, 1792, 2048, 0)
bfi r0.w, l(3), l(5), r1.z, r0.y
bfi r0.w, l(21), l(11), r0.x, r0.w
bfi r1.x, l(1), l(4), r1.w, l(0)
iadd r0.w, r0.w, r1.x
ishl r1.yw, r0.yyyy, l(0, 3, 0, 2)
bfi r1.yz, l(0, 3, 3, 0), l(0, 8, 7, 0), r1.zzzz, r1.yywy
bfi r0.xy, l(21, 21, 0, 0), l(14, 13, 0, 0), r0.xxxx, r1.yzyy
imad r0.xy, r1.xxxx, l(8, 4, 0, 0), r0.xyxx
bfi r0.x, l(12), l(0), r0.z, r0.x
and r0.y, r0.y, l(1792)
iadd r0.x, r0.x, r0.y
and r0.y, r2.w, l(2)
iadd r0.y, r0.y, r2.z
bfi r0.y, l(2), l(6), r0.y, l(0)
iadd r0.x, r0.x, r0.y
bfi r0.x, l(6), l(0), r0.w, r0.x
iadd r0.x, r0.x, CB0[0][0].x
imad r0.y, vThreadID.y, CB0[0][1].y, CB0[0][1].x
ishl r0.z, vThreadID.x, l(4)
iadd r0.y, r0.z, r0.y
ld_raw r1.xyzw, r0.y, T0[0].xyzw
and r0.y, CB0[0][0].y, l(4)
if_nz r0.y
  and r0.y, CB0[0][0].y, l(1)
  movc r1.xyzw, r0.yyyy, r1.wzyx, r1.yxwz
  mov r0.y, l(2)
else 
  mov r0.y, CB0[0][0].y
endif 
ushr r0.z, r0.y, l(1)
xor r0.z, r0.z, r0.y
and r0.yz, r0.yyzy, l(0, 2, 1, 0)
if_nz r0.z
  ishl r2.xyzw, r1.xyzw, l(8, 8, 8, 8)
  and r2.xyzw, r2.xyzw, l(0xff00ff00, 0xff00ff00, 0xff00ff00, 0xff00ff00)
  ushr r3.xyzw, r1.xyzw, l(8, 8, 8, 8)
  and r3.xyzw, r3.xyzw, l(0x00ff00ff, 0x00ff00ff, 0x00ff00ff, 0x00ff00ff)
  iadd r1.xyzw, r2.xyzw, r3.xyzw
endif 
if_nz r0.y
  ushr r2.xyzw, r1.xyzw, l(16, 16, 16, 16)
  bfi r1.xyzw, l(16, 16, 16, 16), l(16, 16, 16, 16), r1.xyzw, r2.xyzw
endif 
store_raw U0[0].xyzw, r0.x, r1.xyzw
ret 
// Approximately 63 instruction slots used
