//
// Generated by Microsoft (R) HLSL Shader Compiler 10.1
//
//
// Buffer Definitions: 
//
// cbuffer XeTextureLoadConstants
// {
//
//   uint xe_texture_load_guest_base;   // Offset:    0 Size:     4
//   uint xe_texture_load_guest_pitch;  // Offset:    4 Size:     4
//   uint xe_texture_load_host_base;    // Offset:    8 Size:     4
//   uint xe_texture_load_host_pitch;   // Offset:   12 Size:     4
//   uint3 xe_texture_load_size_texels; // Offset:   16 Size:    12 [unused]
//   bool xe_texture_load_is_3d;        // Offset:   28 Size:     4
//   uint3 xe_texture_load_size_blocks; // Offset:   32 Size:    12
//   uint xe_texture_load_endianness;   // Offset:   44 Size:     4
//   uint2 xe_texture_guest_storage_width_height;// Offset:   48 Size:     8
//   uint xe_texture_load_guest_format; // Offset:   56 Size:     4 [unused]
//   uint3 xe_texture_load_guest_mip_offset;// Offset:   64 Size:    12
//
// }
//
//
// Resource Bindings:
//
// Name                                 Type  Format         Dim      ID      HLSL Bind  Count
// ------------------------------ ---------- ------- ----------- ------- -------------- ------
// xe_texture_load_source            texture    byte         r/o      T0             t0      1 
// xe_texture_load_dest                  UAV    byte         r/w      U0             u0      1 
// XeTextureLoadConstants            cbuffer      NA          NA     CB0            cb0      1 
//
//
//
// Input signature:
//
// Name                 Index   Mask Register SysValue  Format   Used
// -------------------- ----- ------ -------- -------- ------- ------
// no Input
//
// Output signature:
//
// Name                 Index   Mask Register SysValue  Format   Used
// -------------------- ----- ------ -------- -------- ------- ------
// no Output
cs_5_1
dcl_globalFlags refactoringAllowed
dcl_constantbuffer CB0[0:0][5], immediateIndexed, space=0
dcl_resource_raw T0[0:0], space=0
dcl_uav_raw U0[0:0], space=0
dcl_input vThreadID.xyz
dcl_temps 8
dcl_thread_group 8, 32, 1
ishl r0.x, vThreadID.x, l(2)
mov r0.yz, vThreadID.yyzy
uge r1.xyz, r0.xyzx, CB0[0][2].xyzx
or r0.w, r1.y, r1.x
or r0.w, r1.z, r0.w
if_nz r0.w
  ret 
endif 
iadd r0.yzw, r0.xxyz, CB0[0][4].xxyz
ieq r1.x, CB0[0][0].y, l(-1)
if_nz r1.x
  if_nz CB0[0][1].w
    iadd r1.xyzw, r0.yyyy, l(0, 1, 2, 3)
    ushr r2.xyz, r0.wzzw, l(2, 4, 3, 0)
    ushr r3.xy, CB0[0][3].yxyy, l(4, 5, 0, 0)
    imad r2.y, r2.x, r3.x, r2.y
    iadd r2.x, r2.z, r2.x
    bfi r2.z, l(1), l(1), r2.x, l(0)
    ushr r4.xyzw, r1.xyzw, l(3, 3, 3, 3)
    iadd r4.xyzw, r2.zzzz, r4.xyzw
    bfi r4.xyzw, l(2, 2, 2, 2), l(1, 1, 1, 1), r4.xyzw, l(0, 0, 0, 0)
    bfi r4.xyzw, l(1, 1, 1, 1), l(0, 0, 0, 0), r2.xxxx, r4.xyzw
    ishl r2.x, r0.z, l(12)
    and r2.x, r2.x, l(0x00006000)
    bfi r5.xyzw, l(3, 3, 3, 3), l(10, 10, 10, 10), r1.xyzw, r2.xxxx
    ushr r5.xyzw, r5.xyzw, l(6, 6, 6, 6)
    ushr r1.xyzw, r1.xyzw, l(5, 5, 5, 5)
    imad r1.xyzw, r2.yyyy, r3.yyyy, r1.xyzw
    bfi r2.xyzw, l(18, 18, 18, 18), l(12, 12, 12, 12), r1.xyzw, l(0, 0, 0, 0)
    imad r2.xyzw, r5.xyzw, l(2, 2, 2, 2), r2.xyzw
    bfi r2.xyzw, l(2, 2, 2, 2), l(10, 10, 10, 10), r0.wwww, r2.xyzw
    bfi r3.x, l(1), l(4), r0.z, l(0)
    iadd r6.xyzw, r2.xyzw, r3.xxxx
    ubfe r2.xyzw, l(3, 3, 3, 3), l(6, 6, 6, 6), r2.xyzw
    and r7.xyzw, r4.xyzw, l(6, 6, 6, 6)
    bfi r4.xyzw, l(1, 1, 1, 1), l(8, 8, 8, 8), r4.xyzw, l(0, 0, 0, 0)
    imad r2.xyzw, r2.xyzw, l(32, 32, 32, 32), r4.xyzw
    imad r2.xyzw, r7.xyzw, l(4, 4, 4, 4), r2.xyzw
    bfi r1.xyzw, l(18, 18, 18, 18), l(15, 15, 15, 15), r1.xyzw, l(0, 0, 0, 0)
    imad r1.xyzw, r5.xyzw, l(16, 16, 16, 16), r1.xyzw
    bfi r1.xyzw, l(2, 2, 2, 2), l(13, 13, 13, 13), r0.wwww, r1.xyzw
    imad r1.xyzw, r3.xxxx, l(8, 8, 8, 8), r1.xyzw
    bfi r1.xyzw, l(9, 9, 9, 9), l(3, 3, 3, 3), r2.xyzw, r1.xyzw
    bfi r1.xyzw, l(6, 6, 6, 6), l(0, 0, 0, 0), r6.xyzw, r1.xyzw
  else 
    iadd r2.xyzw, r0.yyyy, l(0, 1, 2, 3)
    ushr r3.xyzw, r2.xyzw, l(5, 5, 5, 5)
    ushr r4.xy, r0.zzzz, l(5, 2, 0, 0)
    iadd r4.z, CB0[0][3].x, l(31)
    ushr r4.z, r4.z, l(5)
    imad r3.xyzw, r4.xxxx, r4.zzzz, r3.xyzw
    ishl r4.x, r0.z, l(7)
    and r4.xz, r4.xxxx, l(1792, 0, 2048, 0)
    bfi r5.xyzw, l(3, 3, 3, 3), l(5, 5, 5, 5), r2.xyzw, r4.xxxx
    bfi r5.xyzw, l(21, 21, 21, 21), l(11, 11, 11, 11), r3.xyzw, r5.xyzw
    bfi r4.w, l(1), l(4), r0.z, l(0)
    iadd r5.xyzw, r5.xyzw, r4.wwww
    ishl r6.xy, r4.xxxx, l(3, 2, 0, 0)
    bfi r7.xyzw, l(3, 3, 3, 3), l(8, 8, 8, 8), r2.xyzw, r6.xxxx
    bfi r7.xyzw, l(21, 21, 21, 21), l(14, 14, 14, 14), r3.xyzw, r7.xyzw
    imad r7.xyzw, r4.wwww, l(8, 8, 8, 8), r7.xyzw
    bfi r7.xyzw, l(12, 12, 12, 12), l(0, 0, 0, 0), r4.zzzz, r7.xyzw
    bfi r6.xyzw, l(3, 3, 3, 3), l(7, 7, 7, 7), r2.xyzw, r6.yyyy
    bfi r3.xyzw, l(21, 21, 21, 21), l(13, 13, 13, 13), r3.xyzw, r6.xyzw
    imad r3.xyzw, r4.wwww, l(4, 4, 4, 4), r3.xyzw
    and r3.xyzw, r3.xyzw, l(1792, 1792, 1792, 1792)
    iadd r3.xyzw, r7.xyzw, r3.xyzw
    ushr r2.xyzw, r2.xyzw, l(3, 3, 3, 3)
    and r4.x, r4.y, l(2)
    iadd r2.xyzw, r2.xyzw, r4.xxxx
    bfi r2.xyzw, l(2, 2, 2, 2), l(6, 6, 6, 6), r2.xyzw, l(0, 0, 0, 0)
    iadd r2.xyzw, r3.xyzw, r2.xyzw
    bfi r1.xyzw, l(6, 6, 6, 6), l(0, 0, 0, 0), r5.xyzw, r2.xyzw
  endif 
else 
  ishl r0.y, r0.y, l(4)
  iadd r2.x, CB0[0][2].y, l(31)
  and r2.x, r2.x, l(-32)
  imad r0.z, r0.w, r2.x, r0.z
  imad r0.y, r0.z, CB0[0][0].y, r0.y
  iadd r1.xyzw, r0.yyyy, l(0, 16, 32, 48)
endif 
iadd r1.xyzw, r1.xyzw, CB0[0][0].xxxx
ld_raw r2.xyzw, r1.x, T0[0].xyzw
ld_raw r3.xyzw, r1.y, T0[0].xyzw
ld_raw r4.xyzw, r1.z, T0[0].xyzw
ld_raw r1.xyzw, r1.w, T0[0].xyzw
ushr r0.y, CB0[0][2].w, l(1)
xor r0.y, r0.y, CB0[0][2].w
and r0.y, r0.y, l(1)
if_nz r0.y
  ishl r5.xyzw, r2.xyzw, l(8, 8, 8, 8)
  and r5.xyzw, r5.xyzw, l(0xff00ff00, 0xff00ff00, 0xff00ff00, 0xff00ff00)
  ushr r6.xyzw, r2.xyzw, l(8, 8, 8, 8)
  and r6.xyzw, r6.xyzw, l(0x00ff00ff, 0x00ff00ff, 0x00ff00ff, 0x00ff00ff)
  iadd r2.xyzw, r5.xyzw, r6.xyzw
endif 
and r0.z, CB0[0][2].w, l(2)
if_nz r0.z
  ushr r5.xyzw, r2.xyzw, l(16, 16, 16, 16)
  bfi r2.xyzw, l(16, 16, 16, 16), l(16, 16, 16, 16), r2.xyzw, r5.xyzw
endif 
if_nz r0.y
  ishl r5.xyzw, r3.xyzw, l(8, 8, 8, 8)
  and r5.xyzw, r5.xyzw, l(0xff00ff00, 0xff00ff00, 0xff00ff00, 0xff00ff00)
  ushr r6.xyzw, r3.xyzw, l(8, 8, 8, 8)
  and r6.xyzw, r6.xyzw, l(0x00ff00ff, 0x00ff00ff, 0x00ff00ff, 0x00ff00ff)
  iadd r3.xyzw, r5.xyzw, r6.xyzw
endif 
if_nz r0.z
  ushr r5.xyzw, r3.xyzw, l(16, 16, 16, 16)
  bfi r3.xyzw, l(16, 16, 16, 16), l(16, 16, 16, 16), r3.xyzw, r5.xyzw
endif 
if_nz r0.y
  ishl r5.xyzw, r4.xyzw, l(8, 8, 8, 8)
  and r5.xyzw, r5.xyzw, l(0xff00ff00, 0xff00ff00, 0xff00ff00, 0xff00ff00)
  ushr r6.xyzw, r4.xyzw, l(8, 8, 8, 8)
  and r6.xyzw, r6.xyzw, l(0x00ff00ff, 0x00ff00ff, 0x00ff00ff, 0x00ff00ff)
  iadd r4.xyzw, r5.xyzw, r6.xyzw
endif 
if_nz r0.z
  ushr r5.xyzw, r4.xyzw, l(16, 16, 16, 16)
  bfi r4.xyzw, l(16, 16, 16, 16), l(16, 16, 16, 16), r4.xyzw, r5.xyzw
endif 
if_nz r0.y
  ishl r5.xyzw, r1.xyzw, l(8, 8, 8, 8)
  and r5.xyzw, r5.xyzw, l(0xff00ff00, 0xff00ff00, 0xff00ff00, 0xff00ff00)
  ushr r6.xyzw, r1.xyzw, l(8, 8, 8, 8)
  and r6.xyzw, r6.xyzw, l(0x00ff00ff, 0x00ff00ff, 0x00ff00ff, 0x00ff00ff)
  iadd r1.xyzw, r5.xyzw, r6.xyzw
endif 
if_nz r0.z
  ushr r5.xyzw, r1.xyzw, l(16, 16, 16, 16)
  bfi r1.xyzw, l(16, 16, 16, 16), l(16, 16, 16, 16), r1.xyzw, r5.xyzw
endif 
ishl r0.x, r0.x, l(4)
imad r0.y, vThreadID.z, CB0[0][2].y, vThreadID.y
imad r0.x, r0.y, CB0[0][0].w, r0.x
iadd r0.x, r0.x, CB0[0][0].z
iadd r5.xyzw, r0.xxxx, l(0, 16, 32, 48)
store_raw U0[0].xyzw, r5.x, r2.xyzw
store_raw U0[0].xyzw, r5.y, r3.xyzw
store_raw U0[0].xyzw, r5.z, r4.xyzw
store_raw U0[0].xyzw, r5.w, r1.xyzw
ret 
// Approximately 145 instruction slots used
