//
// Generated by Microsoft (R) HLSL Shader Compiler 10.1
//
//
// Buffer Definitions: 
//
// cbuffer XeTextureTileConstants
// {
//
//   uint xe_texture_tile_guest_base;   // Offset:    0 Size:     4
//   uint xe_texture_tile_endian_format_guest_pitch;// Offset:    4 Size:     4
//   uint xe_texture_tile_offset;       // Offset:    8 Size:     4
//   uint xe_texture_tile_size;         // Offset:   12 Size:     4
//   uint xe_texture_tile_host_base;    // Offset:   16 Size:     4
//   uint xe_texture_tile_host_pitch;   // Offset:   20 Size:     4
//
// }
//
//
// Resource Bindings:
//
// Name                                 Type  Format         Dim      ID      HLSL Bind  Count
// ------------------------------ ---------- ------- ----------- ------- -------------- ------
// xe_texture_tile_source            texture    byte         r/o      T0             t0      1 
// xe_texture_tile_dest                  UAV    byte         r/w      U0             u0      1 
// XeTextureTileConstants            cbuffer      NA          NA     CB0            cb0      1 
//
//
//
// Input signature:
//
// Name                 Index   Mask Register SysValue  Format   Used
// -------------------- ----- ------ -------- -------- ------- ------
// no Input
//
// Output signature:
//
// Name                 Index   Mask Register SysValue  Format   Used
// -------------------- ----- ------ -------- -------- ------- ------
// no Output
cs_5_1
dcl_globalFlags refactoringAllowed
dcl_constantbuffer CB0[0:0][2], immediateIndexed, space=0
dcl_resource_raw T0[0:0], space=0
dcl_uav_raw U0[0:0], space=0
dcl_input vThreadID.xy
dcl_temps 9
dcl_thread_group 8, 32, 1
ushr r0.y, CB0[0][0].w, l(16)
mov r0.x, CB0[0][0].w
and r0.xy, r0.xyxx, l(0x0000ffff, 0x0000ffff, 0, 0)
ishl r1.x, vThreadID.x, l(2)
mov r1.y, vThreadID.y
uge r0.yz, r1.xxyx, r0.xxyx
or r0.y, r0.z, r0.y
if_nz r0.y
  ret 
endif 
ushr r2.xyz, CB0[0][0].zyyz, l(16, 9, 1, 0)
mov r2.w, CB0[0][0].z
and r0.yz, r2.wwxw, l(0, 0x0000ffff, 0x0000ffff, 0)
iadd r0.yz, r1.xxyx, r0.yyzy
iadd r3.xyzw, r0.yyyy, l(0, 1, 2, 3)
ushr r4.xyzw, r3.xyzw, l(5, 5, 5, 5)
ushr r0.yw, r0.zzzz, l(0, 5, 0, 2)
iadd r1.y, r2.y, l(31)
ushr r1.y, r1.y, l(5)
imad r4.xyzw, r0.yyyy, r1.yyyy, r4.xyzw
ishl r1.yz, r0.zzzz, l(0, 4, 7, 0)
and r1.yz, r1.yyzy, l(0, 224, 2048, 0)
bfi r5.xyzw, l(3, 3, 3, 3), l(2, 2, 2, 2), r3.xyzw, r1.yyyy
ishl r0.y, r1.y, l(1)
bfi r6.xyzw, l(3, 3, 3, 3), l(3, 3, 3, 3), r3.xyzw, r0.yyyy
and r6.xyzw, r6.xyzw, l(480, 480, 480, 480)
bfi r7.xyzw, l(23, 23, 23, 23), l(9, 9, 9, 9), r4.xyzw, r6.xyzw
bfi r7.xyzw, l(4, 4, 4, 4), l(0, 0, 0, 0), r5.xyzw, r7.xyzw
bfi r7.xyzw, l(1, 1, 1, 1), l(4, 4, 4, 4), r0.zzzz, r7.xyzw
ishl r8.xyzw, r6.xyzw, l(3, 3, 3, 3)
bfi r8.xyzw, l(23, 23, 23, 23), l(12, 12, 12, 12), r4.xyzw, r8.xyzw
bfi r8.xyzw, l(4, 4, 4, 4), l(3, 3, 3, 3), r5.xyzw, r8.xyzw
bfi r8.xyzw, l(1, 1, 1, 1), l(7, 7, 7, 7), r0.zzzz, r8.xyzw
bfi r8.xyzw, l(12, 12, 12, 12), l(0, 0, 0, 0), r1.zzzz, r8.xyzw
ishl r6.xyzw, r6.xyzw, l(2, 2, 2, 2)
bfi r4.xyzw, l(23, 23, 23, 23), l(11, 11, 11, 11), r4.xyzw, r6.xyzw
bfi r4.xyzw, l(4, 4, 4, 4), l(2, 2, 2, 2), r5.xyzw, r4.xyzw
bfi r4.xyzw, l(1, 1, 1, 1), l(6, 6, 6, 6), r0.zzzz, r4.xyzw
and r4.xyzw, r4.xyzw, l(1792, 1792, 1792, 1792)
iadd r4.xyzw, r8.xyzw, r4.xyzw
ushr r3.xyzw, r3.xyzw, l(3, 3, 3, 3)
and r0.y, r0.w, l(2)
iadd r3.xyzw, r0.yyyy, r3.xyzw
bfi r3.xyzw, l(2, 2, 2, 2), l(6, 6, 6, 6), r3.xyzw, l(0, 0, 0, 0)
iadd r3.xyzw, r4.xyzw, r3.xyzw
bfi r3.xyzw, l(6, 6, 6, 6), l(0, 0, 0, 0), r7.xyzw, r3.xyzw
iadd r3.xyzw, r3.xyzw, CB0[0][0].xxxx
imad r0.yzw, vThreadID.xxxx, l(0, 4, 4, 4), l(0, 1, 2, 3)
ult r0.xyz, r0.yzwy, r0.xxxx
imad r0.w, vThreadID.y, CB0[0][1].y, CB0[0][1].x
ishl r1.x, r1.x, l(3)
iadd r0.w, r0.w, r1.x
ld_raw r1.xyzw, r0.w, T0[0].xyzw
ubfe r2.xy, l(11, 11, 0, 0), l(5, 5, 0, 0), r1.xzxx
ushr r1.xyzw, r1.xzyw, l(21, 21, 6, 6)
imad r4.xy, r1.xyxx, l(2048, 2048, 0, 0), r2.xyxx
bfi r4.xy, l(10, 10, 0, 0), l(22, 22, 0, 0), r1.zwzz, r4.xyxx
xor r2.z, r2.z, CB0[0][0].y
and r2.z, r2.z, l(1)
if_nz r2.z
  ishl r2.xy, r2.xyxx, l(8, 8, 0, 0)
  imad r1.xy, r1.xyxx, l(0x00080000, 0x00080000, 0, 0), r2.xyxx
  bfi r1.xy, l(10, 10, 0, 0), l(30, 30, 0, 0), r1.zwzz, r1.xyxx
  ushr r1.zw, r4.xxxy, l(0, 0, 8, 8)
  and r1.xyzw, r1.xyzw, l(0xff00ff00, 0xff00ff00, 0x00ff00ff, 0x00ff00ff)
  iadd r4.xy, r1.zwzz, r1.xyxx
endif 
and r1.x, CB0[0][0].y, l(2)
if_nz r1.x
  ushr r1.yz, r4.xxyx, l(0, 16, 16, 0)
  bfi r4.xy, l(16, 16, 0, 0), l(16, 16, 0, 0), r4.xyxx, r1.yzyy
endif 
store_raw U0[0].x, r3.x, r4.x
if_nz r0.x
  store_raw U0[0].x, r3.y, r4.y
  if_nz r0.y
    iadd r0.x, r0.w, l(16)
    ld_raw r4.xyzw, r0.x, T0[0].xyzw
    ubfe r0.xy, l(11, 11, 0, 0), l(5, 5, 0, 0), r4.xzxx
    ushr r4.xyzw, r4.xzyw, l(21, 21, 6, 6)
    imad r1.yz, r4.xxyx, l(0, 2048, 2048, 0), r0.xxyx
    bfi r1.yz, l(0, 10, 10, 0), l(0, 22, 22, 0), r4.zzwz, r1.yyzy
    if_nz r2.z
      ishl r0.xy, r0.xyxx, l(8, 8, 0, 0)
      imad r0.xy, r4.xyxx, l(0x00080000, 0x00080000, 0, 0), r0.xyxx
      bfi r0.xy, l(10, 10, 0, 0), l(30, 30, 0, 0), r4.zwzz, r0.xyxx
      and r0.xy, r0.xyxx, l(0xff00ff00, 0xff00ff00, 0, 0)
      ushr r2.xy, r1.yzyy, l(8, 8, 0, 0)
      and r2.xy, r2.xyxx, l(0x00ff00ff, 0x00ff00ff, 0, 0)
      iadd r1.yz, r0.xxyx, r2.xxyx
    endif 
    if_nz r1.x
      ushr r0.xy, r1.yzyy, l(16, 16, 0, 0)
      bfi r1.yz, l(0, 16, 16, 0), l(0, 16, 16, 0), r1.yyzy, r0.xxyx
    endif 
    store_raw U0[0].x, r3.z, r1.y
    if_nz r0.z
      store_raw U0[0].x, r3.w, r1.z
    endif 
  endif 
endif 
ret 
// Approximately 102 instruction slots used
