//
// Generated by Microsoft (R) HLSL Shader Compiler 10.1
//
//
// Buffer Definitions: 
//
// cbuffer XeTextureLoadConstants
// {
//
//   uint xe_texture_load_is_tiled_3d_endian;// Offset:    0 Size:     4
//   uint xe_texture_load_guest_offset; // Offset:    4 Size:     4
//   uint xe_texture_load_guest_pitch_aligned;// Offset:    8 Size:     4
//   uint xe_texture_load_guest_z_stride_block_rows_aligned;// Offset:   12 Size:     4
//   uint3 xe_texture_load_size_blocks; // Offset:   16 Size:    12
//   uint xe_texture_load_host_offset;  // Offset:   28 Size:     4
//   uint xe_texture_load_host_pitch;   // Offset:   32 Size:     4
//   uint xe_texture_load_height_texels;// Offset:   36 Size:     4 [unused]
//
// }
//
//
// Resource Bindings:
//
// Name                                 Type  Format         Dim      ID      HLSL Bind  Count
// ------------------------------ ---------- ------- ----------- ------- -------------- ------
// xe_texture_load_source            texture   uint4         buf      T0             t0      1 
// xe_texture_load_dest                  UAV   uint4         buf      U0             u0      1 
// XeTextureLoadConstants            cbuffer      NA          NA     CB0            cb0      1 
//
//
//
// Input signature:
//
// Name                 Index   Mask Register SysValue  Format   Used
// -------------------- ----- ------ -------- -------- ------- ------
// no Input
//
// Output signature:
//
// Name                 Index   Mask Register SysValue  Format   Used
// -------------------- ----- ------ -------- -------- ------- ------
// no Output
cs_5_1
dcl_globalFlags refactoringAllowed
dcl_constantbuffer CB0[0:0][3], immediateIndexed, space=0
dcl_resource_buffer (uint,uint,uint,uint) T0[0:0], space=0
dcl_uav_typed_buffer (uint,uint,uint,uint) U0[0:0], space=0
dcl_input vThreadID.xyz
dcl_temps 7
dcl_thread_group 4, 32, 1
ishl r0.x, vThreadID.x, l(3)
mov r0.yz, vThreadID.yyzy
uge r0.yzw, r0.xxyz, CB0[0][1].xxyz
or r0.y, r0.z, r0.y
or r0.y, r0.w, r0.y
if_nz r0.y
  ret 
endif 
ishl r0.y, r0.x, l(3)
imad r0.z, vThreadID.z, CB0[0][1].y, vThreadID.y
imad r0.y, r0.z, CB0[0][2].x, r0.y
iadd r0.y, r0.y, CB0[0][1].w
and r0.z, CB0[0][0].x, l(1)
if_nz r0.z
  and r0.w, CB0[0][0].x, l(2)
  if_nz r0.w
    ishr r1.xyz, vThreadID.yzyy, l(4, 2, 3, 0)
    ushr r2.xy, CB0[0][0].wzww, l(4, 5, 0, 0)
    imad r0.w, r1.y, r2.x, r1.x
    ibfe r1.xw, l(27, 0, 0, 29), l(2, 0, 0, 0), vThreadID.xxxx
    imad r0.w, r0.w, r2.y, r1.x
    ishl r1.x, vThreadID.y, l(10)
    ishr r1.x, r1.x, l(6)
    and r1.x, r1.x, l(96)
    iadd r1.y, r1.y, r1.z
    bfi r1.z, l(1), l(1), r1.y, l(0)
    iadd r1.z, r1.z, r1.w
    bfi r1.z, l(2), l(1), r1.z, l(0)
    bfi r1.y, l(1), l(0), r1.y, r1.z
    bfi r1.zw, l(0, 0, 20, 20), l(0, 0, 10, 13), r0.wwww, l(0, 0, 0, 0)
    imad r1.xz, r1.xxxx, l(2, 0, 16, 0), r1.zzwz
    bfi r1.xz, l(2, 0, 2, 0), l(8, 0, 11, 0), vThreadID.zzzz, r1.xxzx
    bfi r0.w, l(1), l(4), vThreadID.y, l(0)
    ubfe r1.w, l(3), l(6), r1.x
    and r2.x, r1.y, l(6)
    bfi r1.y, l(1), l(8), r1.y, l(0)
    imad r1.y, r1.w, l(32), r1.y
    imad r1.y, r2.x, l(4), r1.y
    bfi r1.xz, l(6, 0, 6, 0), l(0, 0, 3, 0), r0.wwww, r1.xxzx
    bfi r0.w, l(9), l(3), r1.y, r1.z
    bfi r0.w, l(6), l(0), r1.x, r0.w
  else 
    ibfe r1.xy, l(27, 29, 0, 0), l(2, 0, 0, 0), vThreadID.xxxx
    ishr r1.zw, vThreadID.yyyy, l(0, 0, 5, 2)
    ushr r2.x, CB0[0][0].z, l(5)
    imad r1.x, r1.z, r2.x, r1.x
    ishl r2.xy, vThreadID.yyyy, l(5, 7, 0, 0)
    and r2.xy, r2.xyxx, l(448, 2048, 0, 0)
    bfi r1.z, l(23), l(9), r1.x, r2.x
    bfi r2.z, l(1), l(4), vThreadID.y, l(0)
    iadd r1.z, r1.z, r2.z
    ishl r2.xw, r2.xxxx, l(3, 0, 0, 2)
    bfi r2.xw, l(23, 0, 0, 23), l(12, 0, 0, 11), r1.xxxx, r2.xxxw
    imad r2.xz, r2.zzzz, l(8, 0, 4, 0), r2.xxwx
    bfi r1.x, l(12), l(0), r2.y, r2.x
    and r2.x, r2.z, l(1792)
    iadd r1.x, r1.x, r2.x
    and r1.w, r1.w, l(2)
    iadd r1.y, r1.y, r1.w
    bfi r1.y, l(2), l(6), r1.y, l(0)
    iadd r1.x, r1.x, r1.y
    bfi r0.w, l(6), l(0), r1.z, r1.x
  endif 
else 
  ishl r0.x, r0.x, l(2)
  imad r1.x, vThreadID.z, CB0[0][0].w, vThreadID.y
  imad r0.w, r1.x, CB0[0][0].z, r0.x
endif 
iadd r0.x, r0.w, CB0[0][0].y
ushr r0.xy, r0.xyxx, l(4, 4, 0, 0)
ushr r0.w, CB0[0][0].x, l(2)
ld r1.xyzw, r0.xxxx, T0[0].zwxy
ieq r2.xyz, r0.wwww, l(1, 2, 3, 0)
or r2.xy, r2.yzyy, r2.xyxx
if_nz r2.x
  ishl r3.xyzw, r1.zwxy, l(8, 8, 8, 8)
  and r3.xyzw, r3.xyzw, l(0xff00ff00, 0xff00ff00, 0xff00ff00, 0xff00ff00)
  ushr r4.xyzw, r1.zwxy, l(8, 8, 8, 8)
  and r4.xyzw, r4.xyzw, l(0x00ff00ff, 0x00ff00ff, 0x00ff00ff, 0x00ff00ff)
  iadd r1.xyzw, r3.zwxy, r4.zwxy
endif 
if_nz r2.y
  ushr r3.xyzw, r1.zwxy, l(16, 16, 16, 16)
  bfi r1.xyzw, l(16, 16, 16, 16), l(16, 16, 16, 16), r1.xyzw, r3.zwxy
  mov r3.xy, r1.zwzz
else 
  mov r3.xy, r1.zwzz
endif 
ushr r4.xyzw, r3.xyxy, l(22, 22, 1, 1)
mov r3.zw, r4.xxxy
bfi r5.xyzw, l(11, 26, 11, 26), l(5, 6, 5, 6), r3.xzyw, l(0, 0, 0, 0)
ubfe r6.xyzw, l(5, 6, 5, 6), l(6, 26, 6, 26), r3.xxyy
iadd r5.xyzw, r5.xyzw, r6.xyzw
ishl r2.zw, r3.xxxy, l(0, 0, 10, 10)
and r3.xy, r4.zwzz, l(0x001f0000, 0x001f0000, 0, 0)
bfi r2.zw, l(0, 0, 21, 21), l(0, 0, 0, 0), r3.xxxy, r2.zzzw
iadd r3.xz, r2.zzwz, r5.xxzx
iadd r3.yw, r5.yyyw, l(0, 0xffff0000, 0, 0xffff0000)
ushr r4.xyzw, r1.xyxy, l(22, 22, 1, 1)
mov r1.zw, r4.xxxy
bfi r5.xyzw, l(11, 26, 11, 26), l(5, 6, 5, 6), r1.xzyw, l(0, 0, 0, 0)
ubfe r6.xyzw, l(5, 6, 5, 6), l(6, 26, 6, 26), r1.xxyy
iadd r5.xyzw, r5.xyzw, r6.xyzw
ishl r1.xy, r1.xyxx, l(10, 10, 0, 0)
and r1.zw, r4.zzzw, l(0, 0, 0x001f0000, 0x001f0000)
bfi r1.xy, l(21, 21, 0, 0), l(0, 0, 0, 0), r1.zwzz, r1.xyxx
iadd r1.xz, r1.xxyx, r5.xxzx
iadd r1.yw, r5.yyyw, l(0, 0xffff0000, 0, 0xffff0000)
store_uav_typed U0[0].xyzw, r0.yyyy, r3.xyzw
iadd r3.xyz, r0.yyyy, l(1, 2, 3, 0)
store_uav_typed U0[0].xyzw, r3.xxxx, r1.xyzw
movc r0.z, r0.z, l(2), l(1)
iadd r0.x, r0.z, r0.x
ld r1.xyzw, r0.xxxx, T0[0].zwxy
if_nz r2.x
  ishl r4.xyzw, r1.zwxy, l(8, 8, 8, 8)
  and r4.xyzw, r4.xyzw, l(0xff00ff00, 0xff00ff00, 0xff00ff00, 0xff00ff00)
  ushr r5.xyzw, r1.zwxy, l(8, 8, 8, 8)
  and r5.xyzw, r5.xyzw, l(0x00ff00ff, 0x00ff00ff, 0x00ff00ff, 0x00ff00ff)
  iadd r1.xyzw, r4.zwxy, r5.zwxy
endif 
if_nz r2.y
  ushr r2.xyzw, r1.zwxy, l(16, 16, 16, 16)
  bfi r1.xyzw, l(16, 16, 16, 16), l(16, 16, 16, 16), r1.xyzw, r2.zwxy
  mov r2.xy, r1.zwzz
else 
  mov r2.xy, r1.zwzz
endif 
ushr r4.xyzw, r2.xyxy, l(22, 22, 1, 1)
mov r2.zw, r4.xxxy
bfi r5.xyzw, l(11, 26, 11, 26), l(5, 6, 5, 6), r2.xzyw, l(0, 0, 0, 0)
ubfe r6.xyzw, l(5, 6, 5, 6), l(6, 26, 6, 26), r2.xxyy
iadd r5.xyzw, r5.xyzw, r6.xyzw
ishl r0.xz, r2.xxyx, l(10, 0, 10, 0)
and r2.xy, r4.zwzz, l(0x001f0000, 0x001f0000, 0, 0)
bfi r0.xz, l(21, 0, 21, 0), l(0, 0, 0, 0), r2.xxyx, r0.xxzx
iadd r2.xz, r0.xxzx, r5.xxzx
iadd r2.yw, r5.yyyw, l(0, 0xffff0000, 0, 0xffff0000)
ushr r4.xyzw, r1.xyxy, l(22, 22, 1, 1)
mov r1.zw, r4.xxxy
bfi r5.xyzw, l(11, 26, 11, 26), l(5, 6, 5, 6), r1.xzyw, l(0, 0, 0, 0)
ubfe r6.xyzw, l(5, 6, 5, 6), l(6, 26, 6, 26), r1.xxyy
iadd r5.xyzw, r5.xyzw, r6.xyzw
ishl r0.xz, r1.xxyx, l(10, 0, 10, 0)
and r1.xy, r4.zwzz, l(0x001f0000, 0x001f0000, 0, 0)
bfi r0.xz, l(21, 0, 21, 0), l(0, 0, 0, 0), r1.xxyx, r0.xxzx
iadd r1.xz, r0.xxzx, r5.xxzx
iadd r1.yw, r5.yyyw, l(0, 0xffff0000, 0, 0xffff0000)
store_uav_typed U0[0].xyzw, r3.yyyy, r2.xyzw
store_uav_typed U0[0].xyzw, r3.zzzz, r1.xyzw
ret 
// Approximately 151 instruction slots used
