//
// Generated by Microsoft (R) HLSL Shader Compiler 10.1
//
//
// Buffer Definitions: 
//
// cbuffer XeTextureLoadConstants
// {
//
//   uint xe_texture_load_is_tiled_3d_endian;// Offset:    0 Size:     4
//   uint xe_texture_load_guest_offset; // Offset:    4 Size:     4
//   uint xe_texture_load_guest_pitch_aligned;// Offset:    8 Size:     4
//   uint xe_texture_load_guest_z_stride_block_rows_aligned;// Offset:   12 Size:     4
//   uint3 xe_texture_load_size_blocks; // Offset:   16 Size:    12
//   uint xe_texture_load_host_offset;  // Offset:   28 Size:     4
//   uint xe_texture_load_host_pitch;   // Offset:   32 Size:     4
//   uint xe_texture_load_height_texels;// Offset:   36 Size:     4 [unused]
//
// }
//
//
// Resource Bindings:
//
// Name                                 Type  Format         Dim      ID      HLSL Bind  Count
// ------------------------------ ---------- ------- ----------- ------- -------------- ------
// xe_texture_load_source            texture   uint2         buf      T0             t0      1 
// xe_texture_load_dest                  UAV   uint2         buf      U0             u0      1 
// XeTextureLoadConstants            cbuffer      NA          NA     CB0            cb0      1 
//
//
//
// Input signature:
//
// Name                 Index   Mask Register SysValue  Format   Used
// -------------------- ----- ------ -------- -------- ------- ------
// no Input
//
// Output signature:
//
// Name                 Index   Mask Register SysValue  Format   Used
// -------------------- ----- ------ -------- -------- ------- ------
// no Output
cs_5_1
dcl_globalFlags refactoringAllowed
dcl_constantbuffer CB0[0:0][3], immediateIndexed, space=0
dcl_resource_buffer (uint,uint,uint,uint) T0[0:0], space=0
dcl_uav_typed_buffer (uint,uint,uint,uint) U0[0:0], space=0
dcl_input vThreadID.xyz
dcl_temps 10
dcl_thread_group 16, 32, 1
ishl r0.x, vThreadID.x, l(1)
mov r0.yz, vThreadID.yyzy
uge r1.xyz, r0.xyzx, CB0[0][1].xyzx
or r0.w, r1.y, r1.x
or r0.w, r1.z, r0.w
if_nz r0.w
  ret 
endif 
mov r1.x, l(3)
mov r1.z, CB0[0][1].y
imul null, r0.yzw, r0.xxyz, r1.xxxz
ishl r0.y, r0.y, l(2)
imad r0.z, l(3), r0.w, r0.z
imad r0.y, r0.z, CB0[0][2].x, r0.y
iadd r0.y, r0.y, CB0[0][1].w
ushr r0.z, CB0[0][2].x, l(3)
and r0.w, CB0[0][0].x, l(1)
if_nz r0.w
  and r0.w, CB0[0][0].x, l(2)
  if_nz r0.w
    ishr r1.xyz, vThreadID.yzyy, l(4, 2, 3, 0)
    ushr r2.xy, CB0[0][0].wzww, l(4, 5, 0, 0)
    imad r0.w, r1.y, r2.x, r1.x
    ibfe r1.xw, l(27, 0, 0, 29), l(4, 0, 0, 2), vThreadID.xxxx
    imad r0.w, r0.w, r2.y, r1.x
    ishl r1.x, vThreadID.y, l(10)
    and r1.x, r1.x, l(6144)
    bfi r1.x, l(3), l(8), r0.x, r1.x
    ishr r1.x, r1.x, l(6)
    iadd r1.y, r1.y, r1.z
    bfi r1.z, l(1), l(1), r1.y, l(0)
    iadd r1.z, r1.z, r1.w
    bfi r1.z, l(2), l(1), r1.z, l(0)
    bfi r1.y, l(1), l(0), r1.y, r1.z
    and r1.z, r1.x, l(112)
    bfi r2.xy, l(20, 20, 0, 0), l(10, 13, 0, 0), r0.wwww, l(0, 0, 0, 0)
    imad r1.zw, r1.zzzz, l(0, 0, 2, 16), r2.xxxy
    bfi r1.xz, l(4, 0, 4, 0), l(0, 0, 3, 0), r1.xxxx, r1.zzwz
    bfi r1.xz, l(2, 0, 2, 0), l(8, 0, 11, 0), vThreadID.zzzz, r1.xxzx
    ubfe r0.w, l(3), l(6), r1.x
    and r1.w, r1.y, l(6)
    bfi r1.y, l(1), l(8), r1.y, l(0)
    imad r0.w, r0.w, l(32), r1.y
    imad r0.w, r1.w, l(4), r0.w
    bfi r1.xy, l(1, 1, 0, 0), l(4, 7, 0, 0), vThreadID.yyyy, r1.xzxx
    bfi r0.w, l(9), l(3), r0.w, r1.y
    bfi r0.w, l(6), l(0), r1.x, r0.w
  else 
    ibfe r1.xy, l(27, 29, 0, 0), l(4, 2, 0, 0), vThreadID.xxxx
    ishr r1.zw, vThreadID.yyyy, l(0, 0, 5, 2)
    ushr r2.x, CB0[0][0].z, l(5)
    imad r1.x, r1.z, r2.x, r1.x
    ishl r2.xy, vThreadID.yyyy, l(4, 7, 0, 0)
    and r2.xy, r2.xyxx, l(224, 2048, 0, 0)
    bfi r1.z, l(3), l(2), r0.x, r2.x
    ishl r2.x, r2.x, l(1)
    bfi r2.x, l(3), l(3), r0.x, r2.x
    and r2.x, r2.x, l(480)
    bfi r2.z, l(23), l(9), r1.x, r2.x
    bfi r2.z, l(4), l(0), r1.z, r2.z
    bfi r2.z, l(1), l(4), vThreadID.y, r2.z
    ishl r2.xw, r2.xxxx, l(3, 0, 0, 2)
    bfi r2.xw, l(23, 0, 0, 23), l(12, 0, 0, 11), r1.xxxx, r2.xxxw
    bfi r1.xz, l(4, 0, 4, 0), l(3, 0, 2, 0), r1.zzzz, r2.xxwx
    bfi r1.xz, l(1, 0, 1, 0), l(7, 0, 6, 0), vThreadID.yyyy, r1.xxzx
    bfi r1.x, l(12), l(0), r2.y, r1.x
    and r1.z, r1.z, l(1792)
    iadd r1.x, r1.x, r1.z
    and r1.z, r1.w, l(2)
    iadd r1.y, r1.y, r1.z
    bfi r1.y, l(2), l(6), r1.y, l(0)
    iadd r1.x, r1.x, r1.y
    bfi r0.w, l(6), l(0), r2.z, r1.x
  endif 
else 
  ishl r0.x, r0.x, l(2)
  imad r1.x, vThreadID.z, CB0[0][0].w, vThreadID.y
  imad r0.w, r1.x, CB0[0][0].z, r0.x
endif 
iadd r0.x, r0.w, CB0[0][0].y
imul null, r0.x, r0.x, l(9)
ushr r0.xy, r0.xyxx, l(3, 3, 0, 0)
ushr r0.w, CB0[0][0].x, l(2)
ld r1.xy, r0.xxxx, T0[0].xyzw
iadd r2.xyzw, r0.xxxx, l(1, 2, 3, 4)
ld r1.zw, r2.xxxx, T0[0].zwxy
ieq r3.xyz, r0.wwww, l(1, 2, 3, 0)
or r3.xy, r3.yzyy, r3.xyxx
if_nz r3.x
  ishl r4.xyzw, r1.xyzw, l(8, 8, 8, 8)
  and r4.xyzw, r4.xyzw, l(0xff00ff00, 0xff00ff00, 0xff00ff00, 0xff00ff00)
  ushr r5.xyzw, r1.xyzw, l(8, 8, 8, 8)
  and r5.xyzw, r5.xyzw, l(0x00ff00ff, 0x00ff00ff, 0x00ff00ff, 0x00ff00ff)
  iadd r1.xyzw, r4.xyzw, r5.xyzw
endif 
if_nz r3.y
  ushr r4.xyzw, r1.xyzw, l(16, 16, 16, 16)
  bfi r1.xyzw, l(16, 16, 16, 16), l(16, 16, 16, 16), r1.xyzw, r4.xyzw
endif 
ushr r4.xyzw, r1.xyzw, l(8, 8, 8, 8)
ubfe r1.xyzw, l(20, 20, 20, 20), l(8, 8, 8, 8), r1.xyzw
ushr r5.xyzw, r4.xyzw, l(20, 20, 20, 20)
firstbit_hi r6.xyzw, r1.xyzw
iadd r6.xyzw, r6.xyzw, l(-11, -11, -11, -11)
movc r6.xyzw, r1.xyzw, r6.xyzw, l(21,21,21,21)
iadd r7.xyzw, -r6.xyzw, l(1, 1, 1, 1)
movc r7.xyzw, r5.xyzw, r5.xyzw, r7.xyzw
ishl r6.xyzw, r1.xyzw, r6.xyzw
and r6.xyzw, r6.xyzw, l(0x000fffff, 0x000fffff, 0x000fffff, 0x000fffff)
movc r1.xyzw, r5.xyzw, r1.xyzw, r6.xyzw
ishl r5.xyzw, r7.xyzw, l(23, 23, 23, 23)
iadd r5.xyzw, r5.xyzw, l(0x38000000, 0x38000000, 0x38000000, 0x38000000)
ishl r1.xyzw, r1.xyzw, l(3, 3, 3, 3)
iadd r1.xyzw, r5.xyzw, r1.xyzw
movc r1.xyzw, r4.xyzw, r1.xyzw, l(0,0,0,0)
store_uav_typed U0[0].xyzw, r0.yyyy, r1.xyxx
ld r4.xy, r2.yyyy, T0[0].xyzw
ld r4.zw, r2.zzzz, T0[0].zwxy
if_nz r3.x
  ishl r5.xyzw, r4.xyzw, l(8, 8, 8, 8)
  and r5.xyzw, r5.xyzw, l(0xff00ff00, 0xff00ff00, 0xff00ff00, 0xff00ff00)
  ushr r6.xyzw, r4.xyzw, l(8, 8, 8, 8)
  and r6.xyzw, r6.xyzw, l(0x00ff00ff, 0x00ff00ff, 0x00ff00ff, 0x00ff00ff)
  iadd r4.xyzw, r5.xyzw, r6.xyzw
endif 
if_nz r3.y
  ushr r5.xyzw, r4.xyzw, l(16, 16, 16, 16)
  bfi r4.xyzw, l(16, 16, 16, 16), l(16, 16, 16, 16), r4.xyzw, r5.xyzw
endif 
ushr r5.xyzw, r4.xyzw, l(8, 8, 8, 8)
ubfe r4.xyzw, l(20, 20, 20, 20), l(8, 8, 8, 8), r4.xyzw
ushr r6.xyzw, r5.xyzw, l(20, 20, 20, 20)
firstbit_hi r7.xyzw, r4.xyzw
iadd r7.xyzw, r7.xyzw, l(-11, -11, -11, -11)
movc r7.xyzw, r4.xyzw, r7.xyzw, l(21,21,21,21)
iadd r8.xyzw, -r7.xyzw, l(1, 1, 1, 1)
movc r8.xyzw, r6.xyzw, r6.xyzw, r8.xyzw
ishl r7.xyzw, r4.xyzw, r7.xyzw
and r7.xyzw, r7.xyzw, l(0x000fffff, 0x000fffff, 0x000fffff, 0x000fffff)
movc r4.xyzw, r6.xyzw, r4.xyzw, r7.xyzw
ishl r6.xyzw, r8.xyzw, l(23, 23, 23, 23)
iadd r6.xyzw, r6.xyzw, l(0x38000000, 0x38000000, 0x38000000, 0x38000000)
ishl r4.xyzw, r4.xyzw, l(3, 3, 3, 3)
iadd r4.xyzw, r6.xyzw, r4.xyzw
movc r4.xyzw, r5.xyzw, r4.xyzw, l(0,0,0,0)
iadd r0.w, r0.z, r0.y
mov r5.xzw, r1.wwww
mov r5.y, r4.x
store_uav_typed U0[0].xyzw, r0.wwww, r5.xyzw
ishl r0.z, r0.z, l(1)
iadd r0.z, r0.z, r0.y
store_uav_typed U0[0].xyzw, r0.zzzz, r4.zwzz
ld r2.xy, r2.wwww, T0[0].xyzw
iadd r5.xyzw, r0.xxxx, l(5, 6, 7, 8)
ld r2.zw, r5.xxxx, T0[0].zwxy
if_nz r3.x
  ishl r6.xyzw, r2.xyzw, l(8, 8, 8, 8)
  and r6.xyzw, r6.xyzw, l(0xff00ff00, 0xff00ff00, 0xff00ff00, 0xff00ff00)
  ushr r7.xyzw, r2.xyzw, l(8, 8, 8, 8)
  and r7.xyzw, r7.xyzw, l(0x00ff00ff, 0x00ff00ff, 0x00ff00ff, 0x00ff00ff)
  iadd r2.xyzw, r6.xyzw, r7.xyzw
endif 
if_nz r3.y
  ushr r6.xyzw, r2.xyzw, l(16, 16, 16, 16)
  bfi r2.xyzw, l(16, 16, 16, 16), l(16, 16, 16, 16), r2.xyzw, r6.xyzw
endif 
ushr r6.xyzw, r2.xyzw, l(8, 8, 8, 8)
ubfe r2.xyzw, l(20, 20, 20, 20), l(8, 8, 8, 8), r2.xyzw
ushr r7.xyzw, r6.xyzw, l(20, 20, 20, 20)
firstbit_hi r8.xyzw, r2.xyzw
iadd r8.xyzw, r8.xyzw, l(-11, -11, -11, -11)
movc r8.xyzw, r2.xyzw, r8.xyzw, l(21,21,21,21)
iadd r9.xyzw, -r8.xyzw, l(1, 1, 1, 1)
movc r9.xyzw, r7.xyzw, r7.xyzw, r9.xyzw
ishl r8.xyzw, r2.xyzw, r8.xyzw
and r8.xyzw, r8.xyzw, l(0x000fffff, 0x000fffff, 0x000fffff, 0x000fffff)
movc r2.xyzw, r7.xyzw, r2.xyzw, r8.xyzw
ishl r7.xyzw, r9.xyzw, l(23, 23, 23, 23)
iadd r7.xyzw, r7.xyzw, l(0x38000000, 0x38000000, 0x38000000, 0x38000000)
ishl r2.xyzw, r2.xyzw, l(3, 3, 3, 3)
iadd r2.xyzw, r7.xyzw, r2.xyzw
movc r2.xyzw, r6.xyzw, r2.xyzw, l(0,0,0,0)
iadd r1.xy, r0.yyyy, l(1, 2, 0, 0)
mov r6.xzw, r1.zzzz
mov r6.y, r2.y
store_uav_typed U0[0].xyzw, r1.xxxx, r6.xyzw
store_uav_typed U0[0].xyzw, r1.yyyy, r2.zwzz
ld r1.xy, r5.yyyy, T0[0].xyzw
ld r1.zw, r5.zzzz, T0[0].zwxy
if_nz r3.x
  ishl r6.xyzw, r1.xyzw, l(8, 8, 8, 8)
  and r6.xyzw, r6.xyzw, l(0xff00ff00, 0xff00ff00, 0xff00ff00, 0xff00ff00)
  ushr r7.xyzw, r1.xyzw, l(8, 8, 8, 8)
  and r7.xyzw, r7.xyzw, l(0x00ff00ff, 0x00ff00ff, 0x00ff00ff, 0x00ff00ff)
  iadd r1.xyzw, r6.xyzw, r7.xyzw
endif 
if_nz r3.y
  ushr r6.xyzw, r1.xyzw, l(16, 16, 16, 16)
  bfi r1.xyzw, l(16, 16, 16, 16), l(16, 16, 16, 16), r1.xyzw, r6.xyzw
endif 
ushr r6.xyzw, r1.xyzw, l(8, 8, 8, 8)
ubfe r1.xyzw, l(20, 20, 20, 20), l(8, 8, 8, 8), r1.xyzw
ushr r7.xyzw, r6.xyzw, l(20, 20, 20, 20)
firstbit_hi r8.xyzw, r1.xyzw
iadd r8.xyzw, r8.xyzw, l(-11, -11, -11, -11)
movc r8.xyzw, r1.xyzw, r8.xyzw, l(21,21,21,21)
iadd r9.xyzw, -r8.xyzw, l(1, 1, 1, 1)
movc r9.xyzw, r7.xyzw, r7.xyzw, r9.xyzw
ishl r8.xyzw, r1.xyzw, r8.xyzw
and r8.xyzw, r8.xyzw, l(0x000fffff, 0x000fffff, 0x000fffff, 0x000fffff)
movc r1.xyzw, r7.xyzw, r1.xyzw, r8.xyzw
ishl r7.xyzw, r9.xyzw, l(23, 23, 23, 23)
iadd r7.xyzw, r7.xyzw, l(0x38000000, 0x38000000, 0x38000000, 0x38000000)
ishl r1.xyzw, r1.xyzw, l(3, 3, 3, 3)
iadd r1.xyzw, r7.xyzw, r1.xyzw
movc r1.xyzw, r6.xwyz, r1.xwyz, l(0,0,0,0)
iadd r0.xy, r0.wwww, l(1, 2, 0, 0)
mov r4.xzw, r4.yyyy
mov r4.y, r1.x
store_uav_typed U0[0].xyzw, r0.xxxx, r4.xyzw
store_uav_typed U0[0].xyzw, r0.yyyy, r1.zwzz
iadd r0.xy, r0.zzzz, l(1, 2, 0, 0)
mov r1.xzw, r2.xxxx
store_uav_typed U0[0].xyzw, r0.xxxx, r1.xyzw
ld r0.xw, r5.wwww, T0[0].xzwy
if_nz r3.x
  ishl r1.xy, r0.xwxx, l(8, 8, 0, 0)
  ushr r1.zw, r0.xxxw, l(0, 0, 8, 8)
  and r1.xyzw, r1.xyzw, l(0xff00ff00, 0xff00ff00, 0x00ff00ff, 0x00ff00ff)
  iadd r0.xw, r1.zzzw, r1.xxxy
endif 
if_nz r3.y
  ushr r1.xy, r0.xwxx, l(16, 16, 0, 0)
  bfi r0.xw, l(16, 0, 0, 16), l(16, 0, 0, 16), r0.xxxw, r1.xxxy
endif 
ushr r1.xyzw, r0.xwxx, l(8, 8, 8, 8)
ubfe r2.xyzw, l(20, 20, 20, 20), l(8, 8, 8, 8), r0.xwxx
ushr r3.xyzw, r1.wyww, l(20, 20, 20, 20)
firstbit_hi r4.xyzw, r2.wyww
iadd r4.xyzw, r4.xyzw, l(-11, -11, -11, -11)
movc r4.xyzw, r2.wyww, r4.xyzw, l(21,21,21,21)
iadd r5.xyzw, -r4.wyww, l(1, 1, 1, 1)
movc r5.xyzw, r3.wyww, r3.wyww, r5.xyzw
ishl r4.xyzw, r2.wyww, r4.xyzw
and r4.xyzw, r4.xyzw, l(0x000fffff, 0x000fffff, 0x000fffff, 0x000fffff)
movc r2.xyzw, r3.xyzw, r2.xyzw, r4.xyzw
ishl r3.xyzw, r5.xyzw, l(23, 23, 23, 23)
iadd r3.xyzw, r3.xyzw, l(0x38000000, 0x38000000, 0x38000000, 0x38000000)
ishl r2.xyzw, r2.xyzw, l(3, 3, 3, 3)
iadd r2.xyzw, r3.xyzw, r2.xyzw
movc r1.xyzw, r1.xyzw, r2.xyzw, l(0,0,0,0)
store_uav_typed U0[0].xyzw, r0.yyyy, r1.xyzw
ret 
// Approximately 253 instruction slots used
