//
// Generated by Microsoft (R) HLSL Shader Compiler 10.1
//
//
// Buffer Definitions: 
//
// cbuffer XeEDRAMLoadStoreConstants
// {
//
//   uint4 xe_edram_load_store_constants;// Offset:    0 Size:    16
//   uint xe_edram_base_pitch_tiles;    // Offset:   16 Size:     4
//
// }
//
//
// Resource Bindings:
//
// Name                                 Type  Format         Dim      ID      HLSL Bind  Count
// ------------------------------ ---------- ------- ----------- ------- -------------- ------
// xe_edram_load_store_dest              UAV    byte         r/w      U0             u0      1 
// XeEDRAMLoadStoreConstants         cbuffer      NA          NA     CB0            cb0      1 
//
//
//
// Input signature:
//
// Name                 Index   Mask Register SysValue  Format   Used
// -------------------- ----- ------ -------- -------- ------- ------
// no Input
//
// Output signature:
//
// Name                 Index   Mask Register SysValue  Format   Used
// -------------------- ----- ------ -------- -------- ------- ------
// no Output
cs_5_1
dcl_globalFlags refactoringAllowed
dcl_constantbuffer CB0[0:0][2], immediateIndexed, space=0
dcl_uav_raw U0[0:0], space=0
dcl_input vThreadGroupID.xy
dcl_input vThreadIDInGroup.xy
dcl_input vThreadID.xy
dcl_temps 2
dcl_thread_group 40, 16, 1
and r0.xy, CB0[0][0].xyxx, l(0x0000ffff, 0x0000ffff, 0, 0)
ushr r0.zw, CB0[0][0].xxxy, l(0, 0, 16, 16)
ishl r1.x, vThreadID.x, l(1)
mov r1.y, vThreadID.y
ult r0.xz, r1.xxyx, r0.xxzx
or r0.x, r0.z, r0.x
uge r0.zw, r1.xxxy, r0.yyyw
or r0.z, r0.w, r0.z
or r0.x, r0.z, r0.x
if_nz r0.x
  ret 
endif 
and r0.x, CB0[0][1].x, l(2047)
ushr r0.z, CB0[0][1].x, l(11)
imad r0.x, vThreadGroupID.y, r0.z, r0.x
iadd r0.x, r0.x, vThreadGroupID.x
imul null, r0.z, vThreadIDInGroup.y, l(320)
imad r0.x, r0.x, l(5120), r0.z
ishl r0.z, vThreadIDInGroup.x, l(3)
iadd r0.x, r0.z, r0.x
store_raw U0[0].x, r0.x, CB0[0][0].z
imad r0.z, vThreadID.x, l(2), l(1)
ult r0.y, r0.z, r0.y
if_nz r0.y
  iadd r0.y, r0.x, l(4)
  store_raw U0[0].x, r0.y, CB0[0][0].z
endif 
ret 
// Approximately 28 instruction slots used
