//
// Generated by Microsoft (R) HLSL Shader Compiler 10.1
//
//
// Buffer Definitions: 
//
// cbuffer XeTextureCopyConstants
// {
//
//   uint xe_texture_copy_guest_base;   // Offset:    0 Size:     4
//   uint xe_texture_copy_guest_pitch;  // Offset:    4 Size:     4
//   uint xe_texture_copy_host_base;    // Offset:    8 Size:     4
//   uint xe_texture_copy_host_pitch;   // Offset:   12 Size:     4
//   uint3 xe_texture_copy_size_texels; // Offset:   16 Size:    12 [unused]
//   bool xe_texture_copy_is_3d;        // Offset:   28 Size:     4
//   uint3 xe_texture_copy_size_blocks; // Offset:   32 Size:    12
//   uint xe_texture_copy_endianness;   // Offset:   44 Size:     4 [unused]
//   uint3 xe_texture_copy_guest_mip_offset;// Offset:   48 Size:    12
//
// }
//
//
// Resource Bindings:
//
// Name                                 Type  Format         Dim      ID      HLSL Bind  Count
// ------------------------------ ---------- ------- ----------- ------- -------------- ------
// xe_texture_copy_source            texture    byte         r/o      T0             t0      1 
// xe_texture_copy_dest                  UAV    byte         r/w      U0             u0      1 
// XeTextureCopyConstants            cbuffer      NA          NA     CB0            cb0      1 
//
//
//
// Input signature:
//
// Name                 Index   Mask Register SysValue  Format   Used
// -------------------- ----- ------ -------- -------- ------- ------
// no Input
//
// Output signature:
//
// Name                 Index   Mask Register SysValue  Format   Used
// -------------------- ----- ------ -------- -------- ------- ------
// no Output
cs_5_1
dcl_globalFlags refactoringAllowed
dcl_constantbuffer CB0[0:0][4], immediateIndexed, space=0
dcl_resource_raw T0[0:0], space=0
dcl_uav_raw U0[0:0], space=0
dcl_input vThreadID.xyz
dcl_temps 9
dcl_thread_group 8, 32, 1
ishl r0.x, vThreadID.x, l(2)
mov r0.yz, vThreadID.yyzy
uge r1.xyz, r0.xyzx, CB0[0][2].xyzx
or r0.w, r1.y, r1.x
or r0.w, r1.z, r0.w
if_nz r0.w
  ret 
endif 
iadd r0.yzw, r0.xxyz, CB0[0][3].xxyz
ieq r1.x, CB0[0][0].y, l(-1)
if_nz r1.x
  if_nz CB0[0][1].w
    iadd r1.xyzw, r0.yyyy, l(0, 1, 2, 3)
    iadd r2.xy, CB0[0][2].yxyy, l(31, 31, 0, 0)
    ushr r3.xyz, r0.wzzw, l(2, 4, 3, 0)
    ushr r2.xy, r2.xyxx, l(4, 5, 0, 0)
    and r2.x, r2.x, l(0x0ffffffe)
    imad r2.x, r3.x, r2.x, r3.y
    iadd r2.z, r3.z, r3.x
    bfi r2.w, l(1), l(1), r2.z, l(0)
    ushr r3.xyzw, r1.xyzw, l(3, 3, 3, 3)
    iadd r3.xyzw, r2.wwww, r3.xyzw
    bfi r3.xyzw, l(2, 2, 2, 2), l(1, 1, 1, 1), r3.xyzw, l(0, 0, 0, 0)
    bfi r3.xyzw, l(1, 1, 1, 1), l(0, 0, 0, 0), r2.zzzz, r3.xyzw
    ishl r2.z, r0.z, l(2)
    and r2.z, r2.z, l(24)
    bfi r4.xyzw, l(3, 3, 3, 3), l(0, 0, 0, 0), r1.xyzw, r2.zzzz
    ushr r1.xyzw, r1.xyzw, l(5, 5, 5, 5)
    imad r1.xyzw, r2.xxxx, r2.yyyy, r1.xyzw
    and r2.xyzw, r4.xyzw, l(16, 16, 16, 16)
    bfi r5.xyzw, l(22, 22, 22, 22), l(8, 8, 8, 8), r1.xyzw, l(0, 0, 0, 0)
    imad r5.xyzw, r2.xyzw, l(2, 2, 2, 2), r5.xyzw
    bfi r5.xyzw, l(4, 4, 4, 4), l(0, 0, 0, 0), r4.xyzw, r5.xyzw
    bfi r5.xyzw, l(2, 2, 2, 2), l(6, 6, 6, 6), r0.wwww, r5.xyzw
    bfi r6.xyzw, l(1, 1, 1, 1), l(4, 4, 4, 4), r0.zzzz, r5.xyzw
    ubfe r5.xyzw, l(3, 3, 3, 3), l(6, 6, 6, 6), r5.xyzw
    and r7.xyzw, r3.xyzw, l(6, 6, 6, 6)
    bfi r3.xyzw, l(1, 1, 1, 1), l(8, 8, 8, 8), r3.xyzw, l(0, 0, 0, 0)
    imad r3.xyzw, r5.xyzw, l(32, 32, 32, 32), r3.xyzw
    imad r3.xyzw, r7.xyzw, l(4, 4, 4, 4), r3.xyzw
    bfi r1.xyzw, l(22, 22, 22, 22), l(11, 11, 11, 11), r1.xyzw, l(0, 0, 0, 0)
    imad r1.xyzw, r2.xyzw, l(16, 16, 16, 16), r1.xyzw
    bfi r1.xyzw, l(4, 4, 4, 4), l(3, 3, 3, 3), r4.xyzw, r1.xyzw
    bfi r1.xyzw, l(2, 2, 2, 2), l(9, 9, 9, 9), r0.wwww, r1.xyzw
    bfi r1.xyzw, l(1, 1, 1, 1), l(7, 7, 7, 7), r0.zzzz, r1.xyzw
    bfi r1.xyzw, l(9, 9, 9, 9), l(3, 3, 3, 3), r3.xyzw, r1.xyzw
    bfi r1.xyzw, l(6, 6, 6, 6), l(0, 0, 0, 0), r6.xyzw, r1.xyzw
  else 
    iadd r2.xyzw, r0.yyyy, l(0, 1, 2, 3)
    ushr r3.xyzw, r2.xyzw, l(5, 5, 5, 5)
    ushr r4.xy, r0.zzzz, l(5, 2, 0, 0)
    iadd r4.z, CB0[0][2].x, l(31)
    ushr r4.z, r4.z, l(5)
    imad r3.xyzw, r4.xxxx, r4.zzzz, r3.xyzw
    ishl r4.xz, r0.zzzz, l(2, 0, 7, 0)
    and r4.xz, r4.xxzx, l(56, 0, 2048, 0)
    bfi r5.xyzw, l(3, 3, 3, 3), l(0, 0, 0, 0), r2.xyzw, r4.xxxx
    ishl r4.x, r4.x, l(1)
    bfi r6.xyzw, l(3, 3, 3, 3), l(1, 1, 1, 1), r2.xyzw, r4.xxxx
    and r6.xyzw, r6.xyzw, l(96, 96, 96, 96)
    bfi r7.xyzw, l(25, 25, 25, 25), l(7, 7, 7, 7), r3.xyzw, r6.xyzw
    bfi r7.xyzw, l(4, 4, 4, 4), l(0, 0, 0, 0), r5.xyzw, r7.xyzw
    bfi r7.xyzw, l(1, 1, 1, 1), l(4, 4, 4, 4), r0.zzzz, r7.xyzw
    ishl r8.xyzw, r6.xyzw, l(3, 3, 3, 3)
    bfi r8.xyzw, l(25, 25, 25, 25), l(10, 10, 10, 10), r3.xyzw, r8.xyzw
    bfi r8.xyzw, l(4, 4, 4, 4), l(3, 3, 3, 3), r5.xyzw, r8.xyzw
    bfi r8.xyzw, l(1, 1, 1, 1), l(7, 7, 7, 7), r0.zzzz, r8.xyzw
    bfi r8.xyzw, l(12, 12, 12, 12), l(0, 0, 0, 0), r4.zzzz, r8.xyzw
    ishl r6.xyzw, r6.xyzw, l(2, 2, 2, 2)
    bfi r3.xyzw, l(25, 25, 25, 25), l(9, 9, 9, 9), r3.xyzw, r6.xyzw
    bfi r3.xyzw, l(4, 4, 4, 4), l(2, 2, 2, 2), r5.xyzw, r3.xyzw
    bfi r3.xyzw, l(1, 1, 1, 1), l(6, 6, 6, 6), r0.zzzz, r3.xyzw
    and r3.xyzw, r3.xyzw, l(1792, 1792, 1792, 1792)
    iadd r3.xyzw, r8.xyzw, r3.xyzw
    ushr r2.xyzw, r2.xyzw, l(3, 3, 3, 3)
    and r4.x, r4.y, l(2)
    iadd r2.xyzw, r2.xyzw, r4.xxxx
    bfi r2.xyzw, l(2, 2, 2, 2), l(6, 6, 6, 6), r2.xyzw, l(0, 0, 0, 0)
    iadd r2.xyzw, r3.xyzw, r2.xyzw
    bfi r1.xyzw, l(6, 6, 6, 6), l(0, 0, 0, 0), r7.xyzw, r2.xyzw
  endif 
else 
  iadd r2.x, CB0[0][2].y, l(31)
  and r2.x, r2.x, l(-32)
  imad r0.z, r0.w, r2.x, r0.z
  imad r0.y, r0.z, CB0[0][0].y, r0.y
  iadd r1.xyzw, r0.yyyy, l(0, 1, 2, 3)
endif 
iadd r1.xyzw, r1.xyzw, CB0[0][0].xxxx
and r2.xyzw, r1.xyzw, l(-4, -4, -4, -4)
ld_raw r3.x, r2.x, T0[0].xxxx
ld_raw r3.y, r2.y, T0[0].xxxx
ld_raw r3.z, r2.z, T0[0].xxxx
ld_raw r3.w, r2.w, T0[0].xxxx
bfi r1.xyzw, l(2, 2, 2, 2), l(3, 3, 3, 3), r1.xyzw, l(0, 0, 0, 0)
ushr r1.xyzw, r3.xyzw, r1.xyzw
and r2.x, r1.x, l(255)
bfi r2.yzw, l(0, 8, 8, 8), l(0, 8, 16, 24), r1.yyzw, l(0, 0, 0, 0)
iadd r0.yz, r2.zzwz, r2.xxyx
iadd r0.y, r0.z, r0.y
imad r0.z, vThreadID.z, CB0[0][2].y, vThreadID.y
imad r0.x, r0.z, CB0[0][0].w, r0.x
iadd r0.x, r0.x, CB0[0][0].z
store_raw U0[0].x, r0.x, r0.y
ret 
// Approximately 105 instruction slots used
