//
// Generated by Microsoft (R) HLSL Shader Compiler 10.1
//
//
// Buffer Definitions: 
//
// cbuffer XeEDRAMLoadStoreConstants
// {
//
//   uint4 xe_edram_load_store_constants;// Offset:    0 Size:    16
//   uint xe_edram_base_pitch_tiles;    // Offset:   16 Size:     4
//
// }
//
//
// Resource Bindings:
//
// Name                                 Type  Format         Dim      ID      HLSL Bind  Count
// ------------------------------ ---------- ------- ----------- ------- -------------- ------
// xe_edram_load_store_source        texture    byte         r/o      T0             t0      1 
// xe_edram_load_store_dest              UAV    byte         r/w      U0             u0      1 
// XeEDRAMLoadStoreConstants         cbuffer      NA          NA     CB0            cb0      1 
//
//
//
// Input signature:
//
// Name                 Index   Mask Register SysValue  Format   Used
// -------------------- ----- ------ -------- -------- ------- ------
// no Input
//
// Output signature:
//
// Name                 Index   Mask Register SysValue  Format   Used
// -------------------- ----- ------ -------- -------- ------- ------
// no Output
cs_5_1
dcl_globalFlags refactoringAllowed
dcl_constantbuffer CB0[0:0][2], immediateIndexed, space=0
dcl_resource_raw T0[0:0], space=0
dcl_uav_raw U0[0:0], space=0
dcl_input vThreadGroupID.xy
dcl_input vThreadIDInGroup.xy
dcl_input vThreadID.xy
dcl_temps 8
dcl_thread_group 20, 16, 1
and r0.x, CB0[0][1].x, l(2047)
ushr r0.y, CB0[0][1].x, l(11)
imad r0.x, vThreadGroupID.y, r0.y, r0.x
iadd r0.x, r0.x, vThreadGroupID.x
imul null, r0.y, vThreadIDInGroup.y, l(320)
imad r0.x, r0.x, l(5120), r0.y
ishl r0.y, vThreadIDInGroup.x, l(4)
iadd r0.x, r0.y, r0.x
ld_raw r1.xyzw, r0.x, T0[0].xyzw
ushr r2.xyzw, r1.xyzw, l(8, 8, 8, 8)
iadd r0.x, r0.x, l(0x00a00000)
ld_raw r0.xyzw, r0.x, T0[0].xyzw
ubfe r3.xyzw, l(20, 20, 20, 20), l(8, 8, 8, 8), r1.xyzw
ushr r4.xyzw, r2.xyzw, l(20, 20, 20, 20)
movc r5.xyzw, r4.xyzw, l(0,0,0,0), l(1,1,1,1)
firstbit_hi r6.xyzw, r3.xyzw
iadd r6.xyzw, r6.xyzw, l(-11, -11, -11, -11)
movc r6.xyzw, r3.xyzw, r6.xyzw, l(21,21,21,21)
iadd r7.xyzw, -r6.xyzw, l(1, 1, 1, 1)
iadd r7.xyzw, -r4.xyzw, r7.xyzw
imad r4.xyzw, r7.xyzw, r5.xyzw, r4.xyzw
ishl r6.xyzw, r3.xyzw, r6.xyzw
and r6.xyzw, r6.xyzw, l(0x000fffff, 0x000fffff, 0x000fffff, 0x000fffff)
iadd r6.xyzw, -r3.xyzw, r6.xyzw
imad r3.xyzw, r6.xyzw, r5.xyzw, r3.xyzw
ishl r4.xyzw, r4.xyzw, l(23, 23, 23, 23)
iadd r4.xyzw, r4.xyzw, l(0x38000000, 0x38000000, 0x38000000, 0x38000000)
ishl r3.xyzw, r3.xyzw, l(3, 3, 3, 3)
or r3.xyzw, r3.xyzw, r4.xyzw
movc r4.xyzw, r2.xyzw, l(1,1,1,1), l(0,0,0,0)
imul null, r3.xyzw, r3.xyzw, r4.xyzw
iadd r4.xyzw, r0.xyzw, -r3.xyzw
uge r5.xyzw, l(0x7fffffff, 0x7fffffff, 0x7fffffff, 0x7fffffff), r0.xyzw
and r5.xyzw, r5.xyzw, l(1, 1, 1, 1)
imul null, r0.xyzw, r0.xyzw, r5.xyzw
umin r0.xyzw, r0.xyzw, l(0x3ffffff8, 0x3ffffff8, 0x3ffffff8, 0x3ffffff8)
iadd r5.xyzw, r0.xyzw, l(0xc8000000, 0xc8000000, 0xc8000000, 0xc8000000)
bfi r6.xyzw, l(23, 23, 23, 23), l(0, 0, 0, 0), r0.xyzw, l(0x00800000, 0x00800000, 0x00800000, 0x00800000)
ushr r7.xyzw, r0.xyzw, l(23, 23, 23, 23)
iadd r7.xyzw, -r7.xyzw, l(113, 113, 113, 113)
ushr r6.xyzw, r6.xyzw, r7.xyzw
iadd r6.xyzw, -r5.xyzw, r6.xyzw
ult r0.xyzw, r0.xyzw, l(0x38800000, 0x38800000, 0x38800000, 0x38800000)
and r0.xyzw, r0.xyzw, l(1, 1, 1, 1)
imad r0.xyzw, r6.xyzw, r0.xyzw, r5.xyzw
iadd r5.xyzw, r0.xyzw, l(3, 3, 3, 3)
ubfe r0.xyzw, l(1, 1, 1, 1), l(3, 3, 3, 3), r0.xyzw
iadd r0.xyzw, r0.xyzw, r5.xyzw
ubfe r0.xyzw, l(24, 24, 24, 24), l(3, 3, 3, 3), r0.xyzw
ieq r0.xyzw, r2.xyzw, r0.xyzw
and r0.xyzw, r0.xyzw, l(1, 1, 1, 1)
imad r0.xyzw, r4.xyzw, r0.xyzw, r3.xyzw
ishl r2.xy, vThreadID.xxxx, l(4, 2, 0, 0)
imad r2.xy, vThreadID.yyyy, CB0[0][0].ywyy, r2.xyxx
iadd r2.xy, r2.xyxx, CB0[0][0].xzxx
store_raw U0[0].xyzw, r2.x, r0.xyzw
and r0.x, r1.x, l(255)
bfi r0.yzw, l(0, 8, 8, 8), l(0, 8, 16, 24), r1.yyzw, l(0, 0, 0, 0)
iadd r0.xy, r0.zwzz, r0.xyxx
iadd r0.x, r0.y, r0.x
store_raw U0[0].x, r2.y, r0.x
ret 
// Approximately 62 instruction slots used
