//
// Generated by Microsoft (R) HLSL Shader Compiler 10.1
//
//
// Buffer Definitions: 
//
// cbuffer XeTextureLoadConstants
// {
//
//   uint xe_texture_load_guest_base;   // Offset:    0 Size:     4
//   uint xe_texture_load_guest_pitch;  // Offset:    4 Size:     4
//   uint2 xe_texture_load_guest_storage_width_height;// Offset:    8 Size:     8
//   uint3 xe_texture_load_size_blocks; // Offset:   16 Size:    12
//   uint xe_texture_load_is_3d_endian; // Offset:   28 Size:     4
//   uint xe_texture_load_host_base;    // Offset:   32 Size:     4
//   uint xe_texture_load_host_pitch;   // Offset:   36 Size:     4
//   uint xe_texture_load_height_texels;// Offset:   40 Size:     4 [unused]
//
// }
//
//
// Resource Bindings:
//
// Name                                 Type  Format         Dim      ID      HLSL Bind  Count
// ------------------------------ ---------- ------- ----------- ------- -------------- ------
// xe_texture_load_source            texture   uint4         buf      T0             t0      1 
// xe_texture_load_dest                  UAV   uint4         buf      U0             u0      1 
// XeTextureLoadConstants            cbuffer      NA          NA     CB0            cb0      1 
//
//
//
// Input signature:
//
// Name                 Index   Mask Register SysValue  Format   Used
// -------------------- ----- ------ -------- -------- ------- ------
// no Input
//
// Output signature:
//
// Name                 Index   Mask Register SysValue  Format   Used
// -------------------- ----- ------ -------- -------- ------- ------
// no Output
cs_5_1
dcl_globalFlags refactoringAllowed
dcl_constantbuffer CB0[0:0][3], immediateIndexed, space=0
dcl_resource_buffer (uint,uint,uint,uint) T0[0:0], space=0
dcl_uav_typed_buffer (uint,uint,uint,uint) U0[0:0], space=0
dcl_input vThreadID.xyz
dcl_temps 7
dcl_thread_group 4, 32, 1
ishl r0.x, vThreadID.x, l(3)
mov r0.yz, vThreadID.yyzy
uge r0.yzw, r0.xxyz, CB0[0][1].xxyz
or r0.y, r0.z, r0.y
or r0.y, r0.w, r0.y
if_nz r0.y
  ret 
endif 
ishl r0.x, r0.x, l(2)
imad r0.y, vThreadID.z, CB0[0][1].y, vThreadID.y
imad r0.y, r0.y, CB0[0][2].y, r0.x
iadd r0.y, r0.y, CB0[0][2].x
ieq r0.z, CB0[0][0].y, l(-1)
if_nz r0.z
  and r0.w, CB0[0][1].w, l(1)
  if_nz r0.w
    iadd r1.xy, CB0[0][0].wzww, l(31, 31, 0, 0)
    ishr r2.xyz, vThreadID.yzyy, l(4, 2, 3, 0)
    ushr r1.xy, r1.xyxx, l(4, 5, 0, 0)
    and r0.w, r1.x, l(0x0ffffffe)
    imad r0.w, r2.y, r0.w, r2.x
    ibfe r1.xz, l(27, 0, 29, 0), l(2, 0, 0, 0), vThreadID.xxxx
    imad r0.w, r0.w, r1.y, r1.x
    ishl r1.x, vThreadID.y, l(10)
    ishr r1.x, r1.x, l(6)
    and r1.x, r1.x, l(96)
    iadd r1.y, r2.y, r2.z
    bfi r1.w, l(1), l(1), r1.y, l(0)
    iadd r1.z, r1.w, r1.z
    bfi r1.z, l(2), l(1), r1.z, l(0)
    bfi r1.y, l(1), l(0), r1.y, r1.z
    bfi r1.zw, l(0, 0, 20, 20), l(0, 0, 10, 13), r0.wwww, l(0, 0, 0, 0)
    imad r1.xz, r1.xxxx, l(2, 0, 16, 0), r1.zzwz
    bfi r1.xz, l(2, 0, 2, 0), l(8, 0, 11, 0), vThreadID.zzzz, r1.xxzx
    bfi r0.w, l(1), l(4), vThreadID.y, l(0)
    ubfe r1.w, l(3), l(6), r1.x
    and r2.x, r1.y, l(6)
    bfi r1.y, l(1), l(8), r1.y, l(0)
    imad r1.y, r1.w, l(32), r1.y
    imad r1.y, r2.x, l(4), r1.y
    bfi r1.xz, l(6, 0, 6, 0), l(0, 0, 3, 0), r0.wwww, r1.xxzx
    bfi r0.w, l(9), l(3), r1.y, r1.z
    bfi r0.w, l(6), l(0), r1.x, r0.w
  else 
    ibfe r1.xy, l(27, 29, 0, 0), l(2, 0, 0, 0), vThreadID.xxxx
    ishr r1.zw, vThreadID.yyyy, l(0, 0, 5, 2)
    iadd r2.x, CB0[0][0].z, l(31)
    ushr r2.x, r2.x, l(5)
    imad r1.x, r1.z, r2.x, r1.x
    ishl r2.xy, vThreadID.yyyy, l(5, 7, 0, 0)
    and r2.xy, r2.xyxx, l(448, 2048, 0, 0)
    bfi r1.z, l(23), l(9), r1.x, r2.x
    bfi r2.z, l(1), l(4), vThreadID.y, l(0)
    iadd r1.z, r1.z, r2.z
    ishl r2.xw, r2.xxxx, l(3, 0, 0, 2)
    bfi r2.xw, l(23, 0, 0, 23), l(12, 0, 0, 11), r1.xxxx, r2.xxxw
    imad r2.xz, r2.zzzz, l(8, 0, 4, 0), r2.xxwx
    bfi r1.x, l(12), l(0), r2.y, r2.x
    and r2.x, r2.z, l(1792)
    iadd r1.x, r1.x, r2.x
    and r1.w, r1.w, l(2)
    iadd r1.y, r1.y, r1.w
    bfi r1.y, l(2), l(6), r1.y, l(0)
    iadd r1.x, r1.x, r1.y
    bfi r0.w, l(6), l(0), r1.z, r1.x
  endif 
else 
  iadd r1.x, CB0[0][1].y, l(31)
  and r1.x, r1.x, l(-32)
  imad r1.x, vThreadID.z, r1.x, vThreadID.y
  imad r0.w, r1.x, CB0[0][0].y, r0.x
endif 
iadd r0.x, r0.w, CB0[0][0].x
ushr r0.xy, r0.xyxx, l(4, 4, 0, 0)
ushr r0.w, CB0[0][1].w, l(1)
ld r1.xyzw, r0.xxxx, T0[0].xyzw
ieq r2.xyz, r0.wwww, l(1, 2, 3, 0)
or r2.xy, r2.yzyy, r2.xyxx
if_nz r2.x
  ishl r3.xyzw, r1.xyzw, l(8, 8, 8, 8)
  and r3.xyzw, r3.xyzw, l(0xff00ff00, 0xff00ff00, 0xff00ff00, 0xff00ff00)
  ushr r4.xyzw, r1.xyzw, l(8, 8, 8, 8)
  and r4.xyzw, r4.xyzw, l(0x00ff00ff, 0x00ff00ff, 0x00ff00ff, 0x00ff00ff)
  iadd r1.xyzw, r3.xyzw, r4.xyzw
endif 
if_nz r2.y
  ushr r3.xyzw, r1.xyzw, l(16, 16, 16, 16)
  bfi r1.xyzw, l(16, 16, 16, 16), l(16, 16, 16, 16), r1.xyzw, r3.xyzw
endif 
ushr r3.xyzw, r1.xyzw, l(8, 8, 8, 8)
ubfe r1.xyzw, l(20, 20, 20, 20), l(8, 8, 8, 8), r1.xyzw
ushr r4.xyzw, r3.xyzw, l(20, 20, 20, 20)
firstbit_hi r5.xyzw, r1.xyzw
iadd r5.xyzw, r5.xyzw, l(-11, -11, -11, -11)
movc r5.xyzw, r1.xyzw, r5.xyzw, l(21,21,21,21)
iadd r6.xyzw, -r5.xyzw, l(1, 1, 1, 1)
movc r6.xyzw, r4.xyzw, r4.xyzw, r6.xyzw
ishl r5.xyzw, r1.xyzw, r5.xyzw
and r5.xyzw, r5.xyzw, l(0x000fffff, 0x000fffff, 0x000fffff, 0x000fffff)
movc r1.xyzw, r4.xyzw, r1.xyzw, r5.xyzw
ishl r4.xyzw, r6.xyzw, l(23, 23, 23, 23)
iadd r4.xyzw, r4.xyzw, l(0x38000000, 0x38000000, 0x38000000, 0x38000000)
ishl r1.xyzw, r1.xyzw, l(3, 3, 3, 3)
iadd r1.xyzw, r4.xyzw, r1.xyzw
movc r1.xyzw, r3.xyzw, r1.xyzw, l(0,0,0,0)
store_uav_typed U0[0].xyzw, r0.yyyy, r1.xyzw
iadd r0.w, r0.y, l(1)
movc r0.z, r0.z, l(2), l(1)
iadd r0.x, r0.z, r0.x
ld r1.xyzw, r0.xxxx, T0[0].xyzw
if_nz r2.x
  ishl r3.xyzw, r1.xyzw, l(8, 8, 8, 8)
  and r3.xyzw, r3.xyzw, l(0xff00ff00, 0xff00ff00, 0xff00ff00, 0xff00ff00)
  ushr r4.xyzw, r1.xyzw, l(8, 8, 8, 8)
  and r4.xyzw, r4.xyzw, l(0x00ff00ff, 0x00ff00ff, 0x00ff00ff, 0x00ff00ff)
  iadd r1.xyzw, r3.xyzw, r4.xyzw
endif 
if_nz r2.y
  ushr r2.xyzw, r1.xyzw, l(16, 16, 16, 16)
  bfi r1.xyzw, l(16, 16, 16, 16), l(16, 16, 16, 16), r1.xyzw, r2.xyzw
endif 
ushr r2.xyzw, r1.xyzw, l(8, 8, 8, 8)
ubfe r1.xyzw, l(20, 20, 20, 20), l(8, 8, 8, 8), r1.xyzw
ushr r3.xyzw, r2.xyzw, l(20, 20, 20, 20)
firstbit_hi r4.xyzw, r1.xyzw
iadd r4.xyzw, r4.xyzw, l(-11, -11, -11, -11)
movc r4.xyzw, r1.xyzw, r4.xyzw, l(21,21,21,21)
iadd r5.xyzw, -r4.xyzw, l(1, 1, 1, 1)
movc r5.xyzw, r3.xyzw, r3.xyzw, r5.xyzw
ishl r4.xyzw, r1.xyzw, r4.xyzw
and r4.xyzw, r4.xyzw, l(0x000fffff, 0x000fffff, 0x000fffff, 0x000fffff)
movc r1.xyzw, r3.xyzw, r1.xyzw, r4.xyzw
ishl r3.xyzw, r5.xyzw, l(23, 23, 23, 23)
iadd r3.xyzw, r3.xyzw, l(0x38000000, 0x38000000, 0x38000000, 0x38000000)
ishl r1.xyzw, r1.xyzw, l(3, 3, 3, 3)
iadd r1.xyzw, r3.xyzw, r1.xyzw
movc r1.xyzw, r2.xyzw, r1.xyzw, l(0,0,0,0)
store_uav_typed U0[0].xyzw, r0.wwww, r1.xyzw
ret 
// Approximately 139 instruction slots used
