//
// Generated by Microsoft (R) HLSL Shader Compiler 10.1
//
//
// Buffer Definitions: 
//
// cbuffer XeEdramLoadStoreConstants
// {
//
//   uint xe_edram_rt_color_depth_offset;// Offset:    0 Size:     4
//   uint xe_edram_rt_color_depth_pitch;// Offset:    4 Size:     4
//   uint xe_edram_rt_stencil_offset;   // Offset:    8 Size:     4 [unused]
//   uint xe_edram_rt_stencil_pitch;    // Offset:   12 Size:     4 [unused]
//   uint xe_edram_base_samples_2x_depth_pitch;// Offset:   16 Size:     4
//
// }
//
//
// Resource Bindings:
//
// Name                                 Type  Format         Dim      ID      HLSL Bind  Count
// ------------------------------ ---------- ------- ----------- ------- -------------- ------
// xe_edram_load_store_source        texture    byte         r/o      T0             t0      1 
// xe_edram_load_store_dest              UAV    byte         r/w      U0             u0      1 
// XeEdramLoadStoreConstants         cbuffer      NA          NA     CB0            cb0      1 
//
//
//
// Input signature:
//
// Name                 Index   Mask Register SysValue  Format   Used
// -------------------- ----- ------ -------- -------- ------- ------
// no Input
//
// Output signature:
//
// Name                 Index   Mask Register SysValue  Format   Used
// -------------------- ----- ------ -------- -------- ------- ------
// no Output
cs_5_1
dcl_globalFlags refactoringAllowed
dcl_constantbuffer CB0[0:0][2], immediateIndexed, space=0
dcl_resource_raw T0[0:0], space=0
dcl_uav_raw U0[0:0], space=0
dcl_input vThreadGroupID.xy
dcl_input vThreadIDInGroup.xy
dcl_input vThreadID.xy
dcl_temps 7
dcl_thread_group 40, 16, 1
ishl r0.x, vThreadIDInGroup.x, l(1)
and r0.yz, CB0[0][1].xxxx, l(0, 0x00008000, 2047, 0)
if_nz r0.y
  ult r0.y, vThreadIDInGroup.x, l(20)
  uge r0.w, vThreadIDInGroup.x, l(20)
  and r0.yw, r0.yyyw, l(0, 40, 0, -40)
  iadd r0.y, r0.w, r0.y
  iadd r0.x, r0.y, r0.x
endif 
ushr r0.y, CB0[0][1].x, l(16)
imad r0.y, vThreadGroupID.y, r0.y, r0.z
iadd r0.y, r0.y, vThreadGroupID.x
imul null, r0.z, vThreadIDInGroup.y, l(320)
imad r0.y, r0.y, l(5120), r0.z
ishl r0.x, r0.x, l(2)
iadd r0.x, r0.x, r0.y
ubfe r0.y, l(1), l(13), CB0[0][1].x
ishl r0.y, r0.y, l(1)
ishl r0.x, r0.x, r0.y
ld_raw r0.xy, r0.x, T0[0].yxxx
ushr r1.xyzw, r0.yyyx, l(10, 20, 30, 30)
mov r0.zw, r1.xxxy
and r2.xyz, r0.yzwy, l(1023, 1023, 1023, 0)
and r3.xyz, r0.yzwy, l(127, 127, 127, 0)
ubfe r4.xyz, l(3, 3, 3, 0), l(7, 7, 7, 0), r0.yzwy
firstbit_hi r5.xyz, r3.xyzx
iadd r5.xyz, r5.xyzx, l(-24, -24, -24, 0)
movc r5.xyz, r3.xyzx, r5.xyzx, l(8,8,8,0)
iadd r6.xyz, -r5.xyzx, l(1, 1, 1, 0)
movc r6.xyz, r4.xyzx, r4.xyzx, r6.xyzx
bfi r5.xyz, l(7, 7, 7, 0), r5.xyzx, r0.yzwy, l(0, 0, 0, 0)
and r5.xyz, r5.xyzx, l(127, 127, 127, 0)
movc r3.xyz, r4.xyzx, r3.xyzx, r5.xyzx
ishl r4.xyz, r6.xyzx, l(23, 23, 23, 0)
iadd r4.xyz, r4.xyzx, l(0x3e000000, 0x3e000000, 0x3e000000, 0)
ishl r3.xyz, r3.xyzx, l(16, 16, 16, 0)
iadd r3.xyz, r4.xyzx, r3.xyzx
movc r2.xyz, r2.xyzx, r3.xyzx, l(0,0,0,0)
utof r1.xy, r1.zwzz
mul r1.xy, r1.xyxx, l(0.333333, 0.333333, 0.000000, 0.000000)
f32tof16 r2.xyz, r2.xyzx
f32tof16 r2.w, r1.x
ushr r0.yz, r0.xxxx, l(0, 10, 20, 0)
and r1.xzw, r0.xxyz, l(1023, 0, 1023, 1023)
and r3.xyz, r0.xyzx, l(127, 127, 127, 0)
ubfe r4.xyz, l(3, 3, 3, 0), l(7, 7, 7, 0), r0.xyzx
firstbit_hi r5.xyz, r3.xyzx
iadd r5.xyz, r5.xyzx, l(-24, -24, -24, 0)
movc r5.xyz, r3.xyzx, r5.xyzx, l(8,8,8,0)
iadd r6.xyz, -r5.xyzx, l(1, 1, 1, 0)
movc r6.xyz, r4.xyzx, r4.xyzx, r6.xyzx
bfi r0.xyz, l(7, 7, 7, 0), r5.xyzx, r0.xyzx, l(0, 0, 0, 0)
and r0.xyz, r0.xyzx, l(127, 127, 127, 0)
movc r0.xyz, r4.xyzx, r3.xyzx, r0.xyzx
ishl r3.xyz, r6.xyzx, l(23, 23, 23, 0)
iadd r3.xyz, r3.xyzx, l(0x3e000000, 0x3e000000, 0x3e000000, 0)
ishl r0.xyz, r0.xyzx, l(16, 16, 16, 0)
iadd r0.xyz, r3.xyzx, r0.xyzx
movc r0.xyz, r1.xzwx, r0.xyzx, l(0,0,0,0)
f32tof16 r0.xzw, r0.yyxz
f32tof16 r0.y, r1.y
mov r1.xy, r2.ywyy
mov r1.zw, r0.xxxy
mov r0.xy, r2.xzxx
imad r0.xyzw, r1.xyzw, l(0x00010000, 0x00010000, 0x00010000, 0x00010000), r0.xyzw
ishl r1.x, vThreadID.x, l(4)
imad r1.x, vThreadID.y, CB0[0][0].y, r1.x
iadd r1.x, r1.x, CB0[0][0].x
store_raw U0[0].xyzw, r1.x, r0.xyzw
ret 
// Approximately 70 instruction slots used
