//
// Generated by Microsoft (R) HLSL Shader Compiler 10.1
//
//
// Buffer Definitions: 
//
// cbuffer XeTextureLoadConstants
// {
//
//   uint xe_texture_load_guest_base;   // Offset:    0 Size:     4
//   uint xe_texture_load_guest_pitch;  // Offset:    4 Size:     4
//   uint2 xe_texture_load_guest_storage_width_height;// Offset:    8 Size:     8
//   uint3 xe_texture_load_size_blocks; // Offset:   16 Size:    12
//   uint xe_texture_load_is_3d_endian; // Offset:   28 Size:     4
//   uint xe_texture_load_host_base;    // Offset:   32 Size:     4
//   uint xe_texture_load_host_pitch;   // Offset:   36 Size:     4
//   uint xe_texture_load_height_texels;// Offset:   40 Size:     4
//
// }
//
//
// Resource Bindings:
//
// Name                                 Type  Format         Dim      ID      HLSL Bind  Count
// ------------------------------ ---------- ------- ----------- ------- -------------- ------
// xe_texture_load_source            texture   uint4         buf      T0             t0      1 
// xe_texture_load_dest                  UAV   uint4         buf      U0             u0      1 
// XeTextureLoadConstants            cbuffer      NA          NA     CB0            cb0      1 
//
//
//
// Input signature:
//
// Name                 Index   Mask Register SysValue  Format   Used
// -------------------- ----- ------ -------- -------- ------- ------
// no Input
//
// Output signature:
//
// Name                 Index   Mask Register SysValue  Format   Used
// -------------------- ----- ------ -------- -------- ------- ------
// no Output
cs_5_1
dcl_globalFlags refactoringAllowed
dcl_constantbuffer CB0[0:0][3], immediateIndexed, space=0
dcl_resource_buffer (uint,uint,uint,uint) T0[0:0], space=0
dcl_uav_typed_buffer (uint,uint,uint,uint) U0[0:0], space=0
dcl_input vThreadID.xyz
dcl_temps 8
dcl_thread_group 16, 32, 1
ishl r0.x, vThreadID.x, l(1)
mov r0.yz, vThreadID.yyzy
uge r1.xyz, r0.xyzx, CB0[0][1].xyzx
or r0.z, r1.y, r1.x
or r0.z, r1.z, r0.z
if_nz r0.z
  ret 
endif 
ishl r0.yz, r0.xxyx, l(0, 2, 2, 0)
ishl r0.y, r0.y, l(2)
imad r0.z, vThreadID.z, CB0[0][2].z, r0.z
imad r0.y, r0.z, CB0[0][2].y, r0.y
iadd r0.y, r0.y, CB0[0][2].x
ushr r0.z, CB0[0][2].y, l(4)
ieq r0.w, CB0[0][0].y, l(-1)
if_nz r0.w
  and r1.x, CB0[0][1].w, l(1)
  if_nz r1.x
    iadd r1.xy, CB0[0][0].wzww, l(31, 31, 0, 0)
    ishr r2.xyz, vThreadID.yzyy, l(4, 2, 3, 0)
    ushr r1.xy, r1.xyxx, l(4, 5, 0, 0)
    and r1.x, r1.x, l(0x0ffffffe)
    imad r1.x, r2.y, r1.x, r2.x
    ibfe r1.zw, l(0, 0, 27, 29), l(0, 0, 4, 2), vThreadID.xxxx
    imad r1.x, r1.x, r1.y, r1.z
    ishl r1.y, vThreadID.y, l(12)
    and r1.y, r1.y, l(0x00006000)
    bfi r1.y, l(3), l(10), r0.x, r1.y
    ishr r1.y, r1.y, l(6)
    iadd r1.z, r2.y, r2.z
    bfi r2.x, l(1), l(1), r1.z, l(0)
    iadd r1.w, r1.w, r2.x
    bfi r1.w, l(2), l(1), r1.w, l(0)
    bfi r1.z, l(1), l(0), r1.z, r1.w
    bfi r1.xw, l(18, 0, 0, 18), l(12, 0, 0, 15), r1.xxxx, l(0, 0, 0, 0)
    imad r1.xy, r1.yyyy, l(2, 16, 0, 0), r1.xwxx
    bfi r1.xy, l(2, 2, 0, 0), l(10, 13, 0, 0), vThreadID.zzzz, r1.xyxx
    bfi r1.w, l(1), l(4), vThreadID.y, l(0)
    ubfe r2.x, l(3), l(6), r1.x
    and r2.y, r1.z, l(6)
    bfi r1.z, l(1), l(8), r1.z, l(0)
    imad r1.z, r2.x, l(32), r1.z
    imad r1.z, r2.y, l(4), r1.z
    bfi r1.xy, l(6, 6, 0, 0), l(0, 3, 0, 0), r1.wwww, r1.xyxx
    bfi r1.y, l(9), l(3), r1.z, r1.y
    bfi r1.x, l(6), l(0), r1.x, r1.y
  else 
    ibfe r1.yz, l(0, 27, 29, 0), l(0, 4, 2, 0), vThreadID.xxxx
    ishr r2.xy, vThreadID.yyyy, l(5, 2, 0, 0)
    iadd r1.w, CB0[0][0].z, l(31)
    ushr r1.w, r1.w, l(5)
    imad r1.y, r2.x, r1.w, r1.y
    ishl r1.w, vThreadID.y, l(7)
    and r2.xz, r1.wwww, l(1792, 0, 2048, 0)
    bfi r1.w, l(3), l(5), r0.x, r2.x
    bfi r1.w, l(21), l(11), r1.y, r1.w
    bfi r2.w, l(1), l(4), vThreadID.y, l(0)
    iadd r1.w, r1.w, r2.w
    ishl r3.xy, r2.xxxx, l(3, 2, 0, 0)
    bfi r3.xy, l(3, 3, 0, 0), l(8, 7, 0, 0), r0.xxxx, r3.xyxx
    bfi r3.xy, l(21, 21, 0, 0), l(14, 13, 0, 0), r1.yyyy, r3.xyxx
    imad r2.xw, r2.wwww, l(8, 0, 0, 4), r3.xxxy
    bfi r1.y, l(12), l(0), r2.z, r2.x
    and r2.x, r2.w, l(1792)
    iadd r1.y, r1.y, r2.x
    and r2.x, r2.y, l(2)
    iadd r1.z, r1.z, r2.x
    bfi r1.z, l(2), l(6), r1.z, l(0)
    iadd r1.y, r1.y, r1.z
    bfi r1.x, l(6), l(0), r1.w, r1.y
  endif 
else 
  ishl r0.x, r0.x, l(4)
  iadd r1.y, CB0[0][1].y, l(31)
  and r1.y, r1.y, l(-32)
  imad r1.y, vThreadID.z, r1.y, vThreadID.y
  imad r1.x, r1.y, CB0[0][0].y, r0.x
endif 
iadd r0.x, r1.x, CB0[0][0].x
ushr r0.xy, r0.xyxx, l(4, 4, 0, 0)
ushr r1.x, CB0[0][1].w, l(1)
ld r2.xyzw, r0.xxxx, T0[0].yxzw
ieq r1.xyz, r1.xxxx, l(1, 2, 3, 0)
or r1.xy, r1.yzyy, r1.xyxx
if_nz r1.x
  ishl r3.xyzw, r2.yxzw, l(8, 8, 8, 8)
  and r3.xyzw, r3.xyzw, l(0xff00ff00, 0xff00ff00, 0xff00ff00, 0xff00ff00)
  ushr r4.xyzw, r2.yxzw, l(8, 8, 8, 8)
  and r4.xyzw, r4.xyzw, l(0x00ff00ff, 0x00ff00ff, 0x00ff00ff, 0x00ff00ff)
  iadd r2.xyzw, r3.yxzw, r4.yxzw
endif 
if_nz r1.y
  ushr r3.xyzw, r2.yxzw, l(16, 16, 16, 16)
  bfi r2.xyzw, l(16, 16, 16, 16), l(16, 16, 16, 16), r2.xyzw, r3.yxzw
  mov r3.x, r2.y
else 
  mov r3.x, r2.y
endif 
ishl r4.xyz, r2.zzzz, l(3, 7, 12, 0)
ushr r5.xyz, r2.zzzz, l(13, 4, 9, 0)
mov r4.w, r5.x
and r1.zw, r4.xxxw, l(0, 0, 248, 248)
mov r5.xw, r4.zzzy
and r4.xy, r5.wzww, l(0x0003f000, 0x0003f000, 0, 0)
iadd r1.zw, r1.zzzw, r4.xxxy
and r4.xy, r5.xyxx, l(0x0f800000, 0x0f800000, 0, 0)
iadd r1.zw, r1.zzzw, r4.xxxy
ushr r4.xy, r1.zwzz, l(5, 5, 0, 0)
and r4.xy, r4.xyxx, l(0x00700007, 0x00700007, 0, 0)
iadd r1.zw, r1.zzzw, r4.xxxy
ushr r4.xy, r1.zwzz, l(6, 6, 0, 0)
and r4.xy, r4.xyxx, l(3072, 3072, 0, 0)
iadd r1.zw, r1.zzzw, r4.xxxy
ishl r4.x, r2.w, l(1)
ushr r4.y, r2.w, l(1)
and r4.xy, r4.xyxx, l(0xaaaaaaaa, 0x55555555, 0, 0)
iadd r4.x, r4.y, r4.x
ushr r4.y, r4.x, l(1)
and r4.y, r4.y, l(0x55555555)
xor r4.x, r4.y, r4.x
not r5.x, r4.x
ushr r5.yzw, r5.xxxx, l(0, 2, 4, 6)
and r5.xyzw, r5.xyzw, l(3, 3, 3, 3)
ushr r4.yzw, r4.xxxx, l(0, 2, 4, 6)
and r6.xyzw, r4.xyzw, l(3, 3, 3, 3)
imul null, r6.xyzw, r1.wwww, r6.xyzw
imad r5.xyzw, r5.xyzw, r1.zzzz, r6.xyzw
and r6.xyzw, r5.xyzw, l(1023, 1023, 1023, 1023)
udiv r6.xyzw, null, r6.xyzw, l(3, 3, 3, 3)
ishl r6.xyzw, r6.xyzw, l(16, 16, 16, 16)
ubfe r7.xyzw, l(10, 10, 10, 10), l(10, 10, 10, 10), r5.xyzw
udiv r7.xyzw, null, r7.xyzw, l(3, 3, 3, 3)
bfi r6.xyzw, l(8, 8, 8, 8), l(8, 8, 8, 8), r7.xyzw, r6.xyzw
ushr r5.xyzw, r5.xyzw, l(20, 20, 20, 20)
udiv r5.xyzw, null, r5.xyzw, l(3, 3, 3, 3)
or r5.xyzw, r5.xyzw, r6.xyzw
ushr r3.yzw, r3.xxxx, l(0, 4, 8, 12)
and r6.xyzw, r3.xyzw, l(15, 15, 15, 15)
imad r5.xyzw, r6.xyzw, l(0x11000000, 0x11000000, 0x11000000, 0x11000000), r5.xyzw
store_uav_typed U0[0].xyzw, r0.yyyy, r5.xyzw
imad r3.y, vThreadID.y, l(4), l(1)
ilt r3.y, r3.y, CB0[0][2].z
if_nz r3.y
  iadd r3.z, r0.z, r0.y
  ushr r5.x, r4.x, l(8)
  not r6.x, r5.x
  ushr r6.yzw, r6.xxxx, l(0, 2, 4, 6)
  and r6.xyzw, r6.xyzw, l(3, 3, 3, 3)
  ushr r5.yzw, r5.xxxx, l(0, 2, 4, 6)
  and r5.xyzw, r5.xyzw, l(3, 3, 3, 3)
  imul null, r5.xyzw, r1.wwww, r5.xyzw
  imad r5.xyzw, r6.xyzw, r1.zzzz, r5.xyzw
  and r6.xyzw, r5.xyzw, l(1023, 1023, 1023, 1023)
  udiv r6.xyzw, null, r6.xyzw, l(3, 3, 3, 3)
  ishl r6.xyzw, r6.xyzw, l(16, 16, 16, 16)
  ubfe r7.xyzw, l(10, 10, 10, 10), l(10, 10, 10, 10), r5.xyzw
  udiv r7.xyzw, null, r7.xyzw, l(3, 3, 3, 3)
  bfi r6.xyzw, l(8, 8, 8, 8), l(8, 8, 8, 8), r7.xyzw, r6.xyzw
  ushr r5.xyzw, r5.xyzw, l(20, 20, 20, 20)
  udiv r5.xyzw, null, r5.xyzw, l(3, 3, 3, 3)
  or r5.xyzw, r5.xyzw, r6.xyzw
  ubfe r6.xyzw, l(4, 4, 4, 4), l(16, 20, 24, 28), r3.xxxx
  imad r5.xyzw, r6.xyzw, l(0x11000000, 0x11000000, 0x11000000, 0x11000000), r5.xyzw
  store_uav_typed U0[0].xyzw, r3.zzzz, r5.xyzw
  imad r3.x, vThreadID.y, l(4), l(2)
  ilt r3.x, r3.x, CB0[0][2].z
  if_nz r3.x
    ishl r3.x, r0.z, l(1)
    iadd r3.x, r0.y, r3.x
    ushr r5.x, r4.x, l(16)
    not r6.x, r5.x
    ushr r6.yzw, r6.xxxx, l(0, 2, 4, 6)
    and r6.xyzw, r6.xyzw, l(3, 3, 3, 3)
    ushr r5.yzw, r5.xxxx, l(0, 2, 4, 6)
    and r5.xyzw, r5.xyzw, l(3, 3, 3, 3)
    imul null, r5.xyzw, r1.wwww, r5.xyzw
    imad r5.xyzw, r6.xyzw, r1.zzzz, r5.xyzw
    and r6.xyzw, r5.xyzw, l(1023, 1023, 1023, 1023)
    udiv r6.xyzw, null, r6.xyzw, l(3, 3, 3, 3)
    ishl r6.xyzw, r6.xyzw, l(16, 16, 16, 16)
    ubfe r7.xyzw, l(10, 10, 10, 10), l(10, 10, 10, 10), r5.xyzw
    udiv r7.xyzw, null, r7.xyzw, l(3, 3, 3, 3)
    bfi r6.xyzw, l(8, 8, 8, 8), l(8, 8, 8, 8), r7.xyzw, r6.xyzw
    ushr r5.xyzw, r5.xyzw, l(20, 20, 20, 20)
    udiv r5.xyzw, null, r5.xyzw, l(3, 3, 3, 3)
    or r5.xyzw, r5.xyzw, r6.xyzw
    ushr r2.yzw, r2.xxxx, l(0, 4, 8, 12)
    and r6.xyzw, r2.xyzw, l(15, 15, 15, 15)
    imad r5.xyzw, r6.xyzw, l(0x11000000, 0x11000000, 0x11000000, 0x11000000), r5.xyzw
    store_uav_typed U0[0].xyzw, r3.xxxx, r5.xyzw
    imad r2.y, vThreadID.y, l(4), l(3)
    ilt r2.y, r2.y, CB0[0][2].z
    if_nz r2.y
      imad r2.y, l(3), r0.z, r0.y
      ushr r4.x, r4.x, l(24)
      not r5.x, r4.x
      ushr r5.yzw, r5.xxxx, l(0, 2, 4, 6)
      and r5.xyzw, r5.xyzw, l(3, 3, 3, 3)
      ushr r4.yzw, r4.xxxx, l(0, 2, 4, 6)
      and r4.xyzw, r4.xyzw, l(3, 3, 3, 3)
      imul null, r4.xyzw, r1.wwww, r4.xyzw
      imad r4.xyzw, r5.xyzw, r1.zzzz, r4.xyzw
      and r5.xyzw, r4.xyzw, l(1023, 1023, 1023, 1023)
      udiv r5.xyzw, null, r5.xyzw, l(3, 3, 3, 3)
      ishl r5.xyzw, r5.xyzw, l(16, 16, 16, 16)
      ubfe r6.xyzw, l(10, 10, 10, 10), l(10, 10, 10, 10), r4.xyzw
      udiv r6.xyzw, null, r6.xyzw, l(3, 3, 3, 3)
      bfi r5.xyzw, l(8, 8, 8, 8), l(8, 8, 8, 8), r6.xyzw, r5.xyzw
      ushr r4.xyzw, r4.xyzw, l(20, 20, 20, 20)
      udiv r4.xyzw, null, r4.xyzw, l(3, 3, 3, 3)
      or r4.xyzw, r4.xyzw, r5.xyzw
      ubfe r5.xyzw, l(4, 4, 4, 4), l(16, 20, 24, 28), r2.xxxx
      imad r4.xyzw, r5.xyzw, l(0x11000000, 0x11000000, 0x11000000, 0x11000000), r4.xyzw
      store_uav_typed U0[0].xyzw, r2.yyyy, r4.xyzw
    endif 
  endif 
endif 
iadd r0.y, r0.y, l(1)
movc r0.w, r0.w, l(2), l(1)
iadd r0.x, r0.w, r0.x
ld r2.xyzw, r0.xxxx, T0[0].yxzw
if_nz r1.x
  ishl r4.xyzw, r2.yxzw, l(8, 8, 8, 8)
  and r4.xyzw, r4.xyzw, l(0xff00ff00, 0xff00ff00, 0xff00ff00, 0xff00ff00)
  ushr r5.xyzw, r2.yxzw, l(8, 8, 8, 8)
  and r5.xyzw, r5.xyzw, l(0x00ff00ff, 0x00ff00ff, 0x00ff00ff, 0x00ff00ff)
  iadd r2.xyzw, r4.yxzw, r5.yxzw
endif 
if_nz r1.y
  ushr r1.xyzw, r2.yxzw, l(16, 16, 16, 16)
  bfi r2.xyzw, l(16, 16, 16, 16), l(16, 16, 16, 16), r2.xyzw, r1.yxzw
  mov r1.x, r2.y
else 
  mov r1.x, r2.y
endif 
ishl r4.xyz, r2.zzzz, l(3, 7, 12, 0)
ushr r5.xyz, r2.zzzz, l(13, 4, 9, 0)
mov r4.w, r5.x
and r0.xw, r4.xxxw, l(248, 0, 0, 248)
mov r5.xw, r4.zzzy
and r3.xz, r5.wwzw, l(0x0003f000, 0, 0x0003f000, 0)
iadd r0.xw, r0.xxxw, r3.xxxz
and r3.xz, r5.xxyx, l(0x0f800000, 0, 0x0f800000, 0)
iadd r0.xw, r0.xxxw, r3.xxxz
ushr r3.xz, r0.xxwx, l(5, 0, 5, 0)
and r3.xz, r3.xxzx, l(0x00700007, 0, 0x00700007, 0)
iadd r0.xw, r0.xxxw, r3.xxxz
ushr r3.xz, r0.xxwx, l(6, 0, 6, 0)
and r3.xz, r3.xxzx, l(3072, 0, 3072, 0)
iadd r0.xw, r0.xxxw, r3.xxxz
ishl r3.x, r2.w, l(1)
ushr r3.z, r2.w, l(1)
and r3.xz, r3.xxzx, l(0xaaaaaaaa, 0, 0x55555555, 0)
iadd r3.x, r3.z, r3.x
ushr r3.z, r3.x, l(1)
and r3.z, r3.z, l(0x55555555)
xor r4.x, r3.z, r3.x
not r5.x, r4.x
ushr r5.yzw, r5.xxxx, l(0, 2, 4, 6)
and r5.xyzw, r5.xyzw, l(3, 3, 3, 3)
ushr r4.yzw, r4.xxxx, l(0, 2, 4, 6)
and r6.xyzw, r4.xyzw, l(3, 3, 3, 3)
imul null, r6.xyzw, r0.wwww, r6.xyzw
imad r5.xyzw, r5.xyzw, r0.xxxx, r6.xyzw
and r6.xyzw, r5.xyzw, l(1023, 1023, 1023, 1023)
udiv r6.xyzw, null, r6.xyzw, l(3, 3, 3, 3)
ishl r6.xyzw, r6.xyzw, l(16, 16, 16, 16)
ubfe r7.xyzw, l(10, 10, 10, 10), l(10, 10, 10, 10), r5.xyzw
udiv r7.xyzw, null, r7.xyzw, l(3, 3, 3, 3)
bfi r6.xyzw, l(8, 8, 8, 8), l(8, 8, 8, 8), r7.xyzw, r6.xyzw
ushr r5.xyzw, r5.xyzw, l(20, 20, 20, 20)
udiv r5.xyzw, null, r5.xyzw, l(3, 3, 3, 3)
or r5.xyzw, r5.xyzw, r6.xyzw
ushr r1.yzw, r1.xxxx, l(0, 4, 8, 12)
and r6.xyzw, r1.xyzw, l(15, 15, 15, 15)
imad r5.xyzw, r6.xyzw, l(0x11000000, 0x11000000, 0x11000000, 0x11000000), r5.xyzw
store_uav_typed U0[0].xyzw, r0.yyyy, r5.xyzw
if_nz r3.y
  iadd r1.y, r0.z, r0.y
  ushr r3.x, r4.x, l(8)
  not r5.x, r3.x
  ushr r5.yzw, r5.xxxx, l(0, 2, 4, 6)
  and r5.xyzw, r5.xyzw, l(3, 3, 3, 3)
  ushr r3.yzw, r3.xxxx, l(0, 2, 4, 6)
  and r3.xyzw, r3.xyzw, l(3, 3, 3, 3)
  imul null, r3.xyzw, r0.wwww, r3.xyzw
  imad r3.xyzw, r5.xyzw, r0.xxxx, r3.xyzw
  and r5.xyzw, r3.xyzw, l(1023, 1023, 1023, 1023)
  udiv r5.xyzw, null, r5.xyzw, l(3, 3, 3, 3)
  ishl r5.xyzw, r5.xyzw, l(16, 16, 16, 16)
  ubfe r6.xyzw, l(10, 10, 10, 10), l(10, 10, 10, 10), r3.xyzw
  udiv r6.xyzw, null, r6.xyzw, l(3, 3, 3, 3)
  bfi r5.xyzw, l(8, 8, 8, 8), l(8, 8, 8, 8), r6.xyzw, r5.xyzw
  ushr r3.xyzw, r3.xyzw, l(20, 20, 20, 20)
  udiv r3.xyzw, null, r3.xyzw, l(3, 3, 3, 3)
  or r3.xyzw, r3.xyzw, r5.xyzw
  ubfe r5.xyzw, l(4, 4, 4, 4), l(16, 20, 24, 28), r1.xxxx
  imad r3.xyzw, r5.xyzw, l(0x11000000, 0x11000000, 0x11000000, 0x11000000), r3.xyzw
  store_uav_typed U0[0].xyzw, r1.yyyy, r3.xyzw
  imad r1.x, vThreadID.y, l(4), l(2)
  ilt r1.x, r1.x, CB0[0][2].z
  if_nz r1.x
    ishl r1.x, r0.z, l(1)
    iadd r1.x, r0.y, r1.x
    ushr r3.x, r4.x, l(16)
    not r5.x, r3.x
    ushr r5.yzw, r5.xxxx, l(0, 2, 4, 6)
    and r5.xyzw, r5.xyzw, l(3, 3, 3, 3)
    ushr r3.yzw, r3.xxxx, l(0, 2, 4, 6)
    and r3.xyzw, r3.xyzw, l(3, 3, 3, 3)
    imul null, r3.xyzw, r0.wwww, r3.xyzw
    imad r3.xyzw, r5.xyzw, r0.xxxx, r3.xyzw
    and r5.xyzw, r3.xyzw, l(1023, 1023, 1023, 1023)
    udiv r5.xyzw, null, r5.xyzw, l(3, 3, 3, 3)
    ishl r5.xyzw, r5.xyzw, l(16, 16, 16, 16)
    ubfe r6.xyzw, l(10, 10, 10, 10), l(10, 10, 10, 10), r3.xyzw
    udiv r6.xyzw, null, r6.xyzw, l(3, 3, 3, 3)
    bfi r5.xyzw, l(8, 8, 8, 8), l(8, 8, 8, 8), r6.xyzw, r5.xyzw
    ushr r3.xyzw, r3.xyzw, l(20, 20, 20, 20)
    udiv r3.xyzw, null, r3.xyzw, l(3, 3, 3, 3)
    or r3.xyzw, r3.xyzw, r5.xyzw
    ushr r2.yzw, r2.xxxx, l(0, 4, 8, 12)
    and r5.xyzw, r2.xyzw, l(15, 15, 15, 15)
    imad r3.xyzw, r5.xyzw, l(0x11000000, 0x11000000, 0x11000000, 0x11000000), r3.xyzw
    store_uav_typed U0[0].xyzw, r1.xxxx, r3.xyzw
    imad r1.x, vThreadID.y, l(4), l(3)
    ilt r1.x, r1.x, CB0[0][2].z
    if_nz r1.x
      imad r0.y, l(3), r0.z, r0.y
      ushr r1.x, r4.x, l(24)
      not r3.x, r1.x
      ushr r3.yzw, r3.xxxx, l(0, 2, 4, 6)
      and r3.xyzw, r3.xyzw, l(3, 3, 3, 3)
      ushr r1.yzw, r1.xxxx, l(0, 2, 4, 6)
      and r1.xyzw, r1.xyzw, l(3, 3, 3, 3)
      imul null, r1.xyzw, r0.wwww, r1.xyzw
      imad r1.xyzw, r3.xyzw, r0.xxxx, r1.xyzw
      and r3.xyzw, r1.xyzw, l(1023, 1023, 1023, 1023)
      udiv r3.xyzw, null, r3.xyzw, l(3, 3, 3, 3)
      ishl r3.xyzw, r3.xyzw, l(16, 16, 16, 16)
      ubfe r4.xyzw, l(10, 10, 10, 10), l(10, 10, 10, 10), r1.xyzw
      udiv r4.xyzw, null, r4.xyzw, l(3, 3, 3, 3)
      bfi r3.xyzw, l(8, 8, 8, 8), l(8, 8, 8, 8), r4.xyzw, r3.xyzw
      ushr r1.xyzw, r1.xyzw, l(20, 20, 20, 20)
      udiv r1.xyzw, null, r1.xyzw, l(3, 3, 3, 3)
      or r1.xyzw, r1.xyzw, r3.xyzw
      ubfe r2.xyzw, l(4, 4, 4, 4), l(16, 20, 24, 28), r2.xxxx
      imad r1.xyzw, r2.xyzw, l(0x11000000, 0x11000000, 0x11000000, 0x11000000), r1.xyzw
      store_uav_typed U0[0].xyzw, r0.yyyy, r1.xyzw
    endif 
  endif 
endif 
ret 
// Approximately 353 instruction slots used
