//
// Generated by Microsoft (R) HLSL Shader Compiler 10.1
//
//
// Buffer Definitions: 
//
// cbuffer XeEdramLoadStoreConstants
// {
//
//   uint xe_edram_rt_color_depth_offset;// Offset:    0 Size:     4
//   uint xe_edram_rt_color_depth_pitch;// Offset:    4 Size:     4
//   uint xe_edram_rt_stencil_offset;   // Offset:    8 Size:     4
//   uint xe_edram_rt_stencil_pitch;    // Offset:   12 Size:     4
//   uint xe_edram_base_samples_2x_depth_pitch;// Offset:   16 Size:     4
//
// }
//
//
// Resource Bindings:
//
// Name                                 Type  Format         Dim      ID      HLSL Bind  Count
// ------------------------------ ---------- ------- ----------- ------- -------------- ------
// xe_edram_load_store_source        texture    byte         r/o      T0             t0      1 
// xe_edram_load_store_dest              UAV    byte         r/w      U0             u0      1 
// XeEdramLoadStoreConstants         cbuffer      NA          NA     CB0            cb0      1 
//
//
//
// Input signature:
//
// Name                 Index   Mask Register SysValue  Format   Used
// -------------------- ----- ------ -------- -------- ------- ------
// no Input
//
// Output signature:
//
// Name                 Index   Mask Register SysValue  Format   Used
// -------------------- ----- ------ -------- -------- ------- ------
// no Output
cs_5_1
dcl_globalFlags refactoringAllowed
dcl_constantbuffer CB0[0:0][2], immediateIndexed, space=0
dcl_resource_raw T0[0:0], space=0
dcl_uav_raw U0[0:0], space=0
dcl_input vThreadGroupID.xy
dcl_input vThreadIDInGroup.xy
dcl_input vThreadID.xy
dcl_temps 4
dcl_thread_group 20, 16, 1
ishl r0.xy, vThreadID.xxxx, l(4, 2, 0, 0)
imad r0.xy, vThreadID.yyyy, CB0[0][0].ywyy, r0.xyxx
iadd r0.xy, r0.xyxx, CB0[0][0].xzxx
ld_raw r1.xyzw, r0.x, T0[0].xyzw
uge r2.xyzw, l(0x7fffffff, 0x7fffffff, 0x7fffffff, 0x7fffffff), r1.xyzw
and r1.xyzw, r1.xyzw, r2.xyzw
umin r1.xyzw, r1.xyzw, l(0x3ffffff8, 0x3ffffff8, 0x3ffffff8, 0x3ffffff8)
bfi r2.xyzw, l(23, 23, 23, 23), l(0, 0, 0, 0), r1.xyzw, l(0x00800000, 0x00800000, 0x00800000, 0x00800000)
ushr r3.xyzw, r1.xyzw, l(23, 23, 23, 23)
iadd r3.xyzw, -r3.xyzw, l(113, 113, 113, 113)
umin r3.xyzw, r3.xyzw, l(24, 24, 24, 24)
ushr r2.xyzw, r2.xyzw, r3.xyzw
ult r3.xyzw, r1.xyzw, l(0x38800000, 0x38800000, 0x38800000, 0x38800000)
iadd r1.xyzw, r1.xyzw, l(0xc8000000, 0xc8000000, 0xc8000000, 0xc8000000)
movc r1.xyzw, r3.xyzw, r2.xyzw, r1.xyzw
iadd r2.xyzw, r1.xyzw, l(3, 3, 3, 3)
ubfe r1.xyzw, l(1, 1, 1, 1), l(3, 3, 3, 3), r1.xyzw
iadd r1.xyzw, r1.xyzw, r2.xyzw
ushr r1.xyzw, r1.xyzw, l(3, 3, 3, 3)
ld_raw r0.x, r0.y, T0[0].xxxx
ushr r0.yzw, r0.xxxx, l(0, 8, 16, 24)
bfi r0.xyzw, l(24, 24, 24, 24), l(8, 8, 8, 8), r1.xyzw, r0.xyzw
ishl r1.x, vThreadIDInGroup.x, l(2)
and r1.yz, CB0[0][1].xxxx, l(0, 0x00008000, 2047, 0)
if_nz r1.y
  ult r1.y, vThreadIDInGroup.x, l(10)
  uge r1.w, vThreadIDInGroup.x, l(10)
  and r1.yw, r1.yyyw, l(0, 40, 0, -40)
  iadd r1.y, r1.w, r1.y
  iadd r1.x, r1.y, r1.x
endif 
ushr r1.y, CB0[0][1].x, l(16)
imad r1.y, vThreadGroupID.y, r1.y, r1.z
iadd r1.y, r1.y, vThreadGroupID.x
imul null, r1.z, vThreadIDInGroup.y, l(320)
imad r1.y, r1.y, l(5120), r1.z
ishl r1.x, r1.x, l(2)
iadd r1.x, r1.x, r1.y
ubfe r1.y, l(1), l(13), CB0[0][1].x
ishl r1.y, r1.y, l(1)
ishl r1.x, r1.x, r1.y
store_raw U0[0].xyzw, r1.x, r0.xyzw
ret 
// Approximately 43 instruction slots used
