//
// Generated by Microsoft (R) HLSL Shader Compiler 10.1
//
//
// Buffer Definitions: 
//
// cbuffer XeTextureTileConstants
// {
//
//   uint xe_texture_tile_guest_base;   // Offset:    0 Size:     4
//   uint xe_texture_tile_endian_format_guest_pitch;// Offset:    4 Size:     4
//   uint xe_texture_tile_size;         // Offset:    8 Size:     4
//   uint xe_texture_tile_host_base;    // Offset:   12 Size:     4
//   uint xe_texture_tile_host_pitch;   // Offset:   16 Size:     4
//
// }
//
//
// Resource Bindings:
//
// Name                                 Type  Format         Dim      ID      HLSL Bind  Count
// ------------------------------ ---------- ------- ----------- ------- -------------- ------
// xe_texture_tile_source            texture    byte         r/o      T0             t0      1 
// xe_texture_tile_dest                  UAV    uint         buf      U0             u0      1 
// XeTextureTileConstants            cbuffer      NA          NA     CB0            cb0      1 
//
//
//
// Input signature:
//
// Name                 Index   Mask Register SysValue  Format   Used
// -------------------- ----- ------ -------- -------- ------- ------
// no Input
//
// Output signature:
//
// Name                 Index   Mask Register SysValue  Format   Used
// -------------------- ----- ------ -------- -------- ------- ------
// no Output
cs_5_1
dcl_globalFlags refactoringAllowed
dcl_constantbuffer CB0[0:0][2], immediateIndexed, space=0
dcl_resource_raw T0[0:0], space=0
dcl_uav_typed_buffer (uint,uint,uint,uint) U0[0:0], space=0
dcl_input vThreadID.xy
dcl_temps 7
dcl_thread_group 8, 32, 1
ushr r0.y, CB0[0][0].z, l(16)
mov r0.x, CB0[0][0].z
and r0.xy, r0.xyxx, l(0x0000ffff, 0x0000ffff, 0, 0)
ishl r1.x, vThreadID.x, l(2)
mov r1.y, vThreadID.y
uge r0.yz, r1.xxyx, r0.xxyx
or r0.y, r0.z, r0.y
if_nz r0.y
  ret 
endif 
imad r0.y, vThreadID.y, CB0[0][1].x, CB0[0][0].w
iadd r0.y, r1.x, r0.y
ld_raw r1.x, r0.y, T0[0].xxxx
ushr r1.yzw, r1.xxxx, l(0, 8, 16, 24)
and r1.xyzw, r1.xyzw, l(255, 255, 255, 255)
ushr r0.y, CB0[0][0].y, l(9)
imad r2.xyzw, vThreadID.xxxx, l(4, 4, 4, 4), l(0, 1, 2, 3)
ubfe r0.zw, l(0, 0, 27, 29), l(0, 0, 3, 1), vThreadID.xxxx
ushr r3.xy, vThreadID.yyyy, l(5, 2, 0, 0)
iadd r0.y, r0.y, l(31)
ushr r0.y, r0.y, l(5)
imad r0.y, r3.x, r0.y, r0.z
and r4.xyzw, r2.xyzw, l(7, 7, 7, 7)
ishl r3.xz, vThreadID.yyyy, l(2, 0, 7, 0)
and r3.xz, r3.xxzx, l(56, 0, 2048, 0)
iadd r4.xyzw, r3.xxxx, r4.xyzw
ishl r5.xyzw, r4.xyzw, l(1, 1, 1, 1)
and r5.xyzw, r5.xyzw, l(96, 96, 96, 96)
bfi r5.xyzw, l(25, 25, 25, 25), l(7, 7, 7, 7), r0.yyyy, r5.xyzw
and r4.xyzw, r4.xyzw, l(15, 15, 15, 15)
iadd r4.xyzw, r4.xyzw, r5.xyzw
bfi r5.xyzw, l(1, 1, 1, 1), l(4, 4, 4, 4), vThreadID.yyyy, r4.xyzw
ishl r6.xyzw, r4.xyzw, l(3, 3, 3, 3)
bfi r6.xyzw, l(1, 1, 1, 1), l(7, 7, 7, 7), vThreadID.yyyy, r6.xyzw
bfi r6.xyzw, l(12, 12, 12, 12), l(0, 0, 0, 0), r3.zzzz, r6.xyzw
ishl r4.xyzw, r4.xyzw, l(2, 2, 2, 2)
bfi r4.xyzw, l(1, 1, 1, 1), l(6, 6, 6, 6), vThreadID.yyyy, r4.xyzw
and r4.xyzw, r4.xyzw, l(1792, 1792, 1792, 1792)
iadd r4.xyzw, r6.xyzw, r4.xyzw
and r0.y, r3.y, l(2)
iadd r0.y, r0.y, r0.w
bfi r0.y, l(2), l(6), r0.y, l(0)
iadd r3.xyzw, r4.xyzw, r0.yyyy
and r4.xyzw, r5.xyzw, l(63, 63, 63, 63)
iadd r3.xyzw, r3.xyzw, r4.xyzw
iadd r3.xyzw, r3.xyzw, CB0[0][0].xxxx
store_uav_typed U0[0].xyzw, r3.xxxx, r1.xxxx
ult r0.xyz, r2.yzwy, r0.xxxx
if_nz r0.x
  store_uav_typed U0[0].xyzw, r3.yyyy, r1.yyyy
  if_nz r0.y
    store_uav_typed U0[0].xyzw, r3.zzzz, r1.zzzz
    if_nz r0.z
      store_uav_typed U0[0].xyzw, r3.wwww, r1.wwww
    endif 
  endif 
endif 
ret 
// Approximately 58 instruction slots used
