//
// Generated by Microsoft (R) HLSL Shader Compiler 10.1
//
//
// Buffer Definitions: 
//
// cbuffer XeEDRAMLoadStoreConstants
// {
//
//   uint4 xe_edram_load_store_constants;// Offset:    0 Size:    16
//   uint xe_edram_base_depth_pitch;    // Offset:   16 Size:     4
//
// }
//
//
// Resource Bindings:
//
// Name                                 Type  Format         Dim      ID      HLSL Bind  Count
// ------------------------------ ---------- ------- ----------- ------- -------------- ------
// xe_edram_load_store_source        texture    byte         r/o      T0             t0      1 
// xe_edram_load_store_dest              UAV    byte         r/w      U0             u0      1 
// XeEDRAMLoadStoreConstants         cbuffer      NA          NA     CB0            cb0      1 
//
//
//
// Input signature:
//
// Name                 Index   Mask Register SysValue  Format   Used
// -------------------- ----- ------ -------- -------- ------- ------
// no Input
//
// Output signature:
//
// Name                 Index   Mask Register SysValue  Format   Used
// -------------------- ----- ------ -------- -------- ------- ------
// no Output
cs_5_1
dcl_globalFlags refactoringAllowed
dcl_constantbuffer CB0[0:0][2], immediateIndexed, space=0
dcl_resource_raw T0[0:0], space=0
dcl_uav_raw U0[0:0], space=0
dcl_input vThreadGroupID.xy
dcl_input vThreadIDInGroup.xy
dcl_input vThreadID.xy
dcl_temps 2
dcl_thread_group 40, 16, 1
and r0.x, CB0[0][1].x, l(2047)
ushr r0.y, CB0[0][1].x, l(12)
imad r0.x, vThreadGroupID.y, r0.y, r0.x
ishl r0.y, vThreadGroupID.x, l(1)
iadd r0.x, r0.y, r0.x
imul null, r0.y, vThreadIDInGroup.y, l(640)
imad r0.x, r0.x, l(5120), r0.y
ishl r0.y, vThreadIDInGroup.x, l(4)
iadd r0.x, r0.y, r0.x
ld_raw r0.xyzw, r0.x, T0[0].xyzw
ishl r1.x, vThreadID.x, l(4)
imad r1.x, vThreadID.y, CB0[0][0].y, r1.x
iadd r1.x, r1.x, CB0[0][0].x
store_raw U0[0].xyzw, r1.x, r0.xyzw
ret 
// Approximately 15 instruction slots used
