//
// Generated by Microsoft (R) HLSL Shader Compiler 10.1
//
//
// Buffer Definitions: 
//
// cbuffer XeTextureLoadConstants
// {
//
//   uint xe_texture_load_guest_base;   // Offset:    0 Size:     4
//   uint xe_texture_load_guest_pitch;  // Offset:    4 Size:     4
//   uint2 xe_texture_load_guest_storage_width_height;// Offset:    8 Size:     8
//   uint3 xe_texture_load_size_blocks; // Offset:   16 Size:    12
//   uint xe_texture_load_is_3d_endian; // Offset:   28 Size:     4
//   uint xe_texture_load_host_base;    // Offset:   32 Size:     4
//   uint xe_texture_load_host_pitch;   // Offset:   36 Size:     4
//   uint xe_texture_load_height_texels;// Offset:   40 Size:     4 [unused]
//
// }
//
//
// Resource Bindings:
//
// Name                                 Type  Format         Dim      ID      HLSL Bind  Count
// ------------------------------ ---------- ------- ----------- ------- -------------- ------
// xe_texture_load_source            texture   uint4         buf      T0             t0      1 
// xe_texture_load_dest                  UAV   uint4         buf      U0             u0      1 
// XeTextureLoadConstants            cbuffer      NA          NA     CB0            cb0      1 
//
//
//
// Input signature:
//
// Name                 Index   Mask Register SysValue  Format   Used
// -------------------- ----- ------ -------- -------- ------- ------
// no Input
//
// Output signature:
//
// Name                 Index   Mask Register SysValue  Format   Used
// -------------------- ----- ------ -------- -------- ------- ------
// no Output
cs_5_1
dcl_globalFlags refactoringAllowed
dcl_constantbuffer CB0[0:0][3], immediateIndexed, space=0
dcl_resource_buffer (uint,uint,uint,uint) T0[0:0], space=0
dcl_uav_typed_buffer (uint,uint,uint,uint) U0[0:0], space=0
dcl_input vThreadID.xyz
dcl_temps 6
dcl_thread_group 4, 32, 1
ishl r0.x, vThreadID.x, l(3)
mov r0.yz, vThreadID.yyzy
uge r0.yzw, r0.xxyz, CB0[0][1].xxyz
or r0.y, r0.z, r0.y
or r0.y, r0.w, r0.y
if_nz r0.y
  ret 
endif 
ishl r0.y, r0.x, l(3)
imad r0.z, vThreadID.z, CB0[0][1].y, vThreadID.y
imad r0.y, r0.z, CB0[0][2].y, r0.y
iadd r0.y, r0.y, CB0[0][2].x
ieq r0.z, CB0[0][0].y, l(-1)
if_nz r0.z
  and r0.w, CB0[0][1].w, l(1)
  if_nz r0.w
    iadd r1.xy, CB0[0][0].wzww, l(31, 31, 0, 0)
    ishr r2.xyz, vThreadID.yzyy, l(4, 2, 3, 0)
    ushr r1.xy, r1.xyxx, l(4, 5, 0, 0)
    and r0.w, r1.x, l(0x0ffffffe)
    imad r0.w, r2.y, r0.w, r2.x
    ibfe r1.xz, l(27, 0, 29, 0), l(2, 0, 0, 0), vThreadID.xxxx
    imad r0.w, r0.w, r1.y, r1.x
    ishl r1.x, vThreadID.y, l(10)
    ishr r1.x, r1.x, l(6)
    and r1.x, r1.x, l(96)
    iadd r1.y, r2.y, r2.z
    bfi r1.w, l(1), l(1), r1.y, l(0)
    iadd r1.z, r1.w, r1.z
    bfi r1.z, l(2), l(1), r1.z, l(0)
    bfi r1.y, l(1), l(0), r1.y, r1.z
    bfi r1.zw, l(0, 0, 20, 20), l(0, 0, 10, 13), r0.wwww, l(0, 0, 0, 0)
    imad r1.xz, r1.xxxx, l(2, 0, 16, 0), r1.zzwz
    bfi r1.xz, l(2, 0, 2, 0), l(8, 0, 11, 0), vThreadID.zzzz, r1.xxzx
    bfi r0.w, l(1), l(4), vThreadID.y, l(0)
    ubfe r1.w, l(3), l(6), r1.x
    and r2.x, r1.y, l(6)
    bfi r1.y, l(1), l(8), r1.y, l(0)
    imad r1.y, r1.w, l(32), r1.y
    imad r1.y, r2.x, l(4), r1.y
    bfi r1.xz, l(6, 0, 6, 0), l(0, 0, 3, 0), r0.wwww, r1.xxzx
    bfi r0.w, l(9), l(3), r1.y, r1.z
    bfi r0.w, l(6), l(0), r1.x, r0.w
  else 
    ibfe r1.xy, l(27, 29, 0, 0), l(2, 0, 0, 0), vThreadID.xxxx
    ishr r1.zw, vThreadID.yyyy, l(0, 0, 5, 2)
    iadd r2.x, CB0[0][0].z, l(31)
    ushr r2.x, r2.x, l(5)
    imad r1.x, r1.z, r2.x, r1.x
    ishl r2.xy, vThreadID.yyyy, l(5, 7, 0, 0)
    and r2.xy, r2.xyxx, l(448, 2048, 0, 0)
    bfi r1.z, l(23), l(9), r1.x, r2.x
    bfi r2.z, l(1), l(4), vThreadID.y, l(0)
    iadd r1.z, r1.z, r2.z
    ishl r2.xw, r2.xxxx, l(3, 0, 0, 2)
    bfi r2.xw, l(23, 0, 0, 23), l(12, 0, 0, 11), r1.xxxx, r2.xxxw
    imad r2.xz, r2.zzzz, l(8, 0, 4, 0), r2.xxwx
    bfi r1.x, l(12), l(0), r2.y, r2.x
    and r2.x, r2.z, l(1792)
    iadd r1.x, r1.x, r2.x
    and r1.w, r1.w, l(2)
    iadd r1.y, r1.y, r1.w
    bfi r1.y, l(2), l(6), r1.y, l(0)
    iadd r1.x, r1.x, r1.y
    bfi r0.w, l(6), l(0), r1.z, r1.x
  endif 
else 
  ishl r0.x, r0.x, l(2)
  iadd r1.x, CB0[0][1].y, l(31)
  and r1.x, r1.x, l(-32)
  imad r1.x, vThreadID.z, r1.x, vThreadID.y
  imad r0.w, r1.x, CB0[0][0].y, r0.x
endif 
iadd r0.x, r0.w, CB0[0][0].x
ushr r0.xy, r0.xyxx, l(4, 4, 0, 0)
ushr r0.w, CB0[0][1].w, l(1)
ld r1.xyzw, r0.xxxx, T0[0].xyzw
ieq r2.xyz, r0.wwww, l(1, 2, 3, 0)
or r2.xy, r2.yzyy, r2.xyxx
if_nz r2.x
  ishl r3.xyzw, r1.xyzw, l(8, 8, 8, 8)
  and r3.xyzw, r3.xyzw, l(0xff00ff00, 0xff00ff00, 0xff00ff00, 0xff00ff00)
  ushr r4.xyzw, r1.xyzw, l(8, 8, 8, 8)
  and r4.xyzw, r4.xyzw, l(0x00ff00ff, 0x00ff00ff, 0x00ff00ff, 0x00ff00ff)
  iadd r1.xyzw, r3.xyzw, r4.xyzw
endif 
if_nz r2.y
  ushr r3.xyzw, r1.xyzw, l(16, 16, 16, 16)
  bfi r1.xyzw, l(16, 16, 16, 16), l(16, 16, 16, 16), r1.xyzw, r3.xyzw
endif 
and r2.zw, r1.xxxy, l(0, 0, 2047, 2047)
ubfe r3.xyzw, l(1, 1, 11, 11), l(10, 10, 11, 11), r1.xyxy
ieq r4.xy, r2.zwzz, l(1024, 1024, 0, 0)
movc r2.zw, r4.xxxy, l(0,0,1025,1025), r2.zzzw
movc r4.xyzw, r3.xyxy, l(2047,2047,0x0000ffff,0x0000ffff), l(0,0,0,0)
xor r2.zw, r2.zzzw, r4.xxxy
iadd r2.zw, r3.xxxy, r2.zzzw
ishl r4.xy, r2.zwzz, l(5, 5, 0, 0)
ushr r2.zw, r2.zzzw, l(0, 0, 5, 5)
or r2.zw, r2.zzzw, r4.xxxy
xor r2.zw, r4.zzzw, r2.zzzw
iadd r2.zw, r3.xxxy, r2.zzzw
ubfe r3.xy, l(1, 1, 0, 0), l(21, 21, 0, 0), r1.xyxx
ieq r4.xy, r3.zwzz, l(1024, 1024, 0, 0)
movc r3.zw, r4.xxxy, l(0,0,1025,1025), r3.zzzw
movc r4.xyzw, r3.xyxy, l(2047,2047,0x0000ffff,0x0000ffff), l(0,0,0,0)
xor r3.zw, r3.zzzw, r4.xxxy
iadd r3.zw, r3.xxxy, r3.zzzw
ishl r4.xy, r3.zwzz, l(5, 5, 0, 0)
ushr r3.zw, r3.zzzw, l(0, 0, 5, 5)
or r3.zw, r3.zzzw, r4.xxxy
xor r3.zw, r4.zzzw, r3.zzzw
iadd r3.xy, r3.xyxx, r3.zwzz
ishl r3.xy, r3.xyxx, l(16, 16, 0, 0)
or r3.xz, r2.zzwz, r3.xxyx
ushr r1.xy, r1.xyxx, l(22, 22, 0, 0)
ushr r2.zw, r1.xxxy, l(0, 0, 9, 9)
ieq r4.xy, r1.xyxx, l(512, 512, 0, 0)
movc r1.xy, r4.xyxx, l(513,513,0,0), r1.xyxx
movc r4.xyzw, r2.zwzw, l(1023,1023,0x0000ffff,0x0000ffff), l(0,0,0,0)
xor r1.xy, r1.xyxx, r4.xyxx
iadd r1.xy, r2.zwzz, r1.xyxx
ishl r4.xy, r1.xyxx, l(6, 6, 0, 0)
ushr r1.xy, r1.xyxx, l(3, 3, 0, 0)
or r1.xy, r1.xyxx, r4.xyxx
xor r1.xy, r4.zwzz, r1.xyxx
iadd r1.xy, r2.zwzz, r1.xyxx
or r3.yw, r1.xxxy, l(0, 0x7fff0000, 0, 0x7fff0000)
and r1.xy, r1.zwzz, l(2047, 2047, 0, 0)
ubfe r4.xyzw, l(1, 1, 11, 11), l(10, 10, 11, 11), r1.zwzw
ieq r2.zw, r1.xxxy, l(0, 0, 1024, 1024)
movc r1.xy, r2.zwzz, l(1025,1025,0,0), r1.xyxx
movc r5.xyzw, r4.xyxy, l(2047,2047,0x0000ffff,0x0000ffff), l(0,0,0,0)
xor r1.xy, r1.xyxx, r5.xyxx
iadd r1.xy, r4.xyxx, r1.xyxx
ishl r2.zw, r1.xxxy, l(0, 0, 5, 5)
ushr r1.xy, r1.xyxx, l(5, 5, 0, 0)
or r1.xy, r1.xyxx, r2.zwzz
xor r1.xy, r5.zwzz, r1.xyxx
iadd r1.xy, r4.xyxx, r1.xyxx
ubfe r2.zw, l(0, 0, 1, 1), l(0, 0, 21, 21), r1.zzzw
ieq r4.xy, r4.zwzz, l(1024, 1024, 0, 0)
movc r4.xy, r4.xyxx, l(1025,1025,0,0), r4.zwzz
movc r5.xyzw, r2.zwzw, l(2047,2047,0x0000ffff,0x0000ffff), l(0,0,0,0)
xor r4.xy, r4.xyxx, r5.xyxx
iadd r4.xy, r2.zwzz, r4.xyxx
ishl r4.zw, r4.xxxy, l(0, 0, 5, 5)
ushr r4.xy, r4.xyxx, l(5, 5, 0, 0)
or r4.xy, r4.xyxx, r4.zwzz
xor r4.xy, r5.zwzz, r4.xyxx
iadd r2.zw, r2.zzzw, r4.xxxy
ishl r2.zw, r2.zzzw, l(0, 0, 16, 16)
or r4.xz, r1.xxyx, r2.zzwz
ushr r1.xy, r1.zwzz, l(22, 22, 0, 0)
ushr r1.zw, r1.xxxy, l(0, 0, 9, 9)
ieq r2.zw, r1.xxxy, l(0, 0, 512, 512)
movc r1.xy, r2.zwzz, l(513,513,0,0), r1.xyxx
movc r5.xyzw, r1.zwzw, l(1023,1023,0x0000ffff,0x0000ffff), l(0,0,0,0)
xor r1.xy, r1.xyxx, r5.xyxx
iadd r1.xy, r1.zwzz, r1.xyxx
ishl r2.zw, r1.xxxy, l(0, 0, 6, 6)
ushr r1.xy, r1.xyxx, l(3, 3, 0, 0)
or r1.xy, r1.xyxx, r2.zwzz
xor r1.xy, r5.zwzz, r1.xyxx
iadd r1.xy, r1.zwzz, r1.xyxx
or r4.yw, r1.xxxy, l(0, 0x7fff0000, 0, 0x7fff0000)
store_uav_typed U0[0].xyzw, r0.yyyy, r3.xyzw
iadd r1.xyz, r0.yyyy, l(1, 2, 3, 0)
store_uav_typed U0[0].xyzw, r1.xxxx, r4.xyzw
movc r0.z, r0.z, l(2), l(1)
iadd r0.x, r0.z, r0.x
ld r3.xyzw, r0.xxxx, T0[0].xyzw
if_nz r2.x
  ishl r4.xyzw, r3.xyzw, l(8, 8, 8, 8)
  and r4.xyzw, r4.xyzw, l(0xff00ff00, 0xff00ff00, 0xff00ff00, 0xff00ff00)
  ushr r5.xyzw, r3.xyzw, l(8, 8, 8, 8)
  and r5.xyzw, r5.xyzw, l(0x00ff00ff, 0x00ff00ff, 0x00ff00ff, 0x00ff00ff)
  iadd r3.xyzw, r4.xyzw, r5.xyzw
endif 
if_nz r2.y
  ushr r2.xyzw, r3.xyzw, l(16, 16, 16, 16)
  bfi r3.xyzw, l(16, 16, 16, 16), l(16, 16, 16, 16), r3.xyzw, r2.xyzw
endif 
and r0.xz, r3.xxyx, l(2047, 0, 2047, 0)
ubfe r2.xyzw, l(1, 1, 11, 11), l(10, 10, 11, 11), r3.xyxy
ieq r1.xw, r0.xxxz, l(1024, 0, 0, 1024)
movc r0.xz, r1.xxwx, l(1025,0,1025,0), r0.xxzx
movc r4.xyzw, r2.xyxy, l(2047,2047,0x0000ffff,0x0000ffff), l(0,0,0,0)
xor r0.xz, r0.xxzx, r4.xxyx
iadd r0.xz, r2.xxyx, r0.xxzx
ishl r1.xw, r0.xxxz, l(5, 0, 0, 5)
ushr r0.xz, r0.xxzx, l(5, 0, 5, 0)
or r0.xz, r0.xxzx, r1.xxwx
xor r0.xz, r4.zzwz, r0.xxzx
iadd r0.xz, r2.xxyx, r0.xxzx
ubfe r1.xw, l(1, 0, 0, 1), l(21, 0, 0, 21), r3.xxxy
ieq r2.xy, r2.zwzz, l(1024, 1024, 0, 0)
movc r2.xy, r2.xyxx, l(1025,1025,0,0), r2.zwzz
movc r4.xyzw, r1.xwxw, l(2047,2047,0x0000ffff,0x0000ffff), l(0,0,0,0)
xor r2.xy, r2.xyxx, r4.xyxx
iadd r2.xy, r1.xwxx, r2.xyxx
ishl r2.zw, r2.xxxy, l(0, 0, 5, 5)
ushr r2.xy, r2.xyxx, l(5, 5, 0, 0)
or r2.xy, r2.xyxx, r2.zwzz
xor r2.xy, r4.zwzz, r2.xyxx
iadd r1.xw, r1.xxxw, r2.xxxy
ishl r1.xw, r1.xxxw, l(16, 0, 0, 16)
or r2.xz, r0.xxzx, r1.xxwx
ushr r0.xz, r3.xxyx, l(22, 0, 22, 0)
ushr r1.xw, r0.xxxz, l(9, 0, 0, 9)
ieq r3.xy, r0.xzxx, l(512, 512, 0, 0)
movc r0.xz, r3.xxyx, l(513,0,513,0), r0.xxzx
movc r4.xyzw, r1.xwxw, l(1023,1023,0x0000ffff,0x0000ffff), l(0,0,0,0)
xor r0.xz, r0.xxzx, r4.xxyx
iadd r0.xz, r1.xxwx, r0.xxzx
ishl r3.xy, r0.xzxx, l(6, 6, 0, 0)
ushr r0.xz, r0.xxzx, l(3, 0, 3, 0)
or r0.xz, r0.xxzx, r3.xxyx
xor r0.xz, r4.zzwz, r0.xxzx
iadd r0.xz, r1.xxwx, r0.xxzx
or r2.yw, r0.xxxz, l(0, 0x7fff0000, 0, 0x7fff0000)
and r0.xz, r3.zzwz, l(2047, 0, 2047, 0)
ubfe r4.xyzw, l(1, 1, 11, 11), l(10, 10, 11, 11), r3.zwzw
ieq r1.xw, r0.xxxz, l(1024, 0, 0, 1024)
movc r0.xz, r1.xxwx, l(1025,0,1025,0), r0.xxzx
movc r5.xyzw, r4.xyxy, l(2047,2047,0x0000ffff,0x0000ffff), l(0,0,0,0)
xor r0.xz, r0.xxzx, r5.xxyx
iadd r0.xz, r4.xxyx, r0.xxzx
ishl r1.xw, r0.xxxz, l(5, 0, 0, 5)
ushr r0.xz, r0.xxzx, l(5, 0, 5, 0)
or r0.xz, r0.xxzx, r1.xxwx
xor r0.xz, r5.zzwz, r0.xxzx
iadd r0.xz, r4.xxyx, r0.xxzx
ubfe r1.xw, l(1, 0, 0, 1), l(21, 0, 0, 21), r3.zzzw
ieq r3.xy, r4.zwzz, l(1024, 1024, 0, 0)
movc r3.xy, r3.xyxx, l(1025,1025,0,0), r4.zwzz
movc r4.xyzw, r1.xwxw, l(2047,2047,0x0000ffff,0x0000ffff), l(0,0,0,0)
xor r3.xy, r3.xyxx, r4.xyxx
iadd r3.xy, r1.xwxx, r3.xyxx
ishl r4.xy, r3.xyxx, l(5, 5, 0, 0)
ushr r3.xy, r3.xyxx, l(5, 5, 0, 0)
or r3.xy, r3.xyxx, r4.xyxx
xor r3.xy, r4.zwzz, r3.xyxx
iadd r1.xw, r1.xxxw, r3.xxxy
ishl r1.xw, r1.xxxw, l(16, 0, 0, 16)
or r4.xz, r0.xxzx, r1.xxwx
ushr r0.xz, r3.zzwz, l(22, 0, 22, 0)
ushr r1.xw, r0.xxxz, l(9, 0, 0, 9)
ieq r3.xy, r0.xzxx, l(512, 512, 0, 0)
movc r0.xz, r3.xxyx, l(513,0,513,0), r0.xxzx
movc r3.xyzw, r1.xwxw, l(1023,1023,0x0000ffff,0x0000ffff), l(0,0,0,0)
xor r0.xz, r0.xxzx, r3.xxyx
iadd r0.xz, r1.xxwx, r0.xxzx
ishl r3.xy, r0.xzxx, l(6, 6, 0, 0)
ushr r0.xz, r0.xxzx, l(3, 0, 3, 0)
or r0.xz, r0.xxzx, r3.xxyx
xor r0.xz, r3.zzwz, r0.xxzx
iadd r0.xz, r1.xxwx, r0.xxzx
or r4.yw, r0.xxxz, l(0, 0x7fff0000, 0, 0x7fff0000)
store_uav_typed U0[0].xyzw, r1.yyyy, r2.xyzw
store_uav_typed U0[0].xyzw, r1.zzzz, r4.xyzw
ret 
// Approximately 262 instruction slots used
