//
// Generated by Microsoft (R) HLSL Shader Compiler 10.1
//
//
// Buffer Definitions: 
//
// cbuffer XeResolveConstants
// {
//
//   uint2 xe_resolve_clear_value;      // Offset:    0 Size:     8
//   uint xe_resolve_edram_info;        // Offset:    8 Size:     4
//   uint xe_resolve_address_info;      // Offset:   12 Size:     4
//
// }
//
//
// Resource Bindings:
//
// Name                                 Type  Format         Dim      ID      HLSL Bind  Count
// ------------------------------ ---------- ------- ----------- ------- -------------- ------
// xe_resolve_dest                       UAV   uint4         buf      U0             u0      1 
// XeResolveConstants                cbuffer      NA          NA     CB0            cb0      1 
//
//
//
// Input signature:
//
// Name                 Index   Mask Register SysValue  Format   Used
// -------------------- ----- ------ -------- -------- ------- ------
// no Input
//
// Output signature:
//
// Name                 Index   Mask Register SysValue  Format   Used
// -------------------- ----- ------ -------- -------- ------- ------
// no Output
cs_5_1
dcl_globalFlags refactoringAllowed
dcl_constantbuffer CB0[0:0][1], immediateIndexed, space=0
dcl_uav_typed_buffer (uint,uint,uint,uint) U0[0:0], space=0
dcl_input vThreadID.xy
dcl_temps 3
dcl_thread_group 8, 8, 1
ubfe r0.xy, l(2, 11, 0, 0), l(10, 7, 0, 0), CB0[0][0].zwzz
uge r0.xz, r0.xxxx, l(2, 0, 1, 0)
and r0.w, r0.x, l(1)
ishl r0.y, r0.y, r0.w
uge r0.y, vThreadID.x, r0.y
if_nz r0.y
  ret 
endif 
ishl r1.x, vThreadID.x, l(3)
ushr r2.y, CB0[0][0].w, l(5)
movc r0.xy, r0.xzxx, l(4,4,0,0), l(3,3,0,0)
mov r2.x, CB0[0][0].w
bfi r0.xy, l(5, 2, 0, 0), r0.xyxx, r2.xyxx, l(0, 0, 0, 0)
mov r1.y, vThreadID.y
iadd r0.xy, r0.xyxx, r1.xyxx
ubfe r0.z, l(12), l(13), CB0[0][0].z
and r0.w, CB0[0][0].z, l(1023)
udiv r1.x, null, r0.x, l(80)
ushr r1.y, r0.y, l(4)
ishl r1.z, r1.x, l(1)
imad r0.w, r1.y, r0.w, r1.z
iadd r0.z, r0.w, r0.z
ineg r2.xy, r1.xyxx
imad r0.xy, r2.xyxx, l(80, 16, 0, 0), r0.xyxx
imad r0.x, r0.y, l(80), r0.x
ishl r0.x, r0.x, l(1)
imad r0.x, r0.z, l(1280), r0.x
store_uav_typed U0[0].xyzw, r0.xxxx, CB0[0][0].xyxy
iadd r1.xyzw, r0.xxxx, l(1, 3, 7, 15)
store_uav_typed U0[0].xyzw, r1.xxxx, CB0[0][0].xyxy
iadd r2.xyzw, r0.xxxx, l(2, 4, 5, 6)
store_uav_typed U0[0].xyzw, r2.xxxx, CB0[0][0].xyxy
store_uav_typed U0[0].xyzw, r1.yyyy, CB0[0][0].xyxy
store_uav_typed U0[0].xyzw, r2.yyyy, CB0[0][0].xyxy
store_uav_typed U0[0].xyzw, r2.zzzz, CB0[0][0].xyxy
store_uav_typed U0[0].xyzw, r2.wwww, CB0[0][0].xyxy
store_uav_typed U0[0].xyzw, r1.zzzz, CB0[0][0].xyxy
iadd r2.xyzw, r0.xxxx, l(8, 9, 10, 11)
store_uav_typed U0[0].xyzw, r2.xxxx, CB0[0][0].xyxy
store_uav_typed U0[0].xyzw, r2.yyyy, CB0[0][0].xyxy
store_uav_typed U0[0].xyzw, r2.zzzz, CB0[0][0].xyxy
store_uav_typed U0[0].xyzw, r2.wwww, CB0[0][0].xyxy
iadd r0.yzw, r0.xxxx, l(0, 12, 13, 14)
store_uav_typed U0[0].xyzw, r0.yyyy, CB0[0][0].xyxy
store_uav_typed U0[0].xyzw, r0.zzzz, CB0[0][0].xyxy
store_uav_typed U0[0].xyzw, r0.wwww, CB0[0][0].xyxy
store_uav_typed U0[0].xyzw, r1.wwww, CB0[0][0].xyxy
ret 
// Approximately 48 instruction slots used
