//
// Generated by Microsoft (R) HLSL Shader Compiler 10.1
//
//
// Buffer Definitions: 
//
// cbuffer XeEdramLoadStoreConstants
// {
//
//   uint xe_edram_rt_color_depth_offset;// Offset:    0 Size:     4
//   uint xe_edram_rt_color_depth_pitch;// Offset:    4 Size:     4
//   uint xe_edram_rt_stencil_offset;   // Offset:    8 Size:     4 [unused]
//   uint xe_edram_rt_stencil_pitch;    // Offset:   12 Size:     4 [unused]
//   uint xe_edram_base_samples_2x_depth_pitch;// Offset:   16 Size:     4
//
// }
//
//
// Resource Bindings:
//
// Name                                 Type  Format         Dim      ID      HLSL Bind  Count
// ------------------------------ ---------- ------- ----------- ------- -------------- ------
// xe_edram_load_store_source        texture    byte         r/o      T0             t0      1 
// xe_edram_load_store_dest              UAV    byte         r/w      U0             u0      1 
// XeEdramLoadStoreConstants         cbuffer      NA          NA     CB0            cb0      1 
//
//
//
// Input signature:
//
// Name                 Index   Mask Register SysValue  Format   Used
// -------------------- ----- ------ -------- -------- ------- ------
// no Input
//
// Output signature:
//
// Name                 Index   Mask Register SysValue  Format   Used
// -------------------- ----- ------ -------- -------- ------- ------
// no Output
cs_5_1
dcl_globalFlags refactoringAllowed
dcl_constantbuffer CB0[0:0][2], immediateIndexed, space=0
dcl_resource_raw T0[0:0], space=0
dcl_uav_raw U0[0:0], space=0
dcl_input vThreadGroupID.xy
dcl_input vThreadIDInGroup.xy
dcl_input vThreadID.xy
dcl_temps 5
dcl_thread_group 40, 16, 1
ishl r0.x, vThreadID.x, l(4)
imad r0.x, vThreadID.y, CB0[0][0].y, r0.x
iadd r0.x, r0.x, CB0[0][0].x
ld_raw r0.xyzw, r0.x, T0[0].xyzw
ushr r1.xyzw, r0.xyzw, l(16, 16, 16, 16)
f16tof32 r2.yw, r0.xxxy
f16tof32 r2.xz, r1.yyxy
uge r3.xyz, l(0x7fffffff, 0x7fffffff, 0x7fffffff, 0), r2.yzwy
and r2.yzw, r2.yyzw, r3.xxyz
umin r2.yzw, r2.yyzw, l(0, 0x41ff0000, 0x41ff0000, 0x41ff0000)
bfi r3.xyz, l(23, 23, 23, 0), l(0, 0, 0, 0), r2.yzwy, l(0x00800000, 0x00800000, 0x00800000, 0)
ushr r4.xyz, r2.yzwy, l(23, 23, 23, 0)
iadd r4.xyz, -r4.xyzx, l(125, 125, 125, 0)
umin r4.xyz, r4.xyzx, l(24, 24, 24, 0)
ushr r3.xyz, r3.xyzx, r4.xyzx
ult r4.xyz, r2.yzwy, l(0x3e800000, 0x3e800000, 0x3e800000, 0)
iadd r2.yzw, r2.yyzw, l(0, 0xc2000000, 0xc2000000, 0xc2000000)
movc r2.yzw, r4.xxyz, r3.xxyz, r2.yyzw
iadd r3.xyz, r2.yzwy, l(0x00007fff, 0x00007fff, 0x00007fff, 0)
ubfe r2.yzw, l(0, 1, 1, 1), l(0, 16, 16, 16), r2.yyzw
iadd r2.yzw, r2.yyzw, r3.xxyz
ubfe r2.yzw, l(0, 10, 10, 10), l(0, 16, 16, 16), r2.yyzw
imad r0.x, r2.z, l(1024), r2.y
imad r0.x, r2.w, l(0x00100000), r0.x
mov_sat r2.x, r2.x
mad r0.y, r2.x, l(3.000000), l(0.500000)
ftou r0.y, r0.y
imad r0.x, r0.y, l(0x40000000), r0.x
f16tof32 r2.yw, r0.zzzw
f16tof32 r2.xz, r1.wwzw
uge r1.xyz, l(0x7fffffff, 0x7fffffff, 0x7fffffff, 0), r2.yzwy
and r1.xyz, r2.yzwy, r1.xyzx
umin r1.xyz, r1.xyzx, l(0x41ff0000, 0x41ff0000, 0x41ff0000, 0)
bfi r2.yzw, l(0, 23, 23, 23), l(0, 0, 0, 0), r1.xxyz, l(0, 0x00800000, 0x00800000, 0x00800000)
ushr r3.xyz, r1.xyzx, l(23, 23, 23, 0)
iadd r3.xyz, -r3.xyzx, l(125, 125, 125, 0)
umin r3.xyz, r3.xyzx, l(24, 24, 24, 0)
ushr r2.yzw, r2.yyzw, r3.xxyz
ult r3.xyz, r1.xyzx, l(0x3e800000, 0x3e800000, 0x3e800000, 0)
iadd r1.xyz, r1.xyzx, l(0xc2000000, 0xc2000000, 0xc2000000, 0)
movc r1.xyz, r3.xyzx, r2.yzwy, r1.xyzx
iadd r2.yzw, r1.xxyz, l(0, 0x00007fff, 0x00007fff, 0x00007fff)
ubfe r1.xyz, l(1, 1, 1, 0), l(16, 16, 16, 0), r1.xyzx
iadd r1.xyz, r1.xyzx, r2.yzwy
ubfe r1.xyz, l(10, 10, 10, 0), l(16, 16, 16, 0), r1.xyzx
imad r0.z, r1.y, l(1024), r1.x
imad r0.z, r1.z, l(0x00100000), r0.z
mov_sat r2.x, r2.x
mad r0.w, r2.x, l(3.000000), l(0.500000)
ftou r0.w, r0.w
imad r0.y, r0.w, l(0x40000000), r0.z
ishl r0.z, vThreadIDInGroup.x, l(1)
and r1.xy, CB0[0][1].xxxx, l(0x00008000, 2047, 0, 0)
if_nz r1.x
  ult r0.w, vThreadIDInGroup.x, l(20)
  and r0.w, r0.w, l(40)
  uge r1.x, vThreadIDInGroup.x, l(20)
  and r1.x, r1.x, l(-40)
  iadd r0.w, r0.w, r1.x
  iadd r0.z, r0.w, r0.z
endif 
ushr r0.w, CB0[0][1].x, l(16)
imad r0.w, vThreadGroupID.y, r0.w, r1.y
iadd r0.w, r0.w, vThreadGroupID.x
imul null, r1.x, vThreadIDInGroup.y, l(320)
imad r0.w, r0.w, l(5120), r1.x
ishl r0.z, r0.z, l(2)
iadd r0.z, r0.z, r0.w
ubfe r0.w, l(1), l(13), CB0[0][1].x
ishl r0.w, r0.w, l(1)
ishl r0.z, r0.z, r0.w
store_raw U0[0].xy, r0.z, r0.xyxx
ret 
// Approximately 73 instruction slots used
