//
// Generated by Microsoft (R) HLSL Shader Compiler 10.1
//
//
// Buffer Definitions: 
//
// cbuffer XeEdramLoadStoreConstants
// {
//
//   uint xe_edram_rt_color_depth_offset;// Offset:    0 Size:     4
//   uint xe_edram_rt_color_depth_pitch;// Offset:    4 Size:     4
//   uint xe_edram_rt_stencil_offset;   // Offset:    8 Size:     4
//   uint xe_edram_rt_stencil_pitch;    // Offset:   12 Size:     4
//   uint xe_edram_base_samples_2x_depth_pitch;// Offset:   16 Size:     4
//
// }
//
//
// Resource Bindings:
//
// Name                                 Type  Format         Dim      ID      HLSL Bind  Count
// ------------------------------ ---------- ------- ----------- ------- -------------- ------
// xe_edram_load_store_source        texture    byte         r/o      T0             t0      1 
// xe_edram_load_store_dest              UAV    byte         r/w      U0             u0      1 
// XeEdramLoadStoreConstants         cbuffer      NA          NA     CB0            cb0      1 
//
//
//
// Input signature:
//
// Name                 Index   Mask Register SysValue  Format   Used
// -------------------- ----- ------ -------- -------- ------- ------
// no Input
//
// Output signature:
//
// Name                 Index   Mask Register SysValue  Format   Used
// -------------------- ----- ------ -------- -------- ------- ------
// no Output
cs_5_1
dcl_globalFlags refactoringAllowed
dcl_constantbuffer CB0[0:0][2], immediateIndexed, space=0
dcl_resource_raw T0[0:0], space=0
dcl_uav_raw U0[0:0], space=0
dcl_input vThreadGroupID.xy
dcl_input vThreadIDInGroup.xy
dcl_input vThreadID.xy
dcl_temps 7
dcl_thread_group 20, 16, 1
ishl r0.x, vThreadIDInGroup.x, l(2)
and r0.yz, CB0[0][1].xxxx, l(0, 0x00008000, 2047, 0)
if_nz r0.y
  ult r0.y, vThreadIDInGroup.x, l(10)
  uge r0.w, vThreadIDInGroup.x, l(10)
  and r0.yw, r0.yyyw, l(0, 40, 0, -40)
  iadd r0.y, r0.w, r0.y
  iadd r0.x, r0.y, r0.x
endif 
ushr r0.y, CB0[0][1].x, l(16)
imad r0.y, vThreadGroupID.y, r0.y, r0.z
iadd r0.y, r0.y, vThreadGroupID.x
imul null, r0.z, vThreadIDInGroup.y, l(320)
imad r0.y, r0.y, l(5120), r0.z
ishl r0.x, r0.x, l(2)
iadd r0.x, r0.x, r0.y
ubfe r0.y, l(1), l(13), CB0[0][1].x
ishl r0.y, r0.y, l(1)
ishl r0.x, r0.x, r0.y
ld_raw r1.xyzw, r0.x, T0[0].xyzw
ushr r2.xyzw, r1.xyzw, l(8, 8, 8, 8)
iadd r0.x, r0.x, l(0x00a00000)
ld_raw r0.xyzw, r0.x, T0[0].xyzw
ubfe r3.xyzw, l(20, 20, 20, 20), l(8, 8, 8, 8), r1.xyzw
ushr r4.xyzw, r2.xyzw, l(20, 20, 20, 20)
firstbit_hi r5.xyzw, r3.xyzw
iadd r5.xyzw, r5.xyzw, l(-11, -11, -11, -11)
movc r5.xyzw, r3.xyzw, r5.xyzw, l(21,21,21,21)
iadd r6.xyzw, -r5.xyzw, l(1, 1, 1, 1)
movc r6.xyzw, r4.xyzw, r4.xyzw, r6.xyzw
ishl r5.xyzw, r3.xyzw, r5.xyzw
and r5.xyzw, r5.xyzw, l(0x000fffff, 0x000fffff, 0x000fffff, 0x000fffff)
movc r3.xyzw, r4.xyzw, r3.xyzw, r5.xyzw
ishl r4.xyzw, r6.xyzw, l(23, 23, 23, 23)
iadd r4.xyzw, r4.xyzw, l(0x38000000, 0x38000000, 0x38000000, 0x38000000)
ishl r3.xyzw, r3.xyzw, l(3, 3, 3, 3)
iadd r3.xyzw, r4.xyzw, r3.xyzw
movc r3.xyzw, r2.xyzw, r3.xyzw, l(0,0,0,0)
iadd r4.xyzw, r0.xyzw, -r3.xyzw
uge r5.xyzw, l(0x7fffffff, 0x7fffffff, 0x7fffffff, 0x7fffffff), r0.xyzw
and r0.xyzw, r0.xyzw, r5.xyzw
umin r0.xyzw, r0.xyzw, l(0x3ffffff8, 0x3ffffff8, 0x3ffffff8, 0x3ffffff8)
bfi r5.xyzw, l(23, 23, 23, 23), l(0, 0, 0, 0), r0.xyzw, l(0x00800000, 0x00800000, 0x00800000, 0x00800000)
ushr r6.xyzw, r0.xyzw, l(23, 23, 23, 23)
iadd r6.xyzw, -r6.xyzw, l(113, 113, 113, 113)
umin r6.xyzw, r6.xyzw, l(24, 24, 24, 24)
ushr r5.xyzw, r5.xyzw, r6.xyzw
ult r6.xyzw, r0.xyzw, l(0x38800000, 0x38800000, 0x38800000, 0x38800000)
iadd r0.xyzw, r0.xyzw, l(0xc8000000, 0xc8000000, 0xc8000000, 0xc8000000)
movc r0.xyzw, r6.xyzw, r5.xyzw, r0.xyzw
iadd r5.xyzw, r0.xyzw, l(3, 3, 3, 3)
ubfe r0.xyzw, l(1, 1, 1, 1), l(3, 3, 3, 3), r0.xyzw
iadd r0.xyzw, r0.xyzw, r5.xyzw
ubfe r0.xyzw, l(24, 24, 24, 24), l(3, 3, 3, 3), r0.xyzw
ieq r0.xyzw, r2.xyzw, r0.xyzw
and r0.xyzw, r0.xyzw, l(1, 1, 1, 1)
imad r0.xyzw, r4.xyzw, r0.xyzw, r3.xyzw
ishl r2.xy, vThreadID.xxxx, l(4, 2, 0, 0)
imad r2.xy, vThreadID.yyyy, CB0[0][0].ywyy, r2.xyxx
iadd r2.xy, r2.xyxx, CB0[0][0].xzxx
store_raw U0[0].xyzw, r2.x, r0.xyzw
and r0.x, r1.x, l(255)
bfi r0.yzw, l(0, 8, 8, 8), l(0, 8, 16, 24), r1.yyzw, l(0, 0, 0, 0)
iadd r0.xy, r0.zwzz, r0.xyxx
iadd r0.x, r0.y, r0.x
store_raw U0[0].x, r2.y, r0.x
ret 
// Approximately 67 instruction slots used
