//
// Generated by Microsoft (R) HLSL Shader Compiler 10.1
//
//
// Buffer Definitions: 
//
// cbuffer XeTextureLoadConstants
// {
//
//   uint xe_texture_load_is_tiled_3d_endian;// Offset:    0 Size:     4
//   uint xe_texture_load_guest_offset; // Offset:    4 Size:     4
//   uint xe_texture_load_guest_pitch_aligned;// Offset:    8 Size:     4
//   uint xe_texture_load_guest_z_stride_block_rows_aligned;// Offset:   12 Size:     4
//   uint3 xe_texture_load_size_blocks; // Offset:   16 Size:    12
//   uint xe_texture_load_host_offset;  // Offset:   28 Size:     4
//   uint xe_texture_load_host_pitch;   // Offset:   32 Size:     4
//   uint xe_texture_load_height_texels;// Offset:   36 Size:     4 [unused]
//
// }
//
//
// Resource Bindings:
//
// Name                                 Type  Format         Dim      ID      HLSL Bind  Count
// ------------------------------ ---------- ------- ----------- ------- -------------- ------
// xe_texture_load_source            texture   uint4         buf      T0             t0      1 
// xe_texture_load_dest                  UAV   uint4         buf      U0             u0      1 
// XeTextureLoadConstants            cbuffer      NA          NA     CB0            cb0      1 
//
//
//
// Input signature:
//
// Name                 Index   Mask Register SysValue  Format   Used
// -------------------- ----- ------ -------- -------- ------- ------
// no Input
//
// Output signature:
//
// Name                 Index   Mask Register SysValue  Format   Used
// -------------------- ----- ------ -------- -------- ------- ------
// no Output
cs_5_1
dcl_globalFlags refactoringAllowed
dcl_constantbuffer CB0[0:0][3], immediateIndexed, space=0
dcl_resource_buffer (uint,uint,uint,uint) T0[0:0], space=0
dcl_uav_typed_buffer (uint,uint,uint,uint) U0[0:0], space=0
dcl_input vThreadID.xyz
dcl_temps 4
dcl_thread_group 2, 32, 1
ishl r0.x, vThreadID.x, l(4)
mov r0.yz, vThreadID.yyzy
uge r1.xyz, r0.xyzx, CB0[0][1].xyzx
or r0.z, r1.y, r1.x
or r0.z, r1.z, r0.z
if_nz r0.z
  ret 
endif 
ishl r0.yz, r0.xxyx, l(0, 1, 1, 0)
ishl r0.w, CB0[0][1].y, l(1)
imad r0.z, vThreadID.z, r0.w, r0.z
imad r0.y, r0.z, CB0[0][2].x, r0.y
iadd r0.y, r0.y, CB0[0][1].w
ushr r0.z, CB0[0][2].x, l(4)
and r0.w, CB0[0][0].x, l(1)
if_nz r0.w
  and r1.x, CB0[0][0].x, l(2)
  if_nz r1.x
    ishr r1.xyz, vThreadID.yzyy, l(4, 2, 3, 0)
    ushr r2.xy, CB0[0][0].wzww, l(4, 5, 0, 0)
    imad r1.x, r1.y, r2.x, r1.x
    ibfe r1.w, l(27), l(1), vThreadID.x
    imad r1.x, r1.x, r2.y, r1.w
    ishl r1.w, vThreadID.y, l(8)
    ishr r1.w, r1.w, l(6)
    iadd r1.y, r1.y, r1.z
    and r1.z, r1.y, l(1)
    ishr r2.x, r0.x, l(3)
    bfi r1.y, l(1), l(1), r1.y, l(0)
    iadd r1.y, r1.y, r2.x
    bfi r1.y, l(2), l(1), r1.y, l(0)
    iadd r1.y, r1.y, r1.z
    and r1.zw, r1.wwww, l(0, 0, 16, 8)
    bfi r2.xy, l(22, 22, 0, 0), l(8, 11, 0, 0), r1.xxxx, l(0, 0, 0, 0)
    imad r1.xz, r1.zzzz, l(2, 0, 16, 0), r2.xxyx
    bfi r1.xz, l(5, 0, 5, 0), l(0, 0, 3, 0), r1.wwww, r1.xxzx
    bfi r1.xz, l(2, 0, 2, 0), l(6, 0, 9, 0), vThreadID.zzzz, r1.xxzx
    ubfe r1.w, l(3), l(6), r1.x
    and r2.x, r1.y, l(4)
    bfi r1.y, l(2), l(8), r1.y, l(0)
    imad r1.y, r1.w, l(32), r1.y
    imad r1.y, r2.x, l(4), r1.y
    bfi r1.xz, l(1, 0, 1, 0), l(4, 0, 7, 0), vThreadID.yyyy, r1.xxzx
    bfi r1.y, l(9), l(3), r1.y, r1.z
    bfi r1.x, l(6), l(0), r1.x, r1.y
  else 
    ibfe r1.y, l(27), l(1), vThreadID.x
    ishr r1.zw, vThreadID.yyyy, l(0, 0, 5, 2)
    ushr r2.x, CB0[0][0].z, l(5)
    imad r1.y, r1.z, r2.x, r1.y
    ishl r2.xy, vThreadID.yyyy, l(2, 7, 0, 0)
    ishl r1.z, r2.x, l(1)
    and r1.z, r1.z, l(96)
    bfi r2.z, l(25), l(7), r1.y, r1.z
    and r2.xy, r2.xyxx, l(8, 2048, 0, 0)
    iadd r2.z, r2.z, r2.x
    bfi r2.z, l(1), l(4), vThreadID.y, r2.z
    ishl r3.xy, r1.zzzz, l(3, 2, 0, 0)
    bfi r1.yz, l(0, 25, 25, 0), l(0, 10, 9, 0), r1.yyyy, r3.xxyx
    imad r1.yz, r2.xxxx, l(0, 8, 4, 0), r1.yyzy
    bfi r1.yz, l(0, 1, 1, 0), l(0, 7, 6, 0), vThreadID.yyyy, r1.yyzy
    bfi r1.y, l(12), l(0), r2.y, r1.y
    and r1.z, r1.z, l(1792)
    iadd r1.y, r1.y, r1.z
    and r1.z, r1.w, l(2)
    ishr r1.w, r0.x, l(3)
    iadd r1.z, r1.w, r1.z
    bfi r1.z, l(2), l(6), r1.z, l(0)
    iadd r1.y, r1.y, r1.z
    bfi r1.x, l(6), l(0), r2.z, r1.y
  endif 
else 
  imad r1.y, vThreadID.z, CB0[0][0].w, vThreadID.y
  imad r1.x, r1.y, CB0[0][0].z, r0.x
endif 
iadd r0.x, r1.x, CB0[0][0].y
ushr r0.xy, r0.xyxx, l(2, 4, 0, 0)
ld r1.xyzw, r0.xxxx, T0[0].xyzw
iadd r2.x, r0.x, l(1)
ld r2.xyzw, r2.xxxx, T0[0].ywxz
mov r3.xy, r1.ywyy
mov r3.zw, r2.xxxy
mov r2.xy, r1.xzxx
bfi r1.xyzw, l(16, 16, 16, 16), l(16, 16, 16, 16), r3.xyzw, r2.xyzw
store_uav_typed U0[0].xyzw, r0.yyyy, r1.xyzw
iadd r1.x, r0.z, r0.y
ushr r2.xyzw, r2.xyzw, l(16, 16, 16, 16)
bfi r2.xyzw, l(16, 16, 16, 16), l(0, 0, 0, 0), r2.xyzw, r3.xyzw
store_uav_typed U0[0].xyzw, r1.xxxx, r2.xyzw
movc r0.w, r0.w, l(16), l(2)
iadd r0.x, r0.w, r0.x
ld r1.xyzw, r0.xxxx, T0[0].xyzw
iadd r0.xy, r0.xyxx, l(1, 1, 0, 0)
ld r2.xyzw, r0.xxxx, T0[0].ywxz
mov r3.xy, r1.ywyy
mov r3.zw, r2.xxxy
mov r2.xy, r1.xzxx
bfi r1.xyzw, l(16, 16, 16, 16), l(16, 16, 16, 16), r3.xyzw, r2.xyzw
store_uav_typed U0[0].xyzw, r0.yyyy, r1.xyzw
iadd r0.x, r0.z, r0.y
ushr r1.xyzw, r2.xyzw, l(16, 16, 16, 16)
bfi r1.xyzw, l(16, 16, 16, 16), l(0, 0, 0, 0), r1.xyzw, r3.xyzw
store_uav_typed U0[0].xyzw, r0.xxxx, r1.xyzw
ret 
// Approximately 104 instruction slots used
