//
// Generated by Microsoft (R) HLSL Shader Compiler 10.1
//
//
// Buffer Definitions: 
//
// cbuffer XeResolveConstants
// {
//
//   uint xe_resolve_edram_info;        // Offset:    0 Size:     4
//   uint xe_resolve_address_info;      // Offset:    4 Size:     4
//   uint xe_resolve_dest_info;         // Offset:    8 Size:     4
//   uint xe_resolve_dest_pitch_aligned;// Offset:   12 Size:     4
//
// }
//
//
// Resource Bindings:
//
// Name                                 Type  Format         Dim      ID      HLSL Bind  Count
// ------------------------------ ---------- ------- ----------- ------- -------------- ------
// xe_resolve_source                 texture   uint2         buf      T0             t0      1 
// xe_resolve_dest                       UAV   uint2         buf      U0             u0      1 
// XeResolveConstants                cbuffer      NA          NA     CB0            cb0      1 
//
//
//
// Input signature:
//
// Name                 Index   Mask Register SysValue  Format   Used
// -------------------- ----- ------ -------- -------- ------- ------
// no Input
//
// Output signature:
//
// Name                 Index   Mask Register SysValue  Format   Used
// -------------------- ----- ------ -------- -------- ------- ------
// no Output
cs_5_1
dcl_globalFlags refactoringAllowed
dcl_constantbuffer CB0[0:0][1], immediateIndexed, space=0
dcl_resource_buffer (uint,uint,uint,uint) T0[0:0], space=0
dcl_uav_typed_buffer (uint,uint,uint,uint) U0[0:0], space=0
dcl_input vThreadID.xy
dcl_temps 10
dcl_thread_group 8, 8, 1
ishl r0.xw, vThreadID.xxxx, l(1, 0, 0, 1)
ushr r1.x, CB0[0][0].y, l(7)
bfi r1.x, l(11), l(3), r1.x, l(0)
uge r1.x, r0.w, r1.x
if_nz r1.x
  ret 
endif 
ushr r1.xy, CB0[0][0].yyyy, l(5, 29, 0, 0)
mov r1.z, CB0[0][0].y
bfi r2.xy, l(5, 2, 0, 0), l(3, 3, 0, 0), r1.zxzz, l(0, 0, 0, 0)
mov r0.yz, vThreadID.yyyy
iadd r2.xy, r0.wzww, r2.xyxx
ubfe r1.w, l(12), l(13), CB0[0][0].x
and r3.xyzw, CB0[0][0].xxzx, l(1023, 4096, 0x01000000, 0x40000000)
uge r2.z, l(3), r1.y
if_nz r2.z
  mov r4.y, r1.y
else 
  ieq r2.z, r1.y, l(5)
  if_nz r2.z
    mov r4.y, l(2)
  else 
    mov r4.y, l(0)
  endif 
endif 
ishl r2.xy, r2.xyxx, l(1, 1, 0, 0)
ushr r4.x, r4.y, l(1)
bfi r2.xy, l(2, 1, 0, 0), l(0, 0, 0, 0), r4.xyxx, r2.xyxx
udiv r2.zw, null, r2.xxxy, l(0, 0, 80, 16)
imad r3.x, r2.w, r3.x, r2.z
iadd r1.w, r1.w, r3.x
imad r2.xy, -r2.zwzz, l(80, 16, 0, 0), r2.xyxx
if_nz r3.y
  uge r2.z, r2.x, l(40)
  movc r2.z, r2.z, l(-40), l(40)
  iadd r2.x, r2.z, r2.x
endif 
imad r2.x, r2.y, l(80), r2.x
imad r1.w, r1.w, l(1280), r2.x
imul null, r1.w, r1.w, l(9)
ushr r1.w, r1.w, l(1)
ine r2.xy, r1.yyyy, l(2, 3, 0, 0)
and r1.y, r2.y, r2.x
if_nz r1.y
  ld r2.yz, r1.wwww, T0[0].wxyz
  iadd r1.y, r1.w, l(1)
  ld r2.xw, r1.yyyy, T0[0].yzwx
  iadd r4.xyzw, r1.wwww, l(2, 3, 4, 9)
  ld r5.xy, r4.xxxx, T0[0].xyzw
  ld r5.zw, r4.yyyy, T0[0].zwxy
  ld r6.x, r4.zzzz, T0[0].xyzw
  ld r6.yz, r4.wwww, T0[0].zxyw
  iadd r4.xyzw, r1.wwww, l(10, 11, 12, 13)
  ld r3.xy, r4.xxxx, T0[0].xyzw
  ld r7.yz, r4.yyyy, T0[0].zxyw
  ld r4.xy, r4.zzzz, T0[0].xyzw
  ld r4.w, r4.wwww, T0[0].zwyx
  mov r6.w, r3.x
  mov r7.x, r3.y
  mov r7.w, r4.x
  mov r4.zw, r4.yyyw
else 
  iadd r8.xyzw, r1.wwww, l(4, 5, 6, 7)
  ld r2.y, r8.xxxx, T0[0].wyxz
  ld r2.zw, r8.yyyy, T0[0].wzxy
  ld r8.xy, r8.zzzz, T0[0].xyzw
  ld r5.yz, r8.wwww, T0[0].zxyw
  iadd r9.xyzw, r1.wwww, l(8, 13, 14, 15)
  ld r8.zw, r9.xxxx, T0[0].zwxy
  ld r6.y, r9.yyyy, T0[0].xyzw
  ld r6.zw, r9.zzzz, T0[0].zwxy
  ld r7.xy, r9.wwww, T0[0].xyzw
  iadd r1.yw, r1.wwww, l(0, 16, 0, 17)
  ld r7.zw, r1.yyyy, T0[0].zwxy
  ld r4.zw, r1.wwww, T0[0].zwxy
  mov r2.x, r8.x
  mov r5.xw, r8.yyyz
  mov r6.x, r8.w
endif 
if_nz r3.z
  ubfe r1.y, l(4), l(25), CB0[0][0].x
  switch r1.y
    case l(0)
    case l(1)
    and r8.xyzw, r2.yzwx, l(0xff00ff00, 0xff00ff00, 0xff00ff00, 0xff00ff00)
    bfi r8.xyzw, l(8, 8, 8, 8), l(16, 16, 16, 16), r2.yzwx, r8.xyzw
    ubfe r9.xyzw, l(8, 8, 8, 8), l(16, 16, 16, 16), r2.yzwx
    iadd r2.xyzw, r8.wxyz, r9.wxyz
    and r8.xyzw, r5.xyzw, l(0xff00ff00, 0xff00ff00, 0xff00ff00, 0xff00ff00)
    bfi r8.xyzw, l(8, 8, 8, 8), l(16, 16, 16, 16), r5.xyzw, r8.xyzw
    ubfe r9.xyzw, l(8, 8, 8, 8), l(16, 16, 16, 16), r5.xyzw
    iadd r5.xyzw, r8.xyzw, r9.xyzw
    and r8.xyzw, r6.xyzw, l(0xff00ff00, 0xff00ff00, 0xff00ff00, 0xff00ff00)
    bfi r8.xyzw, l(8, 8, 8, 8), l(16, 16, 16, 16), r6.xyzw, r8.xyzw
    ubfe r9.xyzw, l(8, 8, 8, 8), l(16, 16, 16, 16), r6.xyzw
    iadd r6.xyzw, r8.xyzw, r9.xyzw
    and r8.xyzw, r7.xyzw, l(0xff00ff00, 0xff00ff00, 0xff00ff00, 0xff00ff00)
    bfi r8.xyzw, l(8, 8, 8, 8), l(16, 16, 16, 16), r7.xyzw, r8.xyzw
    ubfe r9.xyzw, l(8, 8, 8, 8), l(16, 16, 16, 16), r7.xyzw
    iadd r7.xyzw, r8.xyzw, r9.xyzw
    and r1.yw, r4.zzzw, l(0, 0xff00ff00, 0, 0xff00ff00)
    bfi r1.yw, l(0, 8, 0, 8), l(0, 16, 0, 16), r4.zzzw, r1.yyyw
    ubfe r3.xy, l(8, 8, 0, 0), l(16, 16, 0, 0), r4.zwzz
    iadd r4.zw, r1.yyyw, r3.xxxy
    break 
    case l(2)
    case l(3)
    case l(10)
    case l(12)
    and r8.xyzw, r2.yzwx, l(0xc00ffc00, 0xc00ffc00, 0xc00ffc00, 0xc00ffc00)
    bfi r8.xyzw, l(10, 10, 10, 10), l(20, 20, 20, 20), r2.yzwx, r8.xyzw
    ubfe r9.xyzw, l(10, 10, 10, 10), l(20, 20, 20, 20), r2.yzwx
    iadd r2.xyzw, r8.wxyz, r9.wxyz
    and r8.xyzw, r5.xyzw, l(0xc00ffc00, 0xc00ffc00, 0xc00ffc00, 0xc00ffc00)
    bfi r8.xyzw, l(10, 10, 10, 10), l(20, 20, 20, 20), r5.xyzw, r8.xyzw
    ubfe r9.xyzw, l(10, 10, 10, 10), l(20, 20, 20, 20), r5.xyzw
    iadd r5.xyzw, r8.xyzw, r9.xyzw
    and r8.xyzw, r6.xyzw, l(0xc00ffc00, 0xc00ffc00, 0xc00ffc00, 0xc00ffc00)
    bfi r8.xyzw, l(10, 10, 10, 10), l(20, 20, 20, 20), r6.xyzw, r8.xyzw
    ubfe r9.xyzw, l(10, 10, 10, 10), l(20, 20, 20, 20), r6.xyzw
    iadd r6.xyzw, r8.xyzw, r9.xyzw
    and r8.xyzw, r7.xyzw, l(0xc00ffc00, 0xc00ffc00, 0xc00ffc00, 0xc00ffc00)
    bfi r8.xyzw, l(10, 10, 10, 10), l(20, 20, 20, 20), r7.xyzw, r8.xyzw
    ubfe r9.xyzw, l(10, 10, 10, 10), l(20, 20, 20, 20), r7.xyzw
    iadd r7.xyzw, r8.xyzw, r9.xyzw
    and r1.yw, r4.zzzw, l(0, 0xc00ffc00, 0, 0xc00ffc00)
    bfi r1.yw, l(0, 10, 0, 10), l(0, 20, 0, 20), r4.zzzw, r1.yyyw
    ubfe r3.xy, l(10, 10, 0, 0), l(20, 20, 0, 0), r4.zwzz
    iadd r4.zw, r1.yyyw, r3.xxxy
    break 
    default 
    break 
  endswitch 
endif 
if_nz r3.w
  if_z r0.w
    mov r2.y, r2.z
    mov r5.z, r5.x
    mov r1.y, r5.w
  else 
    mov r1.y, r5.z
    mov r5.z, r2.x
  endif 
  if_z vThreadID.y
    mov r2.yzw, r5.zzxy
    mov r6.yzw, r7.xxyz
  endif 
  mov r2.x, r5.z
  mov r5.z, r1.y
endif 
bfi r1.xyzw, l(2, 2, 2, 2), l(3, 3, 3, 3), r1.zxxz, l(0, 0, 0, 0)
iadd r0.xyzw, r0.xyzw, r1.xyzw
bfi r1.x, l(10), l(5), CB0[0][0].w, l(0)
and r1.yz, CB0[0][0].zzzz, l(0, 7, 8, 0)
if_nz r1.z
  ubfe r1.z, l(3), l(4), CB0[0][0].z
  ushr r1.w, CB0[0][0].w, l(10)
  ishl r1.w, r1.w, l(5)
  ishr r3.xyzw, r0.zwzw, l(4, 5, 3, 3)
  ishr r4.x, r1.z, l(2)
  ushr r1.w, r1.w, l(4)
  and r1.w, r1.w, l(0x00007ffe)
  imad r1.w, r4.x, r1.w, r3.x
  ushr r3.x, r1.x, l(5)
  imad r1.w, r1.w, r3.x, r3.y
  ishl r3.x, r0.z, l(10)
  and r3.x, r3.x, l(6144)
  bfi r3.x, l(3), l(8), r0.w, r3.x
  ishr r3.x, r3.x, l(6)
  iadd r3.y, r3.z, r4.x
  bfi r3.z, l(1), l(1), r3.y, l(0)
  iadd r3.z, r3.z, r3.w
  bfi r3.z, l(2), l(1), r3.z, l(0)
  bfi r3.y, l(1), l(0), r3.y, r3.z
  and r3.z, r3.x, l(112)
  bfi r4.xy, l(20, 20, 0, 0), l(10, 13, 0, 0), r1.wwww, l(0, 0, 0, 0)
  imad r3.zw, r3.zzzz, l(0, 0, 2, 16), r4.xxxy
  bfi r3.xz, l(4, 0, 4, 0), l(0, 0, 3, 0), r3.xxxx, r3.zzwz
  bfi r1.zw, l(0, 0, 2, 2), l(0, 0, 8, 11), r1.zzzz, r3.xxxz
  ubfe r3.x, l(3), l(6), r1.z
  and r3.z, r3.y, l(6)
  bfi r3.y, l(1), l(8), r3.y, l(0)
  imad r3.x, r3.x, l(32), r3.y
  imad r3.x, r3.z, l(4), r3.x
  bfi r1.zw, l(0, 0, 1, 1), l(0, 0, 4, 7), r0.zzzz, r1.zzzw
  bfi r1.w, l(9), l(3), r3.x, r1.w
  bfi r1.z, l(6), l(0), r1.z, r1.w
else 
  ishr r3.xyzw, r0.xyzw, l(5, 5, 2, 3)
  ushr r0.x, r1.x, l(5)
  imad r0.x, r3.y, r0.x, r3.x
  ishl r1.xw, r0.zzzz, l(4, 0, 0, 7)
  and r1.xw, r1.xxxw, l(224, 0, 0, 2048)
  bfi r0.y, l(3), l(2), r0.w, r1.x
  ishl r1.x, r1.x, l(1)
  bfi r0.w, l(3), l(3), r0.w, r1.x
  and r0.w, r0.w, l(480)
  bfi r1.x, l(23), l(9), r0.x, r0.w
  bfi r1.x, l(4), l(0), r0.y, r1.x
  bfi r1.x, l(1), l(4), r0.z, r1.x
  ishl r3.xy, r0.wwww, l(3, 2, 0, 0)
  bfi r0.xw, l(23, 0, 0, 23), l(12, 0, 0, 11), r0.xxxx, r3.xxxy
  bfi r0.xy, l(4, 4, 0, 0), l(3, 2, 0, 0), r0.yyyy, r0.xwxx
  bfi r0.xy, l(1, 1, 0, 0), l(7, 6, 0, 0), r0.zzzz, r0.xyxx
  bfi r0.x, l(12), l(0), r1.w, r0.x
  and r0.y, r0.y, l(1792)
  iadd r0.x, r0.x, r0.y
  and r0.y, r3.z, l(2)
  iadd r0.y, r3.w, r0.y
  bfi r0.y, l(2), l(6), r0.y, l(0)
  iadd r0.x, r0.x, r0.y
  bfi r1.z, l(6), l(0), r1.x, r0.x
endif 
imul null, r0.x, r1.z, l(9)
ushr r0.x, r0.x, l(3)
ieq r0.yzw, r1.yyyy, l(0, 1, 2, 3)
or r0.yz, r0.zzwz, r0.yyzy
if_nz r0.y
  ishl r1.xyzw, r2.yzwx, l(8, 8, 8, 8)
  and r1.xyzw, r1.xyzw, l(0xff00ff00, 0xff00ff00, 0xff00ff00, 0xff00ff00)
  ushr r3.xyzw, r2.yzwx, l(8, 8, 8, 8)
  and r3.xyzw, r3.xyzw, l(0x00ff00ff, 0x00ff00ff, 0x00ff00ff, 0x00ff00ff)
  iadd r2.xyzw, r1.wxyz, r3.wxyz
endif 
if_nz r0.z
  ushr r1.xyzw, r2.yzwx, l(16, 16, 16, 16)
  bfi r2.xyzw, l(16, 16, 16, 16), l(16, 16, 16, 16), r2.xyzw, r1.wxyz
endif 
if_nz r0.y
  ishl r1.xyzw, r5.xyzw, l(8, 8, 8, 8)
  and r1.xyzw, r1.xyzw, l(0xff00ff00, 0xff00ff00, 0xff00ff00, 0xff00ff00)
  ushr r3.xyzw, r5.xyzw, l(8, 8, 8, 8)
  and r3.xyzw, r3.xyzw, l(0x00ff00ff, 0x00ff00ff, 0x00ff00ff, 0x00ff00ff)
  iadd r5.xyzw, r1.xyzw, r3.xyzw
endif 
if_nz r0.z
  ushr r1.xyzw, r5.xyzw, l(16, 16, 16, 16)
  bfi r5.xyzw, l(16, 16, 16, 16), l(16, 16, 16, 16), r5.xyzw, r1.xyzw
endif 
if_nz r0.y
  ishl r1.xyzw, r6.xyzw, l(8, 8, 8, 8)
  and r1.xyzw, r1.xyzw, l(0xff00ff00, 0xff00ff00, 0xff00ff00, 0xff00ff00)
  ushr r3.xyzw, r6.xyzw, l(8, 8, 8, 8)
  and r3.xyzw, r3.xyzw, l(0x00ff00ff, 0x00ff00ff, 0x00ff00ff, 0x00ff00ff)
  iadd r6.xyzw, r1.xyzw, r3.xyzw
endif 
if_nz r0.z
  ushr r1.xyzw, r6.xyzw, l(16, 16, 16, 16)
  bfi r6.xyzw, l(16, 16, 16, 16), l(16, 16, 16, 16), r6.xyzw, r1.xyzw
endif 
if_nz r0.y
  ishl r1.xyzw, r7.xyzw, l(8, 8, 8, 8)
  and r1.xyzw, r1.xyzw, l(0xff00ff00, 0xff00ff00, 0xff00ff00, 0xff00ff00)
  ushr r3.xyzw, r7.xyzw, l(8, 8, 8, 8)
  and r3.xyzw, r3.xyzw, l(0x00ff00ff, 0x00ff00ff, 0x00ff00ff, 0x00ff00ff)
  iadd r7.xyzw, r1.xyzw, r3.xyzw
endif 
if_nz r0.z
  ushr r1.xyzw, r7.xyzw, l(16, 16, 16, 16)
  bfi r7.xyzw, l(16, 16, 16, 16), l(16, 16, 16, 16), r7.xyzw, r1.xyzw
endif 
if_nz r0.y
  ishl r0.yw, r4.zzzw, l(0, 8, 0, 8)
  and r0.yw, r0.yyyw, l(0, 0xff00ff00, 0, 0xff00ff00)
  ushr r1.xy, r4.zwzz, l(8, 8, 0, 0)
  and r1.xy, r1.xyxx, l(0x00ff00ff, 0x00ff00ff, 0, 0)
  iadd r4.zw, r0.yyyw, r1.xxxy
endif 
if_nz r0.z
  ushr r0.yz, r4.zzwz, l(0, 16, 16, 0)
  bfi r4.zw, l(0, 0, 16, 16), l(0, 0, 16, 16), r4.zzzw, r0.yyyz
endif 
store_uav_typed U0[0].xyzw, r0.xxxx, r2.yzyy
iadd r1.xyzw, r0.xxxx, l(1, 2, 3, 4)
store_uav_typed U0[0].xyzw, r1.xxxx, r2.wxww
store_uav_typed U0[0].xyzw, r1.yyyy, r5.xyxx
store_uav_typed U0[0].xyzw, r1.zzzz, r5.zwzz
store_uav_typed U0[0].xyzw, r1.wwww, r6.xyxx
iadd r1.xyzw, r0.xxxx, l(5, 6, 7, 8)
store_uav_typed U0[0].xyzw, r1.xxxx, r6.zwzz
store_uav_typed U0[0].xyzw, r1.yyyy, r7.xyxx
store_uav_typed U0[0].xyzw, r1.zzzz, r7.zwzz
store_uav_typed U0[0].xyzw, r1.wwww, r4.zwzz
ret 
// Approximately 284 instruction slots used
