//
// Generated by Microsoft (R) HLSL Shader Compiler 10.1
//
//
// Buffer Definitions: 
//
// cbuffer XeResolveConstants
// {
//
//   uint xe_resolve_edram_info;        // Offset:    0 Size:     4
//   uint xe_resolve_address_info;      // Offset:    4 Size:     4
//   uint xe_resolve_dest_info;         // Offset:    8 Size:     4
//   uint xe_resolve_dest_pitch_aligned;// Offset:   12 Size:     4
//   uint xe_resolve_dest_base;         // Offset:   16 Size:     4
//
// }
//
//
// Resource Bindings:
//
// Name                                 Type  Format         Dim      ID      HLSL Bind  Count
// ------------------------------ ---------- ------- ----------- ------- -------------- ------
// xe_resolve_source                 texture   uint4         buf      T0             t0      1 
// xe_resolve_dest                       UAV   uint4         buf      U0             u0      1 
// XeResolveConstants                cbuffer      NA          NA     CB0            cb0      1 
//
//
//
// Input signature:
//
// Name                 Index   Mask Register SysValue  Format   Used
// -------------------- ----- ------ -------- -------- ------- ------
// no Input
//
// Output signature:
//
// Name                 Index   Mask Register SysValue  Format   Used
// -------------------- ----- ------ -------- -------- ------- ------
// no Output
cs_5_1
dcl_globalFlags refactoringAllowed
dcl_constantbuffer CB0[0:0][2], immediateIndexed, space=0
dcl_resource_buffer (uint,uint,uint,uint) T0[0:0], space=0
dcl_uav_typed_buffer (uint,uint,uint,uint) U0[0:0], space=0
dcl_input vThreadID.xy
dcl_temps 7
dcl_thread_group 8, 8, 1
ishl r0.xw, vThreadID.xxxx, l(3, 0, 0, 3)
ushr r1.x, CB0[0][0].y, l(7)
bfi r1.x, l(11), l(3), r1.x, l(0)
uge r1.x, r0.w, r1.x
if_nz r1.x
  ret 
endif 
ushr r1.xy, CB0[0][0].yyyy, l(5, 29, 0, 0)
mov r1.z, CB0[0][0].y
bfi r2.xy, l(5, 2, 0, 0), l(3, 3, 0, 0), r1.zxzz, l(0, 0, 0, 0)
mov r0.yz, vThreadID.yyyy
iadd r2.xy, r0.wzww, r2.xyxx
ubfe r2.zw, l(0, 0, 12, 2), l(0, 0, 13, 10), CB0[0][0].xxxx
and r3.xyzw, CB0[0][0].xxzz, l(1023, 4096, 0x01000000, 7)
uge r1.w, l(3), r1.y
if_nz r1.w
  mov r4.y, r1.y
else 
  ieq r1.w, r1.y, l(5)
  if_nz r1.w
    mov r4.y, l(2)
  else 
    mov r4.y, l(0)
  endif 
endif 
uge r1.yw, r2.wwww, l(0, 2, 0, 1)
and r1.yw, r1.yyyw, l(0, 1, 0, 1)
ishl r1.yw, r2.xxxy, r1.yyyw
ushr r4.x, r4.y, l(1)
and r2.xy, r4.xyxx, l(1, 1, 0, 0)
iadd r1.yw, r1.yyyw, r2.xxxy
udiv r2.xy, null, r1.ywyy, l(80, 16, 0, 0)
imad r2.w, r2.y, r3.x, r2.x
iadd r2.z, r2.w, r2.z
imad r1.yw, -r2.xxxy, l(0, 80, 0, 16), r1.yyyw
if_nz r3.y
  uge r2.x, r1.y, l(40)
  movc r2.x, r2.x, l(-40), l(40)
  iadd r1.y, r1.y, r2.x
endif 
imad r1.y, r1.w, l(80), r1.y
imad r1.y, r2.z, l(1280), r1.y
ushr r1.y, r1.y, l(2)
ld r2.xyzw, r1.yyyy, T0[0].xyzw
iadd r1.y, r1.y, l(1)
ld r4.xyzw, r1.yyyy, T0[0].xyzw
if_nz r3.z
  ubfe r1.y, l(4), l(25), CB0[0][0].x
  switch r1.y
    case l(0)
    case l(1)
    and r5.xyzw, r2.xyzw, l(0xff00ff00, 0xff00ff00, 0xff00ff00, 0xff00ff00)
    bfi r5.xyzw, l(8, 8, 8, 8), l(16, 16, 16, 16), r2.xyzw, r5.xyzw
    ubfe r6.xyzw, l(8, 8, 8, 8), l(16, 16, 16, 16), r2.xyzw
    iadd r2.xyzw, r5.xyzw, r6.xyzw
    and r5.xyzw, r4.xyzw, l(0xff00ff00, 0xff00ff00, 0xff00ff00, 0xff00ff00)
    bfi r5.xyzw, l(8, 8, 8, 8), l(16, 16, 16, 16), r4.xyzw, r5.xyzw
    ubfe r6.xyzw, l(8, 8, 8, 8), l(16, 16, 16, 16), r4.xyzw
    iadd r4.xyzw, r5.xyzw, r6.xyzw
    break 
    case l(2)
    case l(3)
    case l(10)
    case l(12)
    and r5.xyzw, r2.xyzw, l(0xc00ffc00, 0xc00ffc00, 0xc00ffc00, 0xc00ffc00)
    bfi r5.xyzw, l(10, 10, 10, 10), l(20, 20, 20, 20), r2.xyzw, r5.xyzw
    ubfe r6.xyzw, l(10, 10, 10, 10), l(20, 20, 20, 20), r2.xyzw
    iadd r2.xyzw, r5.xyzw, r6.xyzw
    and r5.xyzw, r4.xyzw, l(0xc00ffc00, 0xc00ffc00, 0xc00ffc00, 0xc00ffc00)
    bfi r5.xyzw, l(10, 10, 10, 10), l(20, 20, 20, 20), r4.xyzw, r5.xyzw
    ubfe r6.xyzw, l(10, 10, 10, 10), l(20, 20, 20, 20), r4.xyzw
    iadd r4.xyzw, r5.xyzw, r6.xyzw
    break 
    default 
    break 
  endswitch 
endif 
bfi r1.xyzw, l(2, 2, 2, 2), l(3, 3, 3, 3), r1.zxxz, l(0, 0, 0, 0)
iadd r0.xyzw, r0.xyzw, r1.xyzw
bfi r1.x, l(10), l(5), CB0[0][0].w, l(0)
and r1.y, CB0[0][0].z, l(8)
if_nz r1.y
  ubfe r1.y, l(3), l(4), CB0[0][0].z
  ushr r1.z, CB0[0][0].w, l(10)
  ishl r1.z, r1.z, l(5)
  ishr r5.xyzw, r0.zwzw, l(4, 5, 3, 3)
  ishr r1.w, r1.y, l(2)
  ushr r1.z, r1.z, l(4)
  and r1.z, r1.z, l(0x00007ffe)
  imad r1.z, r1.w, r1.z, r5.x
  ushr r3.x, r1.x, l(5)
  imad r1.z, r1.z, r3.x, r5.y
  ishl r3.x, r0.z, l(10)
  ishr r3.x, r3.x, l(6)
  and r3.x, r3.x, l(96)
  iadd r1.w, r1.w, r5.z
  bfi r3.y, l(1), l(1), r1.w, l(0)
  iadd r3.y, r3.y, r5.w
  bfi r3.y, l(2), l(1), r3.y, l(0)
  bfi r1.w, l(1), l(0), r1.w, r3.y
  bfi r3.yz, l(0, 20, 20, 0), l(0, 10, 13, 0), r1.zzzz, l(0, 0, 0, 0)
  imad r3.xy, r3.xxxx, l(2, 16, 0, 0), r3.yzyy
  bfi r1.yz, l(0, 2, 2, 0), l(0, 8, 11, 0), r1.yyyy, r3.xxyx
  bfi r3.x, l(1), l(4), r0.z, l(0)
  ubfe r3.y, l(3), l(6), r1.y
  and r3.z, r1.w, l(6)
  bfi r1.w, l(1), l(8), r1.w, l(0)
  imad r1.w, r3.y, l(32), r1.w
  imad r1.w, r3.z, l(4), r1.w
  bfi r1.yz, l(0, 6, 6, 0), l(0, 0, 3, 0), r3.xxxx, r1.yyzy
  bfi r1.z, l(9), l(3), r1.w, r1.z
  bfi r1.y, l(6), l(0), r1.y, r1.z
else 
  ishr r5.xyzw, r0.xyzw, l(5, 5, 2, 3)
  ushr r0.x, r1.x, l(5)
  imad r0.x, r5.y, r0.x, r5.x
  ishl r0.yw, r0.zzzz, l(0, 5, 0, 7)
  and r0.yw, r0.yyyw, l(0, 448, 0, 2048)
  bfi r1.x, l(23), l(9), r0.x, r0.y
  bfi r0.z, l(1), l(4), r0.z, l(0)
  iadd r1.x, r1.x, r0.z
  ishl r1.zw, r0.yyyy, l(0, 0, 3, 2)
  bfi r0.xy, l(23, 23, 0, 0), l(12, 11, 0, 0), r0.xxxx, r1.zwzz
  imad r0.xy, r0.zzzz, l(8, 4, 0, 0), r0.xyxx
  bfi r0.x, l(12), l(0), r0.w, r0.x
  and r0.y, r0.y, l(1792)
  iadd r0.x, r0.x, r0.y
  and r0.y, r5.z, l(2)
  iadd r0.y, r5.w, r0.y
  bfi r0.y, l(2), l(6), r0.y, l(0)
  iadd r0.x, r0.x, r0.y
  bfi r1.y, l(6), l(0), r1.x, r0.x
endif 
iadd r0.x, r1.y, CB0[0][1].x
ushr r0.x, r0.x, l(4)
ieq r0.yzw, r3.wwww, l(0, 1, 2, 3)
or r0.yz, r0.zzwz, r0.yyzy
if_nz r0.y
  ishl r1.xyzw, r2.xyzw, l(8, 8, 8, 8)
  and r1.xyzw, r1.xyzw, l(0xff00ff00, 0xff00ff00, 0xff00ff00, 0xff00ff00)
  ushr r3.xyzw, r2.xyzw, l(8, 8, 8, 8)
  and r3.xyzw, r3.xyzw, l(0x00ff00ff, 0x00ff00ff, 0x00ff00ff, 0x00ff00ff)
  iadd r2.xyzw, r1.xyzw, r3.xyzw
endif 
if_nz r0.z
  ushr r1.xyzw, r2.xyzw, l(16, 16, 16, 16)
  bfi r2.xyzw, l(16, 16, 16, 16), l(16, 16, 16, 16), r2.xyzw, r1.xyzw
endif 
store_uav_typed U0[0].xyzw, r0.xxxx, r2.xyzw
iadd r0.x, r0.x, l(2)
if_nz r0.y
  ishl r1.xyzw, r4.xyzw, l(8, 8, 8, 8)
  and r1.xyzw, r1.xyzw, l(0xff00ff00, 0xff00ff00, 0xff00ff00, 0xff00ff00)
  ushr r2.xyzw, r4.xyzw, l(8, 8, 8, 8)
  and r2.xyzw, r2.xyzw, l(0x00ff00ff, 0x00ff00ff, 0x00ff00ff, 0x00ff00ff)
  iadd r4.xyzw, r1.xyzw, r2.xyzw
endif 
if_nz r0.z
  ushr r1.xyzw, r4.xyzw, l(16, 16, 16, 16)
  bfi r4.xyzw, l(16, 16, 16, 16), l(16, 16, 16, 16), r4.xyzw, r1.xyzw
endif 
store_uav_typed U0[0].xyzw, r0.xxxx, r4.xyzw
ret 
// Approximately 163 instruction slots used
