//
// Generated by Microsoft (R) HLSL Shader Compiler 10.1
//
//
// Buffer Definitions: 
//
// cbuffer XeResolveConstants
// {
//
//   uint xe_resolve_edram_info;        // Offset:    0 Size:     4
//   uint xe_resolve_address_info;      // Offset:    4 Size:     4
//   uint xe_resolve_dest_info;         // Offset:    8 Size:     4
//   uint xe_resolve_dest_pitch_aligned;// Offset:   12 Size:     4
//
// }
//
//
// Resource Bindings:
//
// Name                                 Type  Format         Dim      ID      HLSL Bind  Count
// ------------------------------ ---------- ------- ----------- ------- -------------- ------
// xe_resolve_source                 texture   uint2         buf      T0             t0      1 
// xe_resolve_dest                       UAV   uint2         buf      U0             u0      1 
// XeResolveConstants                cbuffer      NA          NA     CB0            cb0      1 
//
//
//
// Input signature:
//
// Name                 Index   Mask Register SysValue  Format   Used
// -------------------- ----- ------ -------- -------- ------- ------
// no Input
//
// Output signature:
//
// Name                 Index   Mask Register SysValue  Format   Used
// -------------------- ----- ------ -------- -------- ------- ------
// no Output
cs_5_1
dcl_globalFlags refactoringAllowed
dcl_constantbuffer CB0[0:0][1], immediateIndexed, space=0
dcl_resource_buffer (uint,uint,uint,uint) T0[0:0], space=0
dcl_uav_typed_buffer (uint,uint,uint,uint) U0[0:0], space=0
dcl_input vThreadID.xy
dcl_temps 9
dcl_thread_group 8, 8, 1
ishl r0.xw, vThreadID.xxxx, l(1, 0, 0, 1)
ushr r1.x, CB0[0][0].y, l(7)
bfi r1.x, l(11), l(3), r1.x, l(0)
uge r1.x, r0.w, r1.x
if_nz r1.x
  ret 
endif 
ushr r1.xy, CB0[0][0].yyyy, l(5, 29, 0, 0)
mov r1.z, CB0[0][0].y
bfi r2.xy, l(5, 2, 0, 0), l(3, 3, 0, 0), r1.zxzz, l(0, 0, 0, 0)
mov r0.yz, vThreadID.yyyy
iadd r2.xy, r0.wzww, r2.xyxx
ubfe r2.zw, l(0, 0, 12, 2), l(0, 0, 13, 10), CB0[0][0].xxxx
and r3.xyzw, CB0[0][0].xxzx, l(1023, 4096, 0x01000000, 0x40000000)
uge r1.w, l(3), r1.y
if_nz r1.w
  mov r4.y, r1.y
else 
  ieq r1.w, r1.y, l(5)
  if_nz r1.w
    mov r4.y, l(2)
  else 
    mov r4.y, l(0)
  endif 
endif 
uge r1.yw, r2.wwww, l(0, 2, 0, 1)
and r1.yw, r1.yyyw, l(0, 1, 0, 1)
ishl r1.yw, r2.xxxy, r1.yyyw
ushr r4.x, r4.y, l(1)
and r2.xy, r4.xyxx, l(1, 1, 0, 0)
iadd r1.yw, r1.yyyw, r2.xxxy
udiv r2.xy, null, r1.ywyy, l(80, 16, 0, 0)
imad r2.w, r2.y, r3.x, r2.x
iadd r2.z, r2.w, r2.z
imad r1.yw, -r2.xxxy, l(0, 80, 0, 16), r1.yyyw
if_nz r3.y
  uge r2.x, r1.y, l(40)
  movc r2.x, r2.x, l(-40), l(40)
  iadd r1.y, r1.y, r2.x
endif 
imad r1.y, r1.w, l(80), r1.y
imad r1.y, r2.z, l(1280), r1.y
imul null, r1.y, r1.y, l(9)
ushr r1.y, r1.y, l(1)
ld r2.xy, r1.yyyy, T0[0].xyzw
iadd r4.xyzw, r1.yyyy, l(1, 2, 3, 4)
ld r2.zw, r4.xxxx, T0[0].zwxy
ld r5.xy, r4.yyyy, T0[0].xywz
ld r5.zw, r4.zzzz, T0[0].zwxy
ld r4.xy, r4.wwww, T0[0].yxzw
iadd r6.xyzw, r1.yyyy, l(5, 6, 7, 8)
ld r4.zw, r6.xxxx, T0[0].zwxy
ld r7.xy, r6.yyyy, T0[0].xyzw
ld r7.zw, r6.zzzz, T0[0].zwxy
ld r1.yw, r6.wwww, T0[0].zxwy
if_nz r3.z
  ubfe r3.x, l(4), l(25), CB0[0][0].x
  switch r3.x
    case l(0)
    case l(1)
    and r6.xyzw, r2.xyzw, l(0xff00ff00, 0xff00ff00, 0xff00ff00, 0xff00ff00)
    bfi r6.xyzw, l(8, 8, 8, 8), l(16, 16, 16, 16), r2.xyzw, r6.xyzw
    ubfe r8.xyzw, l(8, 8, 8, 8), l(16, 16, 16, 16), r2.xyzw
    iadd r2.xyzw, r6.xyzw, r8.xyzw
    and r6.xyzw, r5.xyzw, l(0xff00ff00, 0xff00ff00, 0xff00ff00, 0xff00ff00)
    bfi r6.xyzw, l(8, 8, 8, 8), l(16, 16, 16, 16), r5.xyzw, r6.xyzw
    ubfe r8.xyzw, l(8, 8, 8, 8), l(16, 16, 16, 16), r5.xyzw
    iadd r5.xyzw, r6.xyzw, r8.xyzw
    mov r4.xyzw, r4.yxzw
    and r6.xyzw, r4.xyzw, l(0xff00ff00, 0xff00ff00, 0xff00ff00, 0xff00ff00)
    bfi r6.xyzw, l(8, 8, 8, 8), l(16, 16, 16, 16), r4.xyzw, r6.xyzw
    ubfe r8.xyzw, l(8, 8, 8, 8), l(16, 16, 16, 16), r4.xyzw
    iadd r4.xyzw, r6.yxzw, r8.yxzw
    and r6.xyzw, r7.xyzw, l(0xff00ff00, 0xff00ff00, 0xff00ff00, 0xff00ff00)
    bfi r6.xyzw, l(8, 8, 8, 8), l(16, 16, 16, 16), r7.xyzw, r6.xyzw
    ubfe r8.xyzw, l(8, 8, 8, 8), l(16, 16, 16, 16), r7.xyzw
    iadd r7.xyzw, r6.xyzw, r8.xyzw
    and r3.xy, r1.ywyy, l(0xff00ff00, 0xff00ff00, 0, 0)
    bfi r3.xy, l(8, 8, 0, 0), l(16, 16, 0, 0), r1.ywyy, r3.xyxx
    ubfe r6.xy, l(8, 8, 0, 0), l(16, 16, 0, 0), r1.ywyy
    iadd r1.yw, r3.xxxy, r6.xxxy
    break 
    case l(2)
    case l(3)
    case l(10)
    case l(12)
    and r6.xyzw, r2.xyzw, l(0xc00ffc00, 0xc00ffc00, 0xc00ffc00, 0xc00ffc00)
    bfi r6.xyzw, l(10, 10, 10, 10), l(20, 20, 20, 20), r2.xyzw, r6.xyzw
    ubfe r8.xyzw, l(10, 10, 10, 10), l(20, 20, 20, 20), r2.xyzw
    iadd r2.xyzw, r6.xyzw, r8.xyzw
    and r6.xyzw, r5.xyzw, l(0xc00ffc00, 0xc00ffc00, 0xc00ffc00, 0xc00ffc00)
    bfi r6.xyzw, l(10, 10, 10, 10), l(20, 20, 20, 20), r5.xyzw, r6.xyzw
    ubfe r8.xyzw, l(10, 10, 10, 10), l(20, 20, 20, 20), r5.xyzw
    iadd r5.xyzw, r6.xyzw, r8.xyzw
    mov r4.xyzw, r4.yxzw
    and r6.xyzw, r4.xyzw, l(0xc00ffc00, 0xc00ffc00, 0xc00ffc00, 0xc00ffc00)
    bfi r6.xyzw, l(10, 10, 10, 10), l(20, 20, 20, 20), r4.xyzw, r6.xyzw
    ubfe r8.xyzw, l(10, 10, 10, 10), l(20, 20, 20, 20), r4.xyzw
    iadd r4.xyzw, r6.yxzw, r8.yxzw
    and r6.xyzw, r7.xyzw, l(0xc00ffc00, 0xc00ffc00, 0xc00ffc00, 0xc00ffc00)
    bfi r6.xyzw, l(10, 10, 10, 10), l(20, 20, 20, 20), r7.xyzw, r6.xyzw
    ubfe r8.xyzw, l(10, 10, 10, 10), l(20, 20, 20, 20), r7.xyzw
    iadd r7.xyzw, r6.xyzw, r8.xyzw
    and r3.xy, r1.ywyy, l(0xc00ffc00, 0xc00ffc00, 0, 0)
    bfi r3.xy, l(10, 10, 0, 0), l(20, 20, 0, 0), r1.ywyy, r3.xyxx
    ubfe r6.xy, l(10, 10, 0, 0), l(20, 20, 0, 0), r1.ywyy
    iadd r1.yw, r3.xxxy, r6.xxxy
    break 
    default 
    break 
  endswitch 
endif 
if_nz r3.w
  if_z r0.w
    mov r2.x, r2.y
    mov r5.z, r5.x
    mov r3.x, r5.w
  else 
    mov r3.x, r5.z
    mov r5.z, r2.w
  endif 
  if_z vThreadID.y
    mov r2.xyz, r5.zxyz
    mov r4.xzw, r7.xxyz
  endif 
  mov r2.w, r5.z
  mov r5.z, r3.x
endif 
bfi r3.xyzw, l(2, 2, 2, 2), l(3, 3, 3, 3), r1.zxxz, l(0, 0, 0, 0)
iadd r0.xyzw, r0.xyzw, r3.xyzw
bfi r1.x, l(10), l(5), CB0[0][0].w, l(0)
and r3.xy, CB0[0][0].zzzz, l(7, 8, 0, 0)
if_nz r3.y
  ubfe r1.z, l(3), l(4), CB0[0][0].z
  ushr r3.y, CB0[0][0].w, l(10)
  ishl r3.y, r3.y, l(5)
  ishr r6.xyzw, r0.zwzw, l(4, 5, 3, 3)
  ishr r3.z, r1.z, l(2)
  ushr r3.y, r3.y, l(4)
  and r3.y, r3.y, l(0x00007ffe)
  imad r3.y, r3.z, r3.y, r6.x
  ushr r3.w, r1.x, l(5)
  imad r3.y, r3.y, r3.w, r6.y
  ishl r3.w, r0.z, l(10)
  and r3.w, r3.w, l(6144)
  bfi r3.w, l(3), l(8), r0.w, r3.w
  ishr r3.w, r3.w, l(6)
  iadd r3.z, r3.z, r6.z
  bfi r6.xyz, l(1, 20, 20, 0), l(1, 10, 13, 0), r3.zyyz, l(0, 0, 0, 0)
  iadd r6.x, r6.x, r6.w
  bfi r6.x, l(2), l(1), r6.x, l(0)
  bfi r3.z, l(1), l(0), r3.z, r6.x
  and r6.x, r3.w, l(112)
  imad r6.xy, r6.xxxx, l(2, 16, 0, 0), r6.yzyy
  bfi r3.yw, l(0, 4, 0, 4), l(0, 0, 0, 3), r3.wwww, r6.xxxy
  bfi r3.yw, l(0, 2, 0, 2), l(0, 8, 0, 11), r1.zzzz, r3.yyyw
  ubfe r1.z, l(3), l(6), r3.y
  and r6.x, r3.z, l(6)
  bfi r3.z, l(1), l(8), r3.z, l(0)
  imad r1.z, r1.z, l(32), r3.z
  imad r1.z, r6.x, l(4), r1.z
  bfi r3.yz, l(0, 1, 1, 0), l(0, 4, 7, 0), r0.zzzz, r3.yywy
  bfi r1.z, l(9), l(3), r1.z, r3.z
  bfi r1.z, l(6), l(0), r3.y, r1.z
else 
  ishr r6.xyzw, r0.xyzw, l(5, 5, 2, 3)
  ushr r0.x, r1.x, l(5)
  imad r0.x, r6.y, r0.x, r6.x
  ishl r3.yz, r0.zzzz, l(0, 4, 7, 0)
  and r3.yz, r3.yyzy, l(0, 224, 2048, 0)
  bfi r0.y, l(3), l(2), r0.w, r3.y
  ishl r1.x, r3.y, l(1)
  bfi r0.w, l(3), l(3), r0.w, r1.x
  and r0.w, r0.w, l(480)
  bfi r1.x, l(23), l(9), r0.x, r0.w
  bfi r1.x, l(4), l(0), r0.y, r1.x
  bfi r1.x, l(1), l(4), r0.z, r1.x
  ishl r3.yw, r0.wwww, l(0, 3, 0, 2)
  bfi r0.xw, l(23, 0, 0, 23), l(12, 0, 0, 11), r0.xxxx, r3.yyyw
  bfi r0.xy, l(4, 4, 0, 0), l(3, 2, 0, 0), r0.yyyy, r0.xwxx
  bfi r0.xy, l(1, 1, 0, 0), l(7, 6, 0, 0), r0.zzzz, r0.xyxx
  bfi r0.x, l(12), l(0), r3.z, r0.x
  and r0.y, r0.y, l(1792)
  iadd r0.x, r0.x, r0.y
  and r0.y, r6.z, l(2)
  iadd r0.y, r6.w, r0.y
  bfi r0.y, l(2), l(6), r0.y, l(0)
  iadd r0.x, r0.x, r0.y
  bfi r1.z, l(6), l(0), r1.x, r0.x
endif 
imul null, r0.x, r1.z, l(9)
ushr r0.x, r0.x, l(3)
ieq r0.yzw, r3.xxxx, l(0, 1, 2, 3)
or r0.yz, r0.zzwz, r0.yyzy
if_nz r0.y
  ishl r3.xyzw, r2.xyzw, l(8, 8, 8, 8)
  and r3.xyzw, r3.xyzw, l(0xff00ff00, 0xff00ff00, 0xff00ff00, 0xff00ff00)
  ushr r6.xyzw, r2.xyzw, l(8, 8, 8, 8)
  and r6.xyzw, r6.xyzw, l(0x00ff00ff, 0x00ff00ff, 0x00ff00ff, 0x00ff00ff)
  iadd r2.xyzw, r3.xyzw, r6.xyzw
endif 
if_nz r0.z
  ushr r3.xyzw, r2.xyzw, l(16, 16, 16, 16)
  bfi r2.xyzw, l(16, 16, 16, 16), l(16, 16, 16, 16), r2.xyzw, r3.xyzw
endif 
if_nz r0.y
  ishl r3.xyzw, r5.xyzw, l(8, 8, 8, 8)
  and r3.xyzw, r3.xyzw, l(0xff00ff00, 0xff00ff00, 0xff00ff00, 0xff00ff00)
  ushr r6.xyzw, r5.xyzw, l(8, 8, 8, 8)
  and r6.xyzw, r6.xyzw, l(0x00ff00ff, 0x00ff00ff, 0x00ff00ff, 0x00ff00ff)
  iadd r5.xyzw, r3.xyzw, r6.xyzw
endif 
if_nz r0.z
  ushr r3.xyzw, r5.xyzw, l(16, 16, 16, 16)
  bfi r5.xyzw, l(16, 16, 16, 16), l(16, 16, 16, 16), r5.xyzw, r3.xyzw
endif 
if_nz r0.y
  ishl r3.xyzw, r4.yxzw, l(8, 8, 8, 8)
  and r3.xyzw, r3.xyzw, l(0xff00ff00, 0xff00ff00, 0xff00ff00, 0xff00ff00)
  ushr r6.xyzw, r4.yxzw, l(8, 8, 8, 8)
  and r6.xyzw, r6.xyzw, l(0x00ff00ff, 0x00ff00ff, 0x00ff00ff, 0x00ff00ff)
  iadd r4.xyzw, r3.yxzw, r6.yxzw
endif 
if_nz r0.z
  ushr r3.xyzw, r4.yxzw, l(16, 16, 16, 16)
  bfi r4.xyzw, l(16, 16, 16, 16), l(16, 16, 16, 16), r4.xyzw, r3.yxzw
endif 
if_nz r0.y
  ishl r3.xyzw, r7.xyzw, l(8, 8, 8, 8)
  and r3.xyzw, r3.xyzw, l(0xff00ff00, 0xff00ff00, 0xff00ff00, 0xff00ff00)
  ushr r6.xyzw, r7.xyzw, l(8, 8, 8, 8)
  and r6.xyzw, r6.xyzw, l(0x00ff00ff, 0x00ff00ff, 0x00ff00ff, 0x00ff00ff)
  iadd r7.xyzw, r3.xyzw, r6.xyzw
endif 
if_nz r0.z
  ushr r3.xyzw, r7.xyzw, l(16, 16, 16, 16)
  bfi r7.xyzw, l(16, 16, 16, 16), l(16, 16, 16, 16), r7.xyzw, r3.xyzw
endif 
if_nz r0.y
  ishl r0.yw, r1.yyyw, l(0, 8, 0, 8)
  and r0.yw, r0.yyyw, l(0, 0xff00ff00, 0, 0xff00ff00)
  ushr r1.xz, r1.yywy, l(8, 0, 8, 0)
  and r1.xz, r1.xxzx, l(0x00ff00ff, 0, 0x00ff00ff, 0)
  iadd r1.yw, r0.yyyw, r1.xxxz
endif 
if_nz r0.z
  ushr r0.yz, r1.yywy, l(0, 16, 16, 0)
  bfi r1.yw, l(0, 16, 0, 16), l(0, 16, 0, 16), r1.yyyw, r0.yyyz
endif 
store_uav_typed U0[0].xyzw, r0.xxxx, r2.xyxx
iadd r3.xyzw, r0.xxxx, l(1, 2, 3, 4)
store_uav_typed U0[0].xyzw, r3.xxxx, r2.zwzz
store_uav_typed U0[0].xyzw, r3.yyyy, r5.xyxx
store_uav_typed U0[0].xyzw, r3.zzzz, r5.zwzz
store_uav_typed U0[0].xyzw, r3.wwww, r4.yxyy
iadd r2.xyzw, r0.xxxx, l(5, 6, 7, 8)
store_uav_typed U0[0].xyzw, r2.xxxx, r4.zwzz
store_uav_typed U0[0].xyzw, r2.yyyy, r7.xyxx
store_uav_typed U0[0].xyzw, r2.zzzz, r7.zwzz
store_uav_typed U0[0].xyzw, r2.wwww, r1.ywyy
ret 
// Approximately 261 instruction slots used
