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[A64] Add v8-v15 to allocatable VEC pool

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Expands the vector register allocator from 20 to 28 registers by
including v8-v15. The HostToGuestThunk now saves/restores full Q8-Q15
(128-bit) instead of just D8-D15, and the GuestToHostThunk adds Q8-Q15
to its save/restore set since AAPCS64 only preserves their lower 64
bits across C calls.

Reduces register pressure for VMX-heavy guest code at the cost of
slightly larger thunk stack frames.
This commit is contained in:
Herman S.
2026-03-24 15:12:10 +09:00
parent 756ae7a558
commit 02d2cb5cc4
4 changed files with 74 additions and 71 deletions
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4
src/xenia/cpu/backend/a64/a64_emitter.h
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@@ -75,8 +75,8 @@ class A64Emitter : public Xbyak_aarch64::CodeGenerator {
// Scratch: x0-x18 (caller-saved), v0-v3
// Available GPRs for register allocator: x22-x28
static constexpr int GPR_COUNT = 7;
// Available VEC regs: v4-v7, v16-v31
static constexpr int VEC_COUNT = 20;
// Available VEC regs: v4-v15, v16-v31
static constexpr int VEC_COUNT = 28;
static constexpr size_t kStashOffset = 32;
static void SetupReg(const hir::Value* v, Xbyak_aarch64::WReg& r) {