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Renaming xe::cpu::frontend to xe::cpu::ppc.

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This commit is contained in:
Ben Vanik
2015-12-14 21:17:55 -08:00
parent 9273359cdd
commit 15816327b4
225 changed files with 196 additions and 204 deletions
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205
src/xenia/cpu/ppc/testing/instr_andc.s Normal file
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test_andc_1:
#_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF
#_ REGISTER_IN r25 0xFFFFFFFFFFFFFFFF
andc r11, r5, r25
blr
#_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r25 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r11 0
test_andc_1_constant:
li r5, -1
li r25, -1
andc r11, r5, r25
blr
#_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r25 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r11 0
test_andc_2:
#_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF
#_ REGISTER_IN r25 0
andc r11, r5, r25
blr
#_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r25 0
#_ REGISTER_OUT r11 0xFFFFFFFFFFFFFFFF
test_andc_2_constant:
li r5, -1
li r25, 0
andc r11, r5, r25
blr
#_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r25 0
#_ REGISTER_OUT r11 0xFFFFFFFFFFFFFFFF
test_andc_3:
#_ REGISTER_IN r5 0
#_ REGISTER_IN r25 0xFFFFFFFFFFFFFFFF
andc r11, r5, r25
blr
#_ REGISTER_OUT r5 0
#_ REGISTER_OUT r25 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r11 0
test_andc_3_constant:
li r5, 0
li r25, -1
andc r11, r5, r25
blr
#_ REGISTER_OUT r5 0
#_ REGISTER_OUT r25 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r11 0
test_andc_4:
#_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF
#_ REGISTER_IN r25 0x0000FFFF
andc r11, r5, r25
blr
#_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r25 0x0000FFFF
#_ REGISTER_OUT r11 0xFFFFFFFFFFFF0000
test_andc_4_constant:
li r5, -1
li r25, -1
clrldi r25, r25, 48
andc r11, r5, r25
blr
#_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r25 0x0000FFFF
#_ REGISTER_OUT r11 0xFFFFFFFFFFFF0000
test_andc_5:
#_ REGISTER_IN r0 0x100000FF
#_ REGISTER_IN r25 0x0000FFFF
andc r11, r0, r25
blr
#_ REGISTER_OUT r0 0x100000FF
#_ REGISTER_OUT r25 0x0000FFFF
#_ REGISTER_OUT r11 0x10000000
test_andc_5_constant:
lis r0, 0x1000
ori r0, r0, 0xFF
li r25, -1
clrldi r25, r25, 48
andc r11, r0, r25
blr
#_ REGISTER_OUT r0 0x100000FF
#_ REGISTER_OUT r25 0x0000FFFF
#_ REGISTER_OUT r11 0x10000000
test_andc_cr_1:
#_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF
#_ REGISTER_IN r25 0xFFFFFFFFFFFFFFFF
andc. r11, r5, r25
mfcr r12
blr
#_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r25 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r11 0
#_ REGISTER_OUT r12 0x20000000
test_andc_cr_1_constant:
li r5, -1
li r25, -1
andc. r11, r5, r25
mfcr r12
blr
#_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r25 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r11 0
#_ REGISTER_OUT r12 0x20000000
test_andc_cr_2:
#_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF
#_ REGISTER_IN r25 0
andc. r11, r5, r25
mfcr r12
blr
#_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r25 0
#_ REGISTER_OUT r11 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r12 0x80000000
test_andc_cr_2_constant:
li r5, -1
li r25, 0
andc. r11, r5, r25
mfcr r12
blr
#_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r25 0
#_ REGISTER_OUT r11 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r12 0x80000000
test_andc_cr_3:
#_ REGISTER_IN r5 0
#_ REGISTER_IN r25 0xFFFFFFFFFFFFFFFF
andc. r11, r5, r25
mfcr r12
blr
#_ REGISTER_OUT r5 0
#_ REGISTER_OUT r25 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r11 0
#_ REGISTER_OUT r12 0x20000000
test_andc_cr_3_constant:
li r5, 0
li r25, -1
andc. r11, r5, r25
mfcr r12
blr
#_ REGISTER_OUT r5 0
#_ REGISTER_OUT r25 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r11 0
#_ REGISTER_OUT r12 0x20000000
test_andc_cr_4:
#_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF
#_ REGISTER_IN r25 0x0000FFFF
andc. r11, r5, r25
mfcr r12
blr
#_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r25 0x0000FFFF
#_ REGISTER_OUT r11 0xFFFFFFFFFFFF0000
#_ REGISTER_OUT r12 0x80000000
test_andc_cr_4_constant:
li r5, -1
li r25, -1
clrldi r25, r25, 48
andc. r11, r5, r25
mfcr r12
blr
#_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r25 0x0000FFFF
#_ REGISTER_OUT r11 0xFFFFFFFFFFFF0000
#_ REGISTER_OUT r12 0x80000000
test_andc_cr_5:
#_ REGISTER_IN r0 0x100000FF
#_ REGISTER_IN r25 0x0000FFFF
andc. r11, r0, r25
mfcr r12
blr
#_ REGISTER_OUT r0 0x100000FF
#_ REGISTER_OUT r25 0x0000FFFF
#_ REGISTER_OUT r11 0x10000000
#_ REGISTER_OUT r12 0x40000000
test_andc_cr_5_constant:
lis r0, 0x1000
ori r0, r0, 0xFF
li r25, -1
clrldi r25, r25, 48
andc. r11, r0, r25
mfcr r12
blr
#_ REGISTER_OUT r0 0x100000FF
#_ REGISTER_OUT r25 0x0000FFFF
#_ REGISTER_OUT r11 0x10000000
#_ REGISTER_OUT r12 0x40000000